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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-unroll -mcpu=apple-m1 -S %s | FileCheck --check-prefix=APPLE %s3; RUN: opt -p loop-unroll -mcpu=apple-m2 -S %s | FileCheck --check-prefix=APPLE %s4; RUN: opt -p loop-unroll -mcpu=apple-m3 -S %s | FileCheck --check-prefix=APPLE %s5; RUN: opt -p loop-unroll -mcpu=apple-m4 -S %s | FileCheck --check-prefix=APPLE %s6; RUN: opt -p loop-unroll -mcpu=cortex-a57 -S %s | FileCheck --check-prefix=OTHER %s7 8target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"9target triple = "arm64-apple-macosx15.0.0"10 11define void @small_load_store_loop(ptr %src, ptr %dst, i64 %N, i64 %scale) {12; APPLE-LABEL: define void @small_load_store_loop(13; APPLE-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]], i64 [[SCALE:%.*]]) #[[ATTR0:[0-9]+]] {14; APPLE-NEXT: [[ENTRY:.*]]:15; APPLE-NEXT: [[TMP0:%.*]] = add i64 [[N]], -116; APPLE-NEXT: [[XTRAITER:%.*]] = and i64 [[N]], 717; APPLE-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 718; APPLE-NEXT: br i1 [[TMP1]], label %[[LOOP_EPIL_PREHEADER:.*]], label %[[ENTRY_NEW:.*]]19; APPLE: [[ENTRY_NEW]]:20; APPLE-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[N]], [[XTRAITER]]21; APPLE-NEXT: br label %[[LOOP:.*]]22; APPLE: [[LOOP]]:23; APPLE-NEXT: [[IV_EPIL:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[IV_NEXT_7:%.*]], %[[LOOP]] ]24; APPLE-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_7:%.*]], %[[LOOP]] ]25; APPLE-NEXT: [[SCALED_IV_EPIL:%.*]] = mul nuw nsw i64 [[IV_EPIL]], [[SCALE]]26; APPLE-NEXT: [[GEP_SRC_EPIL:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_EPIL]]27; APPLE-NEXT: [[L_EPIL:%.*]] = load float, ptr [[GEP_SRC_EPIL]], align 428; APPLE-NEXT: [[GEP_DST_EPIL:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_EPIL]]29; APPLE-NEXT: store float [[L_EPIL]], ptr [[GEP_DST_EPIL]], align 430; APPLE-NEXT: [[IV_NEXT_EPIL:%.*]] = add nuw nsw i64 [[IV_EPIL]], 131; APPLE-NEXT: [[SCALED_IV_1:%.*]] = mul nuw nsw i64 [[IV_NEXT_EPIL]], [[SCALE]]32; APPLE-NEXT: [[GEP_SRC_1:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_1]]33; APPLE-NEXT: [[L_1:%.*]] = load float, ptr [[GEP_SRC_1]], align 434; APPLE-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT_EPIL]]35; APPLE-NEXT: store float [[L_1]], ptr [[GEP_DST_1]], align 436; APPLE-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i64 [[IV_EPIL]], 237; APPLE-NEXT: [[SCALED_IV_2:%.*]] = mul nuw nsw i64 [[IV_NEXT_1]], [[SCALE]]38; APPLE-NEXT: [[GEP_SRC_2:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_2]]39; APPLE-NEXT: [[L_2:%.*]] = load float, ptr [[GEP_SRC_2]], align 440; APPLE-NEXT: [[GEP_DST_2:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT_1]]41; APPLE-NEXT: store float [[L_2]], ptr [[GEP_DST_2]], align 442; APPLE-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i64 [[IV_EPIL]], 343; APPLE-NEXT: [[SCALED_IV_3:%.*]] = mul nuw nsw i64 [[IV_NEXT_2]], [[SCALE]]44; APPLE-NEXT: [[GEP_SRC_3:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_3]]45; APPLE-NEXT: [[L_3:%.*]] = load float, ptr [[GEP_SRC_3]], align 446; APPLE-NEXT: [[GEP_DST_3:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT_2]]47; APPLE-NEXT: store float [[L_3]], ptr [[GEP_DST_3]], align 448; APPLE-NEXT: [[IV_NEXT_3:%.*]] = add nuw nsw i64 [[IV_EPIL]], 449; APPLE-NEXT: [[SCALED_IV_4:%.*]] = mul nuw nsw i64 [[IV_NEXT_3]], [[SCALE]]50; APPLE-NEXT: [[GEP_SRC_4:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_4]]51; APPLE-NEXT: [[L_4:%.*]] = load float, ptr [[GEP_SRC_4]], align 452; APPLE-NEXT: [[GEP_DST_4:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT_3]]53; APPLE-NEXT: store float [[L_4]], ptr [[GEP_DST_4]], align 454; APPLE-NEXT: [[IV_NEXT_4:%.*]] = add nuw nsw i64 [[IV_EPIL]], 555; APPLE-NEXT: [[SCALED_IV_5:%.*]] = mul nuw nsw i64 [[IV_NEXT_4]], [[SCALE]]56; APPLE-NEXT: [[GEP_SRC_5:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_5]]57; APPLE-NEXT: [[L_5:%.*]] = load float, ptr [[GEP_SRC_5]], align 458; APPLE-NEXT: [[GEP_DST_5:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT_4]]59; APPLE-NEXT: store float [[L_5]], ptr [[GEP_DST_5]], align 460; APPLE-NEXT: [[IV_NEXT_5:%.*]] = add nuw nsw i64 [[IV_EPIL]], 661; APPLE-NEXT: [[SCALED_IV_6:%.*]] = mul nuw nsw i64 [[IV_NEXT_5]], [[SCALE]]62; APPLE-NEXT: [[GEP_SRC_6:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_6]]63; APPLE-NEXT: [[L_6:%.*]] = load float, ptr [[GEP_SRC_6]], align 464; APPLE-NEXT: [[GEP_DST_6:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT_5]]65; APPLE-NEXT: store float [[L_6]], ptr [[GEP_DST_6]], align 466; APPLE-NEXT: [[IV_NEXT_6:%.*]] = add nuw nsw i64 [[IV_EPIL]], 767; APPLE-NEXT: [[SCALED_IV_7:%.*]] = mul nuw nsw i64 [[IV_NEXT_6]], [[SCALE]]68; APPLE-NEXT: [[GEP_SRC_7:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_7]]69; APPLE-NEXT: [[L_7:%.*]] = load float, ptr [[GEP_SRC_7]], align 470; APPLE-NEXT: [[GEP_DST_7:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT_6]]71; APPLE-NEXT: store float [[L_7]], ptr [[GEP_DST_7]], align 472; APPLE-NEXT: [[IV_NEXT_7]] = add nuw nsw i64 [[IV_EPIL]], 873; APPLE-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 874; APPLE-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]75; APPLE-NEXT: br i1 [[NITER_NCMP_7]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]76; APPLE: [[EXIT_UNR_LCSSA]]:77; APPLE-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_7]], %[[LOOP]] ]78; APPLE-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 079; APPLE-NEXT: br i1 [[LCMP_MOD]], label %[[LOOP_EPIL_PREHEADER]], label %[[EXIT:.*]]80; APPLE: [[LOOP_EPIL_PREHEADER]]:81; APPLE-NEXT: [[IV_EPIL_INIT:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_UNR]], %[[EXIT_UNR_LCSSA]] ]82; APPLE-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i64 [[XTRAITER]], 083; APPLE-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]])84; APPLE-NEXT: br label %[[LOOP_EPIL:.*]]85; APPLE: [[LOOP_EPIL]]:86; APPLE-NEXT: [[IV_EPIL1:%.*]] = phi i64 [ [[IV_EPIL_INIT]], %[[LOOP_EPIL_PREHEADER]] ], [ [[IV_NEXT_EPIL1:%.*]], %[[LOOP_EPIL]] ]87; APPLE-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ 0, %[[LOOP_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], %[[LOOP_EPIL]] ]88; APPLE-NEXT: [[SCALED_IV_EPIL1:%.*]] = mul nuw nsw i64 [[IV_EPIL1]], [[SCALE]]89; APPLE-NEXT: [[GEP_SRC_EPIL1:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_EPIL1]]90; APPLE-NEXT: [[L_EPIL1:%.*]] = load float, ptr [[GEP_SRC_EPIL1]], align 491; APPLE-NEXT: [[GEP_DST_EPIL1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_EPIL1]]92; APPLE-NEXT: store float [[L_EPIL1]], ptr [[GEP_DST_EPIL1]], align 493; APPLE-NEXT: [[IV_NEXT_EPIL1]] = add nuw nsw i64 [[IV_EPIL1]], 194; APPLE-NEXT: [[EC_EPIL:%.*]] = icmp eq i64 [[IV_NEXT_EPIL1]], [[N]]95; APPLE-NEXT: [[EPIL_ITER_NEXT]] = add i64 [[EPIL_ITER]], 196; APPLE-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i64 [[EPIL_ITER_NEXT]], [[XTRAITER]]97; APPLE-NEXT: br i1 [[EPIL_ITER_CMP]], label %[[LOOP_EPIL]], label %[[EXIT_EPILOG_LCSSA:.*]], !llvm.loop [[LOOP0:![0-9]+]]98; APPLE: [[EXIT_EPILOG_LCSSA]]:99; APPLE-NEXT: br label %[[EXIT]]100; APPLE: [[EXIT]]:101; APPLE-NEXT: ret void102;103; OTHER-LABEL: define void @small_load_store_loop(104; OTHER-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]], i64 [[SCALE:%.*]]) #[[ATTR0:[0-9]+]] {105; OTHER-NEXT: [[ENTRY:.*]]:106; OTHER-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1107; OTHER-NEXT: [[XTRAITER:%.*]] = and i64 [[N]], 1108; OTHER-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 1109; OTHER-NEXT: br i1 [[TMP1]], label %[[LOOP_EPIL_PREHEADER:.*]], label %[[ENTRY_NEW:.*]]110; OTHER: [[ENTRY_NEW]]:111; OTHER-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[N]], [[XTRAITER]]112; OTHER-NEXT: br label %[[LOOP:.*]]113; OTHER: [[LOOP]]:114; OTHER-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[IV_NEXT_1:%.*]], %[[LOOP]] ]115; OTHER-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_1:%.*]], %[[LOOP]] ]116; OTHER-NEXT: [[SCALED_IV:%.*]] = mul nuw nsw i64 [[IV]], [[SCALE]]117; OTHER-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV]]118; OTHER-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4119; OTHER-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV]]120; OTHER-NEXT: store float [[L]], ptr [[GEP_DST]], align 4121; OTHER-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 1122; OTHER-NEXT: [[SCALED_IV_1:%.*]] = mul nuw nsw i64 [[IV_NEXT]], [[SCALE]]123; OTHER-NEXT: [[GEP_SRC_1:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_1]]124; OTHER-NEXT: [[L_1:%.*]] = load float, ptr [[GEP_SRC_1]], align 4125; OTHER-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT]]126; OTHER-NEXT: store float [[L_1]], ptr [[GEP_DST_1]], align 4127; OTHER-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2128; OTHER-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2129; OTHER-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]130; OTHER-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]131; OTHER: [[EXIT_UNR_LCSSA]]:132; OTHER-NEXT: [[IV_UNR1:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]133; OTHER-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0134; OTHER-NEXT: br i1 [[LCMP_MOD]], label %[[LOOP_EPIL_PREHEADER]], label %[[EXIT:.*]]135; OTHER: [[LOOP_EPIL_PREHEADER]]:136; OTHER-NEXT: [[IV_UNR:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_UNR1]], %[[EXIT_UNR_LCSSA]] ]137; OTHER-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i64 [[XTRAITER]], 0138; OTHER-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]])139; OTHER-NEXT: br label %[[LOOP_EPIL:.*]]140; OTHER: [[LOOP_EPIL]]:141; OTHER-NEXT: [[SCALED_IV_EPIL:%.*]] = mul nuw nsw i64 [[IV_UNR]], [[SCALE]]142; OTHER-NEXT: [[GEP_SRC_EPIL:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_EPIL]]143; OTHER-NEXT: [[L_EPIL:%.*]] = load float, ptr [[GEP_SRC_EPIL]], align 4144; OTHER-NEXT: [[GEP_DST_EPIL:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_UNR]]145; OTHER-NEXT: store float [[L_EPIL]], ptr [[GEP_DST_EPIL]], align 4146; OTHER-NEXT: br label %[[EXIT]]147; OTHER: [[EXIT]]:148; OTHER-NEXT: ret void149;150entry:151 br label %loop152 153loop:154 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]155 %scaled.iv = mul nuw nsw i64 %iv, %scale156 %gep.src = getelementptr inbounds float, ptr %src, i64 %scaled.iv157 %l = load float, ptr %gep.src, align 4158 %gep.dst = getelementptr inbounds float, ptr %dst, i64 %iv159 store float %l, ptr %gep.dst, align 4160 %iv.next = add nuw nsw i64 %iv, 1161 %ec = icmp eq i64 %iv.next, %N162 br i1 %ec, label %exit, label %loop163 164exit:165 ret void166}167 168define void @load_op_store_loop(ptr %src, ptr %dst, i64 %N, i64 %scale, float %k) {169; APPLE-LABEL: define void @load_op_store_loop(170; APPLE-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]], i64 [[SCALE:%.*]], float [[K:%.*]]) #[[ATTR0]] {171; APPLE-NEXT: [[ENTRY:.*]]:172; APPLE-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1173; APPLE-NEXT: [[XTRAITER:%.*]] = and i64 [[N]], 1174; APPLE-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 1175; APPLE-NEXT: br i1 [[TMP1]], label %[[LOOP_EPIL_PREHEADER:.*]], label %[[ENTRY_NEW:.*]]176; APPLE: [[ENTRY_NEW]]:177; APPLE-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[N]], [[XTRAITER]]178; APPLE-NEXT: br label %[[LOOP:.*]]179; APPLE: [[LOOP]]:180; APPLE-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[IV_NEXT_1:%.*]], %[[LOOP]] ]181; APPLE-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_1:%.*]], %[[LOOP]] ]182; APPLE-NEXT: [[SCALED_IV:%.*]] = mul nuw nsw i64 [[IV]], [[SCALE]]183; APPLE-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV]]184; APPLE-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4185; APPLE-NEXT: [[O:%.*]] = fadd float [[L]], [[K]]186; APPLE-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV]]187; APPLE-NEXT: store float [[O]], ptr [[GEP_DST]], align 4188; APPLE-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 1189; APPLE-NEXT: [[SCALED_IV_1:%.*]] = mul nuw nsw i64 [[IV_NEXT]], [[SCALE]]190; APPLE-NEXT: [[GEP_SRC_1:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_1]]191; APPLE-NEXT: [[L_1:%.*]] = load float, ptr [[GEP_SRC_1]], align 4192; APPLE-NEXT: [[O_1:%.*]] = fadd float [[L_1]], [[K]]193; APPLE-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT]]194; APPLE-NEXT: store float [[O_1]], ptr [[GEP_DST_1]], align 4195; APPLE-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2196; APPLE-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2197; APPLE-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]198; APPLE-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]199; APPLE: [[EXIT_UNR_LCSSA]]:200; APPLE-NEXT: [[IV_UNR1:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]201; APPLE-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0202; APPLE-NEXT: br i1 [[LCMP_MOD]], label %[[LOOP_EPIL_PREHEADER]], label %[[EXIT:.*]]203; APPLE: [[LOOP_EPIL_PREHEADER]]:204; APPLE-NEXT: [[IV_UNR:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_UNR1]], %[[EXIT_UNR_LCSSA]] ]205; APPLE-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i64 [[XTRAITER]], 0206; APPLE-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]])207; APPLE-NEXT: br label %[[LOOP_EPIL:.*]]208; APPLE: [[LOOP_EPIL]]:209; APPLE-NEXT: [[SCALED_IV_EPIL:%.*]] = mul nuw nsw i64 [[IV_UNR]], [[SCALE]]210; APPLE-NEXT: [[GEP_SRC_EPIL:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_EPIL]]211; APPLE-NEXT: [[L_EPIL:%.*]] = load float, ptr [[GEP_SRC_EPIL]], align 4212; APPLE-NEXT: [[O_EPIL:%.*]] = fadd float [[L_EPIL]], [[K]]213; APPLE-NEXT: [[GEP_DST_EPIL:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_UNR]]214; APPLE-NEXT: store float [[O_EPIL]], ptr [[GEP_DST_EPIL]], align 4215; APPLE-NEXT: br label %[[EXIT]]216; APPLE: [[EXIT]]:217; APPLE-NEXT: ret void218;219; OTHER-LABEL: define void @load_op_store_loop(220; OTHER-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]], i64 [[SCALE:%.*]], float [[K:%.*]]) #[[ATTR0]] {221; OTHER-NEXT: [[ENTRY:.*]]:222; OTHER-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1223; OTHER-NEXT: [[XTRAITER:%.*]] = and i64 [[N]], 1224; OTHER-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 1225; OTHER-NEXT: br i1 [[TMP1]], label %[[LOOP_EPIL_PREHEADER:.*]], label %[[ENTRY_NEW:.*]]226; OTHER: [[ENTRY_NEW]]:227; OTHER-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[N]], [[XTRAITER]]228; OTHER-NEXT: br label %[[LOOP:.*]]229; OTHER: [[LOOP]]:230; OTHER-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[IV_NEXT_1:%.*]], %[[LOOP]] ]231; OTHER-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_1:%.*]], %[[LOOP]] ]232; OTHER-NEXT: [[SCALED_IV:%.*]] = mul nuw nsw i64 [[IV]], [[SCALE]]233; OTHER-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV]]234; OTHER-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4235; OTHER-NEXT: [[O:%.*]] = fadd float [[L]], [[K]]236; OTHER-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV]]237; OTHER-NEXT: store float [[O]], ptr [[GEP_DST]], align 4238; OTHER-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 1239; OTHER-NEXT: [[SCALED_IV_1:%.*]] = mul nuw nsw i64 [[IV_NEXT]], [[SCALE]]240; OTHER-NEXT: [[GEP_SRC_1:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_1]]241; OTHER-NEXT: [[L_1:%.*]] = load float, ptr [[GEP_SRC_1]], align 4242; OTHER-NEXT: [[O_1:%.*]] = fadd float [[L_1]], [[K]]243; OTHER-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_NEXT]]244; OTHER-NEXT: store float [[O_1]], ptr [[GEP_DST_1]], align 4245; OTHER-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2246; OTHER-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2247; OTHER-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]248; OTHER-NEXT: br i1 [[NITER_NCMP_1]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]249; OTHER: [[EXIT_UNR_LCSSA]]:250; OTHER-NEXT: [[IV_UNR1:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]251; OTHER-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0252; OTHER-NEXT: br i1 [[LCMP_MOD]], label %[[LOOP_EPIL_PREHEADER]], label %[[EXIT:.*]]253; OTHER: [[LOOP_EPIL_PREHEADER]]:254; OTHER-NEXT: [[IV_UNR:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_UNR1]], %[[EXIT_UNR_LCSSA]] ]255; OTHER-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i64 [[XTRAITER]], 0256; OTHER-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]])257; OTHER-NEXT: br label %[[LOOP_EPIL:.*]]258; OTHER: [[LOOP_EPIL]]:259; OTHER-NEXT: [[SCALED_IV_EPIL:%.*]] = mul nuw nsw i64 [[IV_UNR]], [[SCALE]]260; OTHER-NEXT: [[GEP_SRC_EPIL:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV_EPIL]]261; OTHER-NEXT: [[L_EPIL:%.*]] = load float, ptr [[GEP_SRC_EPIL]], align 4262; OTHER-NEXT: [[O_EPIL:%.*]] = fadd float [[L_EPIL]], [[K]]263; OTHER-NEXT: [[GEP_DST_EPIL:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV_UNR]]264; OTHER-NEXT: store float [[O_EPIL]], ptr [[GEP_DST_EPIL]], align 4265; OTHER-NEXT: br label %[[EXIT]]266; OTHER: [[EXIT]]:267; OTHER-NEXT: ret void268;269entry:270 br label %loop271 272loop:273 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]274 %scaled.iv = mul nuw nsw i64 %iv, %scale275 %gep.src = getelementptr inbounds float, ptr %src, i64 %scaled.iv276 %l = load float, ptr %gep.src, align 4277 %o = fadd float %l, %k278 %gep.dst = getelementptr inbounds float, ptr %dst, i64 %iv279 store float %o, ptr %gep.dst, align 4280 %iv.next = add nuw nsw i64 %iv, 1281 %ec = icmp eq i64 %iv.next, %N282 br i1 %ec, label %exit, label %loop283 284exit:285 ret void286}287 288define void @load_op_store_loop_multiblock(ptr %src, ptr %dst, i64 %N, i64 %scale, float %k) {289; APPLE-LABEL: define void @load_op_store_loop_multiblock(290; APPLE-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]], i64 [[SCALE:%.*]], float [[K:%.*]]) #[[ATTR0]] {291; APPLE-NEXT: [[ENTRY:.*]]:292; APPLE-NEXT: br label %[[LOOP:.*]]293; APPLE: [[LOOP]]:294; APPLE-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOPCONT:.*]] ]295; APPLE-NEXT: [[SCALED_IV:%.*]] = mul nuw nsw i64 [[IV]], [[SCALE]]296; APPLE-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV]]297; APPLE-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4298; APPLE-NEXT: [[AND:%.*]] = and i64 [[IV]], 1299; APPLE-NEXT: [[ODD:%.*]] = icmp eq i64 [[AND]], 1300; APPLE-NEXT: br i1 [[ODD]], label %[[LOOPODD:.*]], label %[[LOOPCONT]]301; APPLE: [[LOOPCONT]]:302; APPLE-NEXT: [[D:%.*]] = phi float [ [[L2:%.*]], %[[LOOPODD]] ], [ [[L]], %[[LOOP]] ]303; APPLE-NEXT: [[O:%.*]] = fadd float [[D]], [[K]]304; APPLE-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV]]305; APPLE-NEXT: store float [[O]], ptr [[GEP_DST]], align 4306; APPLE-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1307; APPLE-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]308; APPLE-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]309; APPLE: [[LOOPODD]]:310; APPLE-NEXT: [[L2]] = fneg float [[L]]311; APPLE-NEXT: br label %[[LOOPCONT]]312; APPLE: [[EXIT]]:313; APPLE-NEXT: ret void314;315; OTHER-LABEL: define void @load_op_store_loop_multiblock(316; OTHER-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]], i64 [[SCALE:%.*]], float [[K:%.*]]) #[[ATTR0]] {317; OTHER-NEXT: [[ENTRY:.*]]:318; OTHER-NEXT: br label %[[LOOP:.*]]319; OTHER: [[LOOP]]:320; OTHER-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOPCONT:.*]] ]321; OTHER-NEXT: [[SCALED_IV:%.*]] = mul nuw nsw i64 [[IV]], [[SCALE]]322; OTHER-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds float, ptr [[SRC]], i64 [[SCALED_IV]]323; OTHER-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4324; OTHER-NEXT: [[AND:%.*]] = and i64 [[IV]], 1325; OTHER-NEXT: [[ODD:%.*]] = icmp eq i64 [[AND]], 1326; OTHER-NEXT: br i1 [[ODD]], label %[[LOOPODD:.*]], label %[[LOOPCONT]]327; OTHER: [[LOOPCONT]]:328; OTHER-NEXT: [[D:%.*]] = phi float [ [[L2:%.*]], %[[LOOPODD]] ], [ [[L]], %[[LOOP]] ]329; OTHER-NEXT: [[O:%.*]] = fadd float [[D]], [[K]]330; OTHER-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 [[IV]]331; OTHER-NEXT: store float [[O]], ptr [[GEP_DST]], align 4332; OTHER-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1333; OTHER-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]334; OTHER-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]335; OTHER: [[LOOPODD]]:336; OTHER-NEXT: [[L2]] = fneg float [[L]]337; OTHER-NEXT: br label %[[LOOPCONT]]338; OTHER: [[EXIT]]:339; OTHER-NEXT: ret void340;341entry:342 br label %loop343loop:344 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loopcont ]345 %scaled.iv = mul nuw nsw i64 %iv, %scale346 %gep.src = getelementptr inbounds float, ptr %src, i64 %scaled.iv347 %l1 = load float, ptr %gep.src, align 4348 %and = and i64 %iv, 1349 %odd = icmp eq i64 %and, 1350 br i1 %odd, label %loopodd, label %loopcont351loopcont:352 %d = phi float [ %l2, %loopodd ], [ %l1, %loop]353 %o = fadd float %d, %k354 %gep.dst = getelementptr inbounds float, ptr %dst, i64 %iv355 store float %o, ptr %gep.dst, align 4356 %iv.next = add nuw nsw i64 %iv, 1357 %ec = icmp eq i64 %iv.next, %N358 br i1 %ec, label %exit, label %loop359loopodd:360 %l2 = fneg float %l1361 br label %loopcont362exit:363 ret void364}365 366@A = external constant [9 x i8], align 1367@B = external constant [8 x i32], align 4368@C = external constant [8 x i32], align 4369 370define void @early_continue_dep_on_load_large(ptr %p.1, ptr %p.2, i64 %N, i32 %x, i32 %width, i32 %t.1, i32 %t.2) {371; APPLE-LABEL: define void @early_continue_dep_on_load_large(372; APPLE-SAME: ptr [[P_1:%.*]], ptr [[P_2:%.*]], i64 [[N:%.*]], i32 [[X:%.*]], i32 [[WIDTH:%.*]], i32 [[T_1:%.*]], i32 [[T_2:%.*]]) #[[ATTR0]] {373; APPLE-NEXT: [[ENTRY:.*]]:374; APPLE-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1375; APPLE-NEXT: [[TMP1:%.*]] = add i64 [[N]], -2376; APPLE-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP0]], 3377; APPLE-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], 3378; APPLE-NEXT: br i1 [[TMP2]], label %[[LOOP_HEADER_EPIL_PREHEADER:.*]], label %[[ENTRY_NEW:.*]]379; APPLE: [[ENTRY_NEW]]:380; APPLE-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[TMP0]], [[XTRAITER]]381; APPLE-NEXT: br label %[[LOOP_HEADER:.*]]382; APPLE: [[LOOP_HEADER]]:383; APPLE-NEXT: [[IV_EPIL:%.*]] = phi i64 [ 1, %[[ENTRY_NEW]] ], [ [[IV_NEXT_3:%.*]], %[[LOOP_LATCH_3:.*]] ]384; APPLE-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_3:%.*]], %[[LOOP_LATCH_3]] ]385; APPLE-NEXT: [[GEP_EPIL:%.*]] = getelementptr { i32, i8, i8, [2 x i8] }, ptr [[P_1]], i64 [[IV_EPIL]]386; APPLE-NEXT: [[L_1_EPIL:%.*]] = load i32, ptr [[GEP_EPIL]], align 4387; APPLE-NEXT: [[CMP6_NOT_EPIL:%.*]] = icmp sgt i32 [[L_1_EPIL]], [[T_1]]388; APPLE-NEXT: br i1 [[CMP6_NOT_EPIL]], label %[[THEN:.*]], label %[[LOOP_LATCH:.*]]389; APPLE: [[THEN]]:390; APPLE-NEXT: [[GEP_4_EPIL:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP_EPIL]], i64 4391; APPLE-NEXT: [[L_2_EPIL:%.*]] = load i8, ptr [[GEP_4_EPIL]], align 4392; APPLE-NEXT: [[OR_COND_EPIL:%.*]] = icmp ugt i8 [[L_2_EPIL]], 7393; APPLE-NEXT: br i1 [[OR_COND_EPIL]], label %[[MERGE:.*]], label %[[ELSE:.*]]394; APPLE: [[ELSE]]:395; APPLE-NEXT: [[CONV_I_EPIL:%.*]] = zext nneg i8 [[L_2_EPIL]] to i64396; APPLE-NEXT: [[ARRAYIDX_I_EPIL:%.*]] = getelementptr inbounds [9 x i8], ptr @A, i64 0, i64 [[CONV_I_EPIL]]397; APPLE-NEXT: [[TMP27:%.*]] = load i8, ptr [[ARRAYIDX_I_EPIL]], align 1398; APPLE-NEXT: [[IDXPROM_I_EPIL:%.*]] = sext i8 [[TMP27]] to i64399; APPLE-NEXT: [[ARRAYIDX_I37_EPIL:%.*]] = getelementptr inbounds [8 x i32], ptr @B, i64 0, i64 [[IDXPROM_I_EPIL]]400; APPLE-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX_I37_EPIL]], align 4401; APPLE-NEXT: [[ARRAYIDX_I42_EPIL:%.*]] = getelementptr inbounds [8 x i32], ptr @C, i64 0, i64 [[IDXPROM_I_EPIL]]402; APPLE-NEXT: [[TMP29:%.*]] = load i32, ptr [[ARRAYIDX_I42_EPIL]], align 4403; APPLE-NEXT: br label %[[MERGE]]404; APPLE: [[MERGE]]:405; APPLE-NEXT: [[RETVAL_0_I3851_EPIL:%.*]] = phi i32 [ 0, %[[THEN]] ], [ [[TMP28]], %[[ELSE]] ]406; APPLE-NEXT: [[RETVAL_0_I43_EPIL:%.*]] = phi i32 [ 0, %[[THEN]] ], [ [[TMP29]], %[[ELSE]] ]407; APPLE-NEXT: [[ADD14_EPIL:%.*]] = add nsw i32 [[RETVAL_0_I43_EPIL]], [[X]]408; APPLE-NEXT: [[MUL15_EPIL:%.*]] = mul nsw i32 [[ADD14_EPIL]], [[WIDTH]]409; APPLE-NEXT: [[TMP30:%.*]] = trunc nuw nsw i64 [[IV_EPIL]] to i32410; APPLE-NEXT: [[ADD16_EPIL:%.*]] = add nsw i32 [[RETVAL_0_I3851_EPIL]], [[TMP30]]411; APPLE-NEXT: [[ADD17_EPIL:%.*]] = add nsw i32 [[ADD16_EPIL]], [[MUL15_EPIL]]412; APPLE-NEXT: [[IDXPROM18_EPIL:%.*]] = sext i32 [[ADD17_EPIL]] to i64413; APPLE-NEXT: [[ARRAYIDX19_EPIL:%.*]] = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr [[P_2]], i64 [[IDXPROM18_EPIL]]414; APPLE-NEXT: [[TMP31:%.*]] = load i32, ptr [[ARRAYIDX19_EPIL]], align 4415; APPLE-NEXT: [[SUB_EPIL:%.*]] = sub nsw i32 [[X]], [[RETVAL_0_I43_EPIL]]416; APPLE-NEXT: [[MUL21_EPIL:%.*]] = mul nsw i32 [[SUB_EPIL]], [[WIDTH]]417; APPLE-NEXT: [[SUB22_EPIL:%.*]] = sub i32 [[TMP30]], [[RETVAL_0_I3851_EPIL]]418; APPLE-NEXT: [[ADD23_EPIL:%.*]] = add nsw i32 [[SUB22_EPIL]], [[MUL21_EPIL]]419; APPLE-NEXT: [[IDXPROM24_EPIL:%.*]] = sext i32 [[ADD23_EPIL]] to i64420; APPLE-NEXT: [[ARRAYIDX25_EPIL:%.*]] = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr [[P_2]], i64 [[IDXPROM24_EPIL]]421; APPLE-NEXT: [[TMP32:%.*]] = load i32, ptr [[ARRAYIDX25_EPIL]], align 4422; APPLE-NEXT: [[CMP27_EPIL:%.*]] = icmp sgt i32 [[L_1_EPIL]], [[TMP31]]423; APPLE-NEXT: [[CMP28_EPIL:%.*]] = icmp sgt i32 [[L_1_EPIL]], [[TMP32]]424; APPLE-NEXT: [[AND34_EPIL:%.*]] = and i1 [[CMP27_EPIL]], [[CMP28_EPIL]]425; APPLE-NEXT: br i1 [[AND34_EPIL]], label %[[STORE_RES:.*]], label %[[LOOP_LATCH]]426; APPLE: [[STORE_RES]]:427; APPLE-NEXT: [[CMP32_EPIL:%.*]] = icmp sgt i32 [[L_1_EPIL]], [[T_2]]428; APPLE-NEXT: [[GEP_5_EPIL:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP_EPIL]], i64 5429; APPLE-NEXT: [[RES_EPIL:%.*]] = select i1 [[CMP32_EPIL]], i8 1, i8 2430; APPLE-NEXT: store i8 [[RES_EPIL]], ptr [[GEP_5_EPIL]], align 1431; APPLE-NEXT: br label %[[LOOP_LATCH]]432; APPLE: [[LOOP_LATCH]]:433; APPLE-NEXT: [[IV_NEXT_EPIL:%.*]] = add nuw nsw i64 [[IV_EPIL]], 1434; APPLE-NEXT: [[GEP_1:%.*]] = getelementptr { i32, i8, i8, [2 x i8] }, ptr [[P_1]], i64 [[IV_NEXT_EPIL]]435; APPLE-NEXT: [[L_1_1:%.*]] = load i32, ptr [[GEP_1]], align 4436; APPLE-NEXT: [[C_1_1:%.*]] = icmp sgt i32 [[L_1_1]], [[T_1]]437; APPLE-NEXT: br i1 [[C_1_1]], label %[[THEN_1:.*]], label %[[LOOP_LATCH_1:.*]]438; APPLE: [[THEN_1]]:439; APPLE-NEXT: [[GEP_4_1:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP_1]], i64 4440; APPLE-NEXT: [[L_2_1:%.*]] = load i8, ptr [[GEP_4_1]], align 4441; APPLE-NEXT: [[C_2_1:%.*]] = icmp ugt i8 [[L_2_1]], 7442; APPLE-NEXT: br i1 [[C_2_1]], label %[[MERGE_12:.*]], label %[[ELSE_1:.*]]443; APPLE: [[ELSE_1]]:444; APPLE-NEXT: [[CONV_I_1:%.*]] = zext nneg i8 [[L_2_1]] to i64445; APPLE-NEXT: [[GEP_A_1:%.*]] = getelementptr inbounds [9 x i8], ptr @A, i64 0, i64 [[CONV_I_1]]446; APPLE-NEXT: [[L_3_1:%.*]] = load i8, ptr [[GEP_A_1]], align 1447; APPLE-NEXT: [[IDXPROM_I_1:%.*]] = sext i8 [[L_3_1]] to i64448; APPLE-NEXT: [[GEP_B_1:%.*]] = getelementptr inbounds [8 x i32], ptr @B, i64 0, i64 [[IDXPROM_I_1]]449; APPLE-NEXT: [[L_4_1:%.*]] = load i32, ptr [[GEP_B_1]], align 4450; APPLE-NEXT: [[GEP_C_1:%.*]] = getelementptr inbounds [8 x i32], ptr @C, i64 0, i64 [[IDXPROM_I_1]]451; APPLE-NEXT: [[L_5_1:%.*]] = load i32, ptr [[GEP_C_1]], align 4452; APPLE-NEXT: br label %[[MERGE_12]]453; APPLE: [[MERGE_12]]:454; APPLE-NEXT: [[MERGE_1_1:%.*]] = phi i32 [ 0, %[[THEN_1]] ], [ [[L_4_1]], %[[ELSE_1]] ]455; APPLE-NEXT: [[MERGE_2_1:%.*]] = phi i32 [ 0, %[[THEN_1]] ], [ [[L_5_1]], %[[ELSE_1]] ]456; APPLE-NEXT: [[ADD14_1:%.*]] = add nsw i32 [[MERGE_2_1]], [[X]]457; APPLE-NEXT: [[MUL15_1:%.*]] = mul nsw i32 [[ADD14_1]], [[WIDTH]]458; APPLE-NEXT: [[TMP4:%.*]] = trunc nuw nsw i64 [[IV_NEXT_EPIL]] to i32459; APPLE-NEXT: [[ADD16_1:%.*]] = add nsw i32 [[MERGE_1_1]], [[TMP4]]460; APPLE-NEXT: [[ADD17_1:%.*]] = add nsw i32 [[ADD16_1]], [[MUL15_1]]461; APPLE-NEXT: [[IDXPROM18_1:%.*]] = sext i32 [[ADD17_1]] to i64462; APPLE-NEXT: [[GEP_P_2_1:%.*]] = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr [[P_2]], i64 [[IDXPROM18_1]]463; APPLE-NEXT: [[L_6_1:%.*]] = load i32, ptr [[GEP_P_2_1]], align 4464; APPLE-NEXT: [[SUB_1:%.*]] = sub nsw i32 [[X]], [[MERGE_2_1]]465; APPLE-NEXT: [[MUL21_1:%.*]] = mul nsw i32 [[SUB_1]], [[WIDTH]]466; APPLE-NEXT: [[SUB22_1:%.*]] = sub i32 [[TMP4]], [[MERGE_1_1]]467; APPLE-NEXT: [[ADD23_1:%.*]] = add nsw i32 [[SUB22_1]], [[MUL21_1]]468; APPLE-NEXT: [[IDXPROM24_1:%.*]] = sext i32 [[ADD23_1]] to i64469; APPLE-NEXT: [[GEP_P2_1_1:%.*]] = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr [[P_2]], i64 [[IDXPROM24_1]]470; APPLE-NEXT: [[L_7_1:%.*]] = load i32, ptr [[GEP_P2_1_1]], align 4471; APPLE-NEXT: [[C_3_1:%.*]] = icmp sgt i32 [[L_1_1]], [[L_6_1]]472; APPLE-NEXT: [[C_4_1:%.*]] = icmp sgt i32 [[L_1_1]], [[L_7_1]]473; APPLE-NEXT: [[AND34_1:%.*]] = and i1 [[C_3_1]], [[C_4_1]]474; APPLE-NEXT: br i1 [[AND34_1]], label %[[STORE_RES_1:.*]], label %[[LOOP_LATCH_1]]475; APPLE: [[STORE_RES_1]]:476; APPLE-NEXT: [[C_5_1:%.*]] = icmp sgt i32 [[L_1_1]], [[T_2]]477; APPLE-NEXT: [[GEP_5_1:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP_1]], i64 5478; APPLE-NEXT: [[RES_1:%.*]] = select i1 [[C_5_1]], i8 1, i8 2479; APPLE-NEXT: store i8 [[RES_1]], ptr [[GEP_5_1]], align 1480; APPLE-NEXT: br label %[[LOOP_LATCH_1]]481; APPLE: [[LOOP_LATCH_1]]:482; APPLE-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i64 [[IV_EPIL]], 2483; APPLE-NEXT: [[GEP_2:%.*]] = getelementptr { i32, i8, i8, [2 x i8] }, ptr [[P_1]], i64 [[IV_NEXT_1]]484; APPLE-NEXT: [[L_1_2:%.*]] = load i32, ptr [[GEP_2]], align 4485; APPLE-NEXT: [[C_1_2:%.*]] = icmp sgt i32 [[L_1_2]], [[T_1]]486; APPLE-NEXT: br i1 [[C_1_2]], label %[[THEN_2:.*]], label %[[LOOP_LATCH_2:.*]]487; APPLE: [[THEN_2]]:488; APPLE-NEXT: [[GEP_4_2:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP_2]], i64 4489; APPLE-NEXT: [[L_2_2:%.*]] = load i8, ptr [[GEP_4_2]], align 4490; APPLE-NEXT: [[C_2_2:%.*]] = icmp ugt i8 [[L_2_2]], 7491; APPLE-NEXT: br i1 [[C_2_2]], label %[[MERGE_23:.*]], label %[[ELSE_2:.*]]492; APPLE: [[ELSE_2]]:493; APPLE-NEXT: [[CONV_I_2:%.*]] = zext nneg i8 [[L_2_2]] to i64494; APPLE-NEXT: [[GEP_A_2:%.*]] = getelementptr inbounds [9 x i8], ptr @A, i64 0, i64 [[CONV_I_2]]495; APPLE-NEXT: [[L_3_2:%.*]] = load i8, ptr [[GEP_A_2]], align 1496; APPLE-NEXT: [[IDXPROM_I_2:%.*]] = sext i8 [[L_3_2]] to i64497; APPLE-NEXT: [[GEP_B_2:%.*]] = getelementptr inbounds [8 x i32], ptr @B, i64 0, i64 [[IDXPROM_I_2]]498; APPLE-NEXT: [[L_4_2:%.*]] = load i32, ptr [[GEP_B_2]], align 4499; APPLE-NEXT: [[GEP_C_2:%.*]] = getelementptr inbounds [8 x i32], ptr @C, i64 0, i64 [[IDXPROM_I_2]]500; APPLE-NEXT: [[L_5_2:%.*]] = load i32, ptr [[GEP_C_2]], align 4501; APPLE-NEXT: br label %[[MERGE_23]]502; APPLE: [[MERGE_23]]:503; APPLE-NEXT: [[MERGE_1_2:%.*]] = phi i32 [ 0, %[[THEN_2]] ], [ [[L_4_2]], %[[ELSE_2]] ]504; APPLE-NEXT: [[MERGE_2_2:%.*]] = phi i32 [ 0, %[[THEN_2]] ], [ [[L_5_2]], %[[ELSE_2]] ]505; APPLE-NEXT: [[ADD14_2:%.*]] = add nsw i32 [[MERGE_2_2]], [[X]]506; APPLE-NEXT: [[MUL15_2:%.*]] = mul nsw i32 [[ADD14_2]], [[WIDTH]]507; APPLE-NEXT: [[TMP5:%.*]] = trunc nuw nsw i64 [[IV_NEXT_1]] to i32508; APPLE-NEXT: [[ADD16_2:%.*]] = add nsw i32 [[MERGE_1_2]], [[TMP5]]509; APPLE-NEXT: [[ADD17_2:%.*]] = add nsw i32 [[ADD16_2]], [[MUL15_2]]510; APPLE-NEXT: [[IDXPROM18_2:%.*]] = sext i32 [[ADD17_2]] to i64511; APPLE-NEXT: [[GEP_P_2_2:%.*]] = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr [[P_2]], i64 [[IDXPROM18_2]]512; APPLE-NEXT: [[L_6_2:%.*]] = load i32, ptr [[GEP_P_2_2]], align 4513; APPLE-NEXT: [[SUB_2:%.*]] = sub nsw i32 [[X]], [[MERGE_2_2]]514; APPLE-NEXT: [[MUL21_2:%.*]] = mul nsw i32 [[SUB_2]], [[WIDTH]]515; APPLE-NEXT: [[SUB22_2:%.*]] = sub i32 [[TMP5]], [[MERGE_1_2]]516; APPLE-NEXT: [[ADD23_2:%.*]] = add nsw i32 [[SUB22_2]], [[MUL21_2]]517; APPLE-NEXT: [[IDXPROM24_2:%.*]] = sext i32 [[ADD23_2]] to i64518; APPLE-NEXT: [[GEP_P2_1_2:%.*]] = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr [[P_2]], i64 [[IDXPROM24_2]]519; APPLE-NEXT: [[L_7_2:%.*]] = load i32, ptr [[GEP_P2_1_2]], align 4520; APPLE-NEXT: [[C_3_2:%.*]] = icmp sgt i32 [[L_1_2]], [[L_6_2]]521; APPLE-NEXT: [[C_4_2:%.*]] = icmp sgt i32 [[L_1_2]], [[L_7_2]]522; APPLE-NEXT: [[AND34_2:%.*]] = and i1 [[C_3_2]], [[C_4_2]]523; APPLE-NEXT: br i1 [[AND34_2]], label %[[STORE_RES_2:.*]], label %[[LOOP_LATCH_2]]524; APPLE: [[STORE_RES_2]]:525; APPLE-NEXT: [[C_5_2:%.*]] = icmp sgt i32 [[L_1_2]], [[T_2]]526; APPLE-NEXT: [[GEP_5_2:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP_2]], i64 5527; APPLE-NEXT: [[RES_2:%.*]] = select i1 [[C_5_2]], i8 1, i8 2528; APPLE-NEXT: store i8 [[RES_2]], ptr [[GEP_5_2]], align 1529; APPLE-NEXT: br label %[[LOOP_LATCH_2]]530; APPLE: [[LOOP_LATCH_2]]:531; APPLE-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i64 [[IV_EPIL]], 3532; APPLE-NEXT: [[GEP_3:%.*]] = getelementptr { i32, i8, i8, [2 x i8] }, ptr [[P_1]], i64 [[IV_NEXT_2]]533; APPLE-NEXT: [[L_1_3:%.*]] = load i32, ptr [[GEP_3]], align 4534; APPLE-NEXT: [[C_1_3:%.*]] = icmp sgt i32 [[L_1_3]], [[T_1]]535; APPLE-NEXT: br i1 [[C_1_3]], label %[[THEN_3:.*]], label %[[LOOP_LATCH_3]]536; APPLE: [[THEN_3]]:537; APPLE-NEXT: [[GEP_4_3:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP_3]], i64 4538; APPLE-NEXT: [[L_2_3:%.*]] = load i8, ptr [[GEP_4_3]], align 4539; APPLE-NEXT: [[C_2_3:%.*]] = icmp ugt i8 [[L_2_3]], 7540; APPLE-NEXT: br i1 [[C_2_3]], label %[[MERGE_3:.*]], label %[[ELSE_3:.*]]541; APPLE: [[ELSE_3]]:542; APPLE-NEXT: [[CONV_I_3:%.*]] = zext nneg i8 [[L_2_3]] to i64543; APPLE-NEXT: [[GEP_A_3:%.*]] = getelementptr inbounds [9 x i8], ptr @A, i64 0, i64 [[CONV_I_3]]544; APPLE-NEXT: [[L_3_3:%.*]] = load i8, ptr [[GEP_A_3]], align 1545; APPLE-NEXT: [[IDXPROM_I_3:%.*]] = sext i8 [[L_3_3]] to i64546; APPLE-NEXT: [[GEP_B_3:%.*]] = getelementptr inbounds [8 x i32], ptr @B, i64 0, i64 [[IDXPROM_I_3]]547; APPLE-NEXT: [[L_4_3:%.*]] = load i32, ptr [[GEP_B_3]], align 4548; APPLE-NEXT: [[GEP_C_3:%.*]] = getelementptr inbounds [8 x i32], ptr @C, i64 0, i64 [[IDXPROM_I_3]]549; APPLE-NEXT: [[L_5_3:%.*]] = load i32, ptr [[GEP_C_3]], align 4550; APPLE-NEXT: br label %[[MERGE_3]]551; APPLE: [[MERGE_3]]:552; APPLE-NEXT: [[MERGE_1_3:%.*]] = phi i32 [ 0, %[[THEN_3]] ], [ [[L_4_3]], %[[ELSE_3]] ]553; APPLE-NEXT: [[MERGE_2_3:%.*]] = phi i32 [ 0, %[[THEN_3]] ], [ [[L_5_3]], %[[ELSE_3]] ]554; APPLE-NEXT: [[ADD14_3:%.*]] = add nsw i32 [[MERGE_2_3]], [[X]]555; APPLE-NEXT: [[MUL15_3:%.*]] = mul nsw i32 [[ADD14_3]], [[WIDTH]]556; APPLE-NEXT: [[TMP6:%.*]] = trunc nuw nsw i64 [[IV_NEXT_2]] to i32557; APPLE-NEXT: [[ADD16_3:%.*]] = add nsw i32 [[MERGE_1_3]], [[TMP6]]558; APPLE-NEXT: [[ADD17_3:%.*]] = add nsw i32 [[ADD16_3]], [[MUL15_3]]559; APPLE-NEXT: [[IDXPROM18_3:%.*]] = sext i32 [[ADD17_3]] to i64560; APPLE-NEXT: [[GEP_P_2_3:%.*]] = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr [[P_2]], i64 [[IDXPROM18_3]]561; APPLE-NEXT: [[L_6_3:%.*]] = load i32, ptr [[GEP_P_2_3]], align 4562; APPLE-NEXT: [[SUB_3:%.*]] = sub nsw i32 [[X]], [[MERGE_2_3]]563; APPLE-NEXT: [[MUL21_3:%.*]] = mul nsw i32 [[SUB_3]], [[WIDTH]]564; APPLE-NEXT: [[SUB22_3:%.*]] = sub i32 [[TMP6]], [[MERGE_1_3]]565; APPLE-NEXT: [[ADD23_3:%.*]] = add nsw i32 [[SUB22_3]], [[MUL21_3]]566; APPLE-NEXT: [[IDXPROM24_3:%.*]] = sext i32 [[ADD23_3]] to i64567; APPLE-NEXT: [[GEP_P2_1_3:%.*]] = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr [[P_2]], i64 [[IDXPROM24_3]]568; APPLE-NEXT: [[L_7_3:%.*]] = load i32, ptr [[GEP_P2_1_3]], align 4569; APPLE-NEXT: [[C_3_3:%.*]] = icmp sgt i32 [[L_1_3]], [[L_6_3]]570; APPLE-NEXT: [[C_4_3:%.*]] = icmp sgt i32 [[L_1_3]], [[L_7_3]]571; APPLE-NEXT: [[AND34_3:%.*]] = and i1 [[C_3_3]], [[C_4_3]]572; APPLE-NEXT: br i1 [[AND34_3]], label %[[STORE_RES_3:.*]], label %[[LOOP_LATCH_3]]573; APPLE: [[STORE_RES_3]]:574; APPLE-NEXT: [[C_5_3:%.*]] = icmp sgt i32 [[L_1_3]], [[T_2]]575; APPLE-NEXT: [[GEP_5_3:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP_3]], i64 5576; APPLE-NEXT: [[RES_3:%.*]] = select i1 [[C_5_3]], i8 1, i8 2577; APPLE-NEXT: store i8 [[RES_3]], ptr [[GEP_5_3]], align 1578; APPLE-NEXT: br label %[[LOOP_LATCH_3]]579; APPLE: [[LOOP_LATCH_3]]:580; APPLE-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV_EPIL]], 4581; APPLE-NEXT: [[NITER_NEXT_3]] = add i64 [[NITER]], 4582; APPLE-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]583; APPLE-NEXT: br i1 [[NITER_NCMP_3]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP_HEADER]]584; APPLE: [[EXIT_UNR_LCSSA]]:585; APPLE-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_3]], %[[LOOP_LATCH_3]] ]586; APPLE-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0587; APPLE-NEXT: br i1 [[LCMP_MOD]], label %[[LOOP_HEADER_EPIL_PREHEADER]], label %[[EXIT:.*]]588; APPLE: [[LOOP_HEADER_EPIL_PREHEADER]]:589; APPLE-NEXT: [[IV_EPIL_INIT:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[IV_UNR]], %[[EXIT_UNR_LCSSA]] ]590; APPLE-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i64 [[XTRAITER]], 0591; APPLE-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]])592; APPLE-NEXT: br label %[[LOOP_HEADER_EPIL:.*]]593; APPLE: [[LOOP_HEADER_EPIL]]:594; APPLE-NEXT: [[IV_EPIL1:%.*]] = phi i64 [ [[IV_EPIL_INIT]], %[[LOOP_HEADER_EPIL_PREHEADER]] ], [ [[IV_NEXT_EPIL1:%.*]], %[[LOOP_LATCH_EPIL:.*]] ]595; APPLE-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ 0, %[[LOOP_HEADER_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], %[[LOOP_LATCH_EPIL]] ]596; APPLE-NEXT: [[GEP_EPIL1:%.*]] = getelementptr { i32, i8, i8, [2 x i8] }, ptr [[P_1]], i64 [[IV_EPIL1]]597; APPLE-NEXT: [[L_1_EPIL1:%.*]] = load i32, ptr [[GEP_EPIL1]], align 4598; APPLE-NEXT: [[C_1_EPIL:%.*]] = icmp sgt i32 [[L_1_EPIL1]], [[T_1]]599; APPLE-NEXT: br i1 [[C_1_EPIL]], label %[[THEN_EPIL:.*]], label %[[LOOP_LATCH_EPIL]]600; APPLE: [[THEN_EPIL]]:601; APPLE-NEXT: [[GEP_4_EPIL1:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP_EPIL1]], i64 4602; APPLE-NEXT: [[L_2_EPIL1:%.*]] = load i8, ptr [[GEP_4_EPIL1]], align 4603; APPLE-NEXT: [[C_2_EPIL:%.*]] = icmp ugt i8 [[L_2_EPIL1]], 7604; APPLE-NEXT: br i1 [[C_2_EPIL]], label %[[MERGE_EPIL:.*]], label %[[ELSE_EPIL:.*]]605; APPLE: [[ELSE_EPIL]]:606; APPLE-NEXT: [[CONV_I_EPIL1:%.*]] = zext nneg i8 [[L_2_EPIL1]] to i64607; APPLE-NEXT: [[GEP_A_EPIL:%.*]] = getelementptr inbounds [9 x i8], ptr @A, i64 0, i64 [[CONV_I_EPIL1]]608; APPLE-NEXT: [[L_3_EPIL:%.*]] = load i8, ptr [[GEP_A_EPIL]], align 1609; APPLE-NEXT: [[IDXPROM_I_EPIL1:%.*]] = sext i8 [[L_3_EPIL]] to i64610; APPLE-NEXT: [[GEP_B_EPIL:%.*]] = getelementptr inbounds [8 x i32], ptr @B, i64 0, i64 [[IDXPROM_I_EPIL1]]611; APPLE-NEXT: [[L_4_EPIL:%.*]] = load i32, ptr [[GEP_B_EPIL]], align 4612; APPLE-NEXT: [[GEP_C_EPIL:%.*]] = getelementptr inbounds [8 x i32], ptr @C, i64 0, i64 [[IDXPROM_I_EPIL1]]613; APPLE-NEXT: [[L_5_EPIL:%.*]] = load i32, ptr [[GEP_C_EPIL]], align 4614; APPLE-NEXT: br label %[[MERGE_EPIL]]615; APPLE: [[MERGE_EPIL]]:616; APPLE-NEXT: [[MERGE_1_EPIL:%.*]] = phi i32 [ 0, %[[THEN_EPIL]] ], [ [[L_4_EPIL]], %[[ELSE_EPIL]] ]617; APPLE-NEXT: [[MERGE_2_EPIL:%.*]] = phi i32 [ 0, %[[THEN_EPIL]] ], [ [[L_5_EPIL]], %[[ELSE_EPIL]] ]618; APPLE-NEXT: [[ADD14_EPIL1:%.*]] = add nsw i32 [[MERGE_2_EPIL]], [[X]]619; APPLE-NEXT: [[MUL15_EPIL1:%.*]] = mul nsw i32 [[ADD14_EPIL1]], [[WIDTH]]620; APPLE-NEXT: [[TMP7:%.*]] = trunc nuw nsw i64 [[IV_EPIL1]] to i32621; APPLE-NEXT: [[ADD16_EPIL1:%.*]] = add nsw i32 [[MERGE_1_EPIL]], [[TMP7]]622; APPLE-NEXT: [[ADD17_EPIL1:%.*]] = add nsw i32 [[ADD16_EPIL1]], [[MUL15_EPIL1]]623; APPLE-NEXT: [[IDXPROM18_EPIL1:%.*]] = sext i32 [[ADD17_EPIL1]] to i64624; APPLE-NEXT: [[GEP_P_2_EPIL:%.*]] = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr [[P_2]], i64 [[IDXPROM18_EPIL1]]625; APPLE-NEXT: [[L_6_EPIL:%.*]] = load i32, ptr [[GEP_P_2_EPIL]], align 4626; APPLE-NEXT: [[SUB_EPIL1:%.*]] = sub nsw i32 [[X]], [[MERGE_2_EPIL]]627; APPLE-NEXT: [[MUL21_EPIL1:%.*]] = mul nsw i32 [[SUB_EPIL1]], [[WIDTH]]628; APPLE-NEXT: [[SUB22_EPIL1:%.*]] = sub i32 [[TMP7]], [[MERGE_1_EPIL]]629; APPLE-NEXT: [[ADD23_EPIL1:%.*]] = add nsw i32 [[SUB22_EPIL1]], [[MUL21_EPIL1]]630; APPLE-NEXT: [[IDXPROM24_EPIL1:%.*]] = sext i32 [[ADD23_EPIL1]] to i64631; APPLE-NEXT: [[GEP_P2_1_EPIL:%.*]] = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr [[P_2]], i64 [[IDXPROM24_EPIL1]]632; APPLE-NEXT: [[L_7_EPIL:%.*]] = load i32, ptr [[GEP_P2_1_EPIL]], align 4633; APPLE-NEXT: [[C_3_EPIL:%.*]] = icmp sgt i32 [[L_1_EPIL1]], [[L_6_EPIL]]634; APPLE-NEXT: [[C_4_EPIL:%.*]] = icmp sgt i32 [[L_1_EPIL1]], [[L_7_EPIL]]635; APPLE-NEXT: [[AND34_EPIL1:%.*]] = and i1 [[C_3_EPIL]], [[C_4_EPIL]]636; APPLE-NEXT: br i1 [[AND34_EPIL1]], label %[[STORE_RES_EPIL:.*]], label %[[LOOP_LATCH_EPIL]]637; APPLE: [[STORE_RES_EPIL]]:638; APPLE-NEXT: [[C_5_EPIL:%.*]] = icmp sgt i32 [[L_1_EPIL1]], [[T_2]]639; APPLE-NEXT: [[GEP_5_EPIL1:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP_EPIL1]], i64 5640; APPLE-NEXT: [[RES_EPIL1:%.*]] = select i1 [[C_5_EPIL]], i8 1, i8 2641; APPLE-NEXT: store i8 [[RES_EPIL1]], ptr [[GEP_5_EPIL1]], align 1642; APPLE-NEXT: br label %[[LOOP_LATCH_EPIL]]643; APPLE: [[LOOP_LATCH_EPIL]]:644; APPLE-NEXT: [[IV_NEXT_EPIL1]] = add nuw nsw i64 [[IV_EPIL1]], 1645; APPLE-NEXT: [[EC_EPIL:%.*]] = icmp eq i64 [[IV_NEXT_EPIL1]], [[N]]646; APPLE-NEXT: [[EPIL_ITER_NEXT]] = add i64 [[EPIL_ITER]], 1647; APPLE-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i64 [[EPIL_ITER_NEXT]], [[XTRAITER]]648; APPLE-NEXT: br i1 [[EPIL_ITER_CMP]], label %[[LOOP_HEADER_EPIL]], label %[[EXIT_EPILOG_LCSSA:.*]], !llvm.loop [[LOOP2:![0-9]+]]649; APPLE: [[EXIT_EPILOG_LCSSA]]:650; APPLE-NEXT: br label %[[EXIT]]651; APPLE: [[EXIT]]:652; APPLE-NEXT: ret void653;654; OTHER-LABEL: define void @early_continue_dep_on_load_large(655; OTHER-SAME: ptr [[P_1:%.*]], ptr [[P_2:%.*]], i64 [[N:%.*]], i32 [[X:%.*]], i32 [[WIDTH:%.*]], i32 [[T_1:%.*]], i32 [[T_2:%.*]]) #[[ATTR0]] {656; OTHER-NEXT: [[ENTRY:.*]]:657; OTHER-NEXT: br label %[[LOOP_HEADER:.*]]658; OTHER: [[LOOP_HEADER]]:659; OTHER-NEXT: [[IV:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]660; OTHER-NEXT: [[GEP:%.*]] = getelementptr { i32, i8, i8, [2 x i8] }, ptr [[P_1]], i64 [[IV]]661; OTHER-NEXT: [[L_1:%.*]] = load i32, ptr [[GEP]], align 4662; OTHER-NEXT: [[CMP6_NOT:%.*]] = icmp sgt i32 [[L_1]], [[T_1]]663; OTHER-NEXT: br i1 [[CMP6_NOT]], label %[[THEN:.*]], label %[[LOOP_LATCH]]664; OTHER: [[THEN]]:665; OTHER-NEXT: [[GEP_4:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP]], i64 4666; OTHER-NEXT: [[L_2:%.*]] = load i8, ptr [[GEP_4]], align 4667; OTHER-NEXT: [[OR_COND:%.*]] = icmp ugt i8 [[L_2]], 7668; OTHER-NEXT: br i1 [[OR_COND]], label %[[MERGE:.*]], label %[[ELSE:.*]]669; OTHER: [[ELSE]]:670; OTHER-NEXT: [[CONV_I:%.*]] = zext nneg i8 [[L_2]] to i64671; OTHER-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [9 x i8], ptr @A, i64 0, i64 [[CONV_I]]672; OTHER-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX_I]], align 1673; OTHER-NEXT: [[IDXPROM_I:%.*]] = sext i8 [[TMP0]] to i64674; OTHER-NEXT: [[ARRAYIDX_I37:%.*]] = getelementptr inbounds [8 x i32], ptr @B, i64 0, i64 [[IDXPROM_I]]675; OTHER-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX_I37]], align 4676; OTHER-NEXT: [[ARRAYIDX_I42:%.*]] = getelementptr inbounds [8 x i32], ptr @C, i64 0, i64 [[IDXPROM_I]]677; OTHER-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX_I42]], align 4678; OTHER-NEXT: br label %[[MERGE]]679; OTHER: [[MERGE]]:680; OTHER-NEXT: [[RETVAL_0_I3851:%.*]] = phi i32 [ 0, %[[THEN]] ], [ [[TMP1]], %[[ELSE]] ]681; OTHER-NEXT: [[RETVAL_0_I43:%.*]] = phi i32 [ 0, %[[THEN]] ], [ [[TMP2]], %[[ELSE]] ]682; OTHER-NEXT: [[ADD14:%.*]] = add nsw i32 [[RETVAL_0_I43]], [[X]]683; OTHER-NEXT: [[MUL15:%.*]] = mul nsw i32 [[ADD14]], [[WIDTH]]684; OTHER-NEXT: [[TMP3:%.*]] = trunc nuw nsw i64 [[IV]] to i32685; OTHER-NEXT: [[ADD16:%.*]] = add nsw i32 [[RETVAL_0_I3851]], [[TMP3]]686; OTHER-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD16]], [[MUL15]]687; OTHER-NEXT: [[IDXPROM18:%.*]] = sext i32 [[ADD17]] to i64688; OTHER-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr [[P_2]], i64 [[IDXPROM18]]689; OTHER-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX19]], align 4690; OTHER-NEXT: [[SUB:%.*]] = sub nsw i32 [[X]], [[RETVAL_0_I43]]691; OTHER-NEXT: [[MUL21:%.*]] = mul nsw i32 [[SUB]], [[WIDTH]]692; OTHER-NEXT: [[SUB22:%.*]] = sub i32 [[TMP3]], [[RETVAL_0_I3851]]693; OTHER-NEXT: [[ADD23:%.*]] = add nsw i32 [[SUB22]], [[MUL21]]694; OTHER-NEXT: [[IDXPROM24:%.*]] = sext i32 [[ADD23]] to i64695; OTHER-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr [[P_2]], i64 [[IDXPROM24]]696; OTHER-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX25]], align 4697; OTHER-NEXT: [[CMP27:%.*]] = icmp sgt i32 [[L_1]], [[TMP4]]698; OTHER-NEXT: [[CMP28:%.*]] = icmp sgt i32 [[L_1]], [[TMP5]]699; OTHER-NEXT: [[AND34:%.*]] = and i1 [[CMP27]], [[CMP28]]700; OTHER-NEXT: br i1 [[AND34]], label %[[STORE_RES:.*]], label %[[LOOP_LATCH]]701; OTHER: [[STORE_RES]]:702; OTHER-NEXT: [[CMP32:%.*]] = icmp sgt i32 [[L_1]], [[T_2]]703; OTHER-NEXT: [[GEP_5:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP]], i64 5704; OTHER-NEXT: [[RES:%.*]] = select i1 [[CMP32]], i8 1, i8 2705; OTHER-NEXT: store i8 [[RES]], ptr [[GEP_5]], align 1706; OTHER-NEXT: br label %[[LOOP_LATCH]]707; OTHER: [[LOOP_LATCH]]:708; OTHER-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1709; OTHER-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]710; OTHER-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]711; OTHER: [[EXIT]]:712; OTHER-NEXT: ret void713;714entry:715 br label %loop.header716 717loop.header:718 %iv = phi i64 [ 1, %entry ], [ %iv.next, %loop.latch ]719 %gep = getelementptr { i32, i8, i8, [2 x i8] }, ptr %p.1, i64 %iv720 %l.1 = load i32, ptr %gep, align 4721 %c.1 = icmp sgt i32 %l.1, %t.1722 br i1 %c.1, label %then, label %loop.latch723 724then:725 %gep.4 = getelementptr inbounds nuw i8, ptr %gep, i64 4726 %l.2 = load i8, ptr %gep.4, align 4727 %c.2 = icmp ugt i8 %l.2, 7728 br i1 %c.2, label %merge, label %else729 730else:731 %conv.i = zext nneg i8 %l.2 to i64732 %gep.A = getelementptr inbounds [9 x i8], ptr @A, i64 0, i64 %conv.i733 %l.3 = load i8, ptr %gep.A, align 1734 %idxprom.i = sext i8 %l.3 to i64735 %gep.B = getelementptr inbounds [8 x i32], ptr @B, i64 0, i64 %idxprom.i736 %l.4 = load i32, ptr %gep.B, align 4737 %gep.C = getelementptr inbounds [8 x i32], ptr @C, i64 0, i64 %idxprom.i738 %l.5 = load i32, ptr %gep.C, align 4739 br label %merge740 741merge:742 %merge.1 = phi i32 [ 0, %then ], [ %l.4, %else ]743 %merge.2 = phi i32 [ 0, %then ], [ %l.5, %else ]744 %add14 = add nsw i32 %merge.2, %x745 %mul15 = mul nsw i32 %add14, %width746 %12 = trunc nuw nsw i64 %iv to i32747 %add16 = add nsw i32 %merge.1, %12748 %add17 = add nsw i32 %add16, %mul15749 %idxprom18 = sext i32 %add17 to i64750 %gep.p.2 = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr %p.2, i64 %idxprom18751 %l.6 = load i32, ptr %gep.p.2, align 4752 %sub = sub nsw i32 %x, %merge.2753 %mul21 = mul nsw i32 %sub, %width754 %sub22 = sub i32 %12, %merge.1755 %add23 = add nsw i32 %sub22, %mul21756 %idxprom24 = sext i32 %add23 to i64757 %gep.p2.1 = getelementptr inbounds { i32, i8, i8, [2 x i8] }, ptr %p.2, i64 %idxprom24758 %l.7 = load i32, ptr %gep.p2.1, align 4759 %c.3 = icmp sgt i32 %l.1, %l.6760 %c.4 = icmp sgt i32 %l.1, %l.7761 %and34 = and i1 %c.3, %c.4762 br i1 %and34, label %store.res, label %loop.latch763 764store.res:765 %c.5 = icmp sgt i32 %l.1, %t.2766 %gep.5 = getelementptr inbounds nuw i8, ptr %gep, i64 5767 %res = select i1 %c.5, i8 1, i8 2768 store i8 %res, ptr %gep.5, align 1769 br label %loop.latch770 771loop.latch:772 %iv.next = add nuw nsw i64 %iv, 1773 %ec = icmp eq i64 %iv.next, %N774 br i1 %ec, label %exit, label %loop.header775 776exit:777 ret void778}779 780define i32 @test_add_reduction_unroll_partial(ptr %a, i64 noundef %n) {781; APPLE-LABEL: define i32 @test_add_reduction_unroll_partial(782; APPLE-SAME: ptr [[A:%.*]], i64 noundef [[N:%.*]]) #[[ATTR0]] {783; APPLE-NEXT: [[ENTRY:.*]]:784; APPLE-NEXT: br label %[[LOOP:.*]]785; APPLE: [[LOOP]]:786; APPLE-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT_3:%.*]], %[[LOOP]] ]787; APPLE-NEXT: [[RDX_1:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RDX_NEXT_1:%.*]], %[[LOOP]] ]788; APPLE-NEXT: [[RDX_2:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RDX_NEXT_2:%.*]], %[[LOOP]] ]789; APPLE-NEXT: [[RDX_3:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RDX_NEXT_3:%.*]], %[[LOOP]] ]790; APPLE-NEXT: [[RDX:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RDX_NEXT:%.*]], %[[LOOP]] ]791; APPLE-NEXT: [[GEP_A:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV]]792; APPLE-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP_A]], align 2793; APPLE-NEXT: [[RDX_NEXT]] = add i32 [[RDX]], [[TMP0]]794; APPLE-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 1795; APPLE-NEXT: [[GEP_A_1:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT]]796; APPLE-NEXT: [[TMP1:%.*]] = load i32, ptr [[GEP_A_1]], align 2797; APPLE-NEXT: [[RDX_NEXT_1]] = add i32 [[RDX_1]], [[TMP1]]798; APPLE-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i64 [[IV]], 2799; APPLE-NEXT: [[GEP_A_2:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT_1]]800; APPLE-NEXT: [[TMP2:%.*]] = load i32, ptr [[GEP_A_2]], align 2801; APPLE-NEXT: [[RDX_NEXT_2]] = add i32 [[RDX_2]], [[TMP2]]802; APPLE-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i64 [[IV]], 3803; APPLE-NEXT: [[GEP_A_3:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT_2]]804; APPLE-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_3]], align 2805; APPLE-NEXT: [[RDX_NEXT_3]] = add i32 [[RDX_3]], [[TMP3]]806; APPLE-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV]], 4807; APPLE-NEXT: [[EC_3:%.*]] = icmp eq i64 [[IV_NEXT_3]], 1024808; APPLE-NEXT: br i1 [[EC_3]], label %[[EXIT:.*]], label %[[LOOP]]809; APPLE: [[EXIT]]:810; APPLE-NEXT: [[RES:%.*]] = phi i32 [ [[RDX_NEXT_3]], %[[LOOP]] ]811; APPLE-NEXT: [[BIN_RDX:%.*]] = add i32 [[RDX_NEXT_1]], [[RDX_NEXT]]812; APPLE-NEXT: [[BIN_RDX1:%.*]] = add i32 [[RDX_NEXT_2]], [[BIN_RDX]]813; APPLE-NEXT: [[BIN_RDX2:%.*]] = add i32 [[RDX_NEXT_3]], [[BIN_RDX1]]814; APPLE-NEXT: ret i32 [[BIN_RDX2]]815;816; OTHER-LABEL: define i32 @test_add_reduction_unroll_partial(817; OTHER-SAME: ptr [[A:%.*]], i64 noundef [[N:%.*]]) #[[ATTR0]] {818; OTHER-NEXT: [[ENTRY:.*]]:819; OTHER-NEXT: br label %[[LOOP:.*]]820; OTHER: [[LOOP]]:821; OTHER-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT_3:%.*]], %[[LOOP]] ]822; OTHER-NEXT: [[RDX:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RDX_NEXT_3:%.*]], %[[LOOP]] ]823; OTHER-NEXT: [[GEP_A:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV]]824; OTHER-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP_A]], align 2825; OTHER-NEXT: [[RDX_NEXT:%.*]] = add nuw nsw i32 [[RDX]], [[TMP0]]826; OTHER-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 1827; OTHER-NEXT: [[GEP_A_1:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT]]828; OTHER-NEXT: [[TMP1:%.*]] = load i32, ptr [[GEP_A_1]], align 2829; OTHER-NEXT: [[RDX_2:%.*]] = add nuw nsw i32 [[RDX_NEXT]], [[TMP1]]830; OTHER-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i64 [[IV]], 2831; OTHER-NEXT: [[GEP_A_2:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT_1]]832; OTHER-NEXT: [[TMP2:%.*]] = load i32, ptr [[GEP_A_2]], align 2833; OTHER-NEXT: [[RDX_NEXT_2:%.*]] = add nuw nsw i32 [[RDX_2]], [[TMP2]]834; OTHER-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i64 [[IV]], 3835; OTHER-NEXT: [[GEP_A_3:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT_2]]836; OTHER-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_3]], align 2837; OTHER-NEXT: [[RDX_NEXT_3]] = add nuw nsw i32 [[RDX_NEXT_2]], [[TMP3]]838; OTHER-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV]], 4839; OTHER-NEXT: [[EC_3:%.*]] = icmp eq i64 [[IV_NEXT_3]], 1024840; OTHER-NEXT: br i1 [[EC_3]], label %[[EXIT:.*]], label %[[LOOP]]841; OTHER: [[EXIT]]:842; OTHER-NEXT: [[BIN_RDX2:%.*]] = phi i32 [ [[RDX_NEXT_3]], %[[LOOP]] ]843; OTHER-NEXT: ret i32 [[BIN_RDX2]]844;845entry:846 br label %loop847 848loop:849 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]850 %rdx = phi i32 [ 0, %entry ], [ %rdx.next, %loop ]851 %gep.a = getelementptr inbounds nuw i32, ptr %a, i64 %iv852 %1 = load i32, ptr %gep.a, align 2853 %rdx.next = add nuw nsw i32 %rdx, %1854 %iv.next = add nuw nsw i64 %iv, 1855 %ec = icmp eq i64 %iv.next, 1024856 br i1 %ec, label %exit, label %loop857 858exit:859 %res = phi i32 [ %rdx.next, %loop ]860 ret i32 %res861}862 863declare i1 @cond()864 865define i32 @test_add_reduction_multi_block(ptr %a, i64 noundef %n) {866; APPLE-LABEL: define i32 @test_add_reduction_multi_block(867; APPLE-SAME: ptr [[A:%.*]], i64 noundef [[N:%.*]]) #[[ATTR0]] {868; APPLE-NEXT: [[ENTRY:.*]]:869; APPLE-NEXT: br label %[[LOOP:.*]]870; APPLE: [[LOOP]]:871; APPLE-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]872; APPLE-NEXT: [[RDX:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RDX_NEXT:%.*]], %[[LOOP_LATCH]] ]873; APPLE-NEXT: [[GEP_A:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV]]874; APPLE-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP_A]], align 2875; APPLE-NEXT: [[C:%.*]] = call i1 @cond()876; APPLE-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]]877; APPLE: [[THEN]]:878; APPLE-NEXT: store i32 0, ptr [[GEP_A]], align 4879; APPLE-NEXT: br label %[[LOOP_LATCH]]880; APPLE: [[LOOP_LATCH]]:881; APPLE-NEXT: [[RDX_NEXT]] = add nuw nsw i32 [[RDX]], [[TMP0]]882; APPLE-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1883; APPLE-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 1024884; APPLE-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]885; APPLE: [[EXIT]]:886; APPLE-NEXT: [[RES:%.*]] = phi i32 [ [[RDX_NEXT]], %[[LOOP_LATCH]] ]887; APPLE-NEXT: ret i32 [[RES]]888;889; OTHER-LABEL: define i32 @test_add_reduction_multi_block(890; OTHER-SAME: ptr [[A:%.*]], i64 noundef [[N:%.*]]) #[[ATTR0]] {891; OTHER-NEXT: [[ENTRY:.*]]:892; OTHER-NEXT: br label %[[LOOP:.*]]893; OTHER: [[LOOP]]:894; OTHER-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]895; OTHER-NEXT: [[RDX:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RDX_NEXT:%.*]], %[[LOOP_LATCH]] ]896; OTHER-NEXT: [[GEP_A:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV]]897; OTHER-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP_A]], align 2898; OTHER-NEXT: [[C:%.*]] = call i1 @cond()899; OTHER-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]]900; OTHER: [[THEN]]:901; OTHER-NEXT: store i32 0, ptr [[GEP_A]], align 4902; OTHER-NEXT: br label %[[LOOP_LATCH]]903; OTHER: [[LOOP_LATCH]]:904; OTHER-NEXT: [[RDX_NEXT]] = add nuw nsw i32 [[RDX]], [[TMP0]]905; OTHER-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1906; OTHER-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 1024907; OTHER-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]908; OTHER: [[EXIT]]:909; OTHER-NEXT: [[RES:%.*]] = phi i32 [ [[RDX_NEXT]], %[[LOOP_LATCH]] ]910; OTHER-NEXT: ret i32 [[RES]]911;912entry:913 br label %loop914 915loop:916 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]917 %rdx = phi i32 [ 0, %entry ], [ %rdx.next, %loop.latch ]918 %gep.a = getelementptr inbounds nuw i32, ptr %a, i64 %iv919 %1 = load i32, ptr %gep.a, align 2920 %c = call i1 @cond()921 br i1 %c, label %then, label %loop.latch922 923then:924 store i32 0, ptr %gep.a925 br label %loop.latch926 927loop.latch:928 %rdx.next = add nuw nsw i32 %rdx, %1929 %iv.next = add nuw nsw i64 %iv, 1930 %ec = icmp eq i64 %iv.next, 1024931 br i1 %ec, label %exit, label %loop932 933exit:934 %res = phi i32 [ %rdx.next, %loop.latch ]935 ret i32 %res936}937 938define i32 @test_add_and_mul_reduction_unroll_partial(ptr %a, i64 noundef %n) {939; APPLE-LABEL: define i32 @test_add_and_mul_reduction_unroll_partial(940; APPLE-SAME: ptr [[A:%.*]], i64 noundef [[N:%.*]]) #[[ATTR0]] {941; APPLE-NEXT: [[ENTRY:.*]]:942; APPLE-NEXT: br label %[[LOOP:.*]]943; APPLE: [[LOOP]]:944; APPLE-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT_3:%.*]], %[[LOOP]] ]945; APPLE-NEXT: [[RDX_1:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[BIN_RDX3:%.*]], %[[LOOP]] ]946; APPLE-NEXT: [[RDX_21:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RDX_NEXT_2:%.*]], %[[LOOP]] ]947; APPLE-NEXT: [[RDX_3:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RDX_NEXT_3:%.*]], %[[LOOP]] ]948; APPLE-NEXT: [[RDX:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RES_2:%.*]], %[[LOOP]] ]949; APPLE-NEXT: [[RDX_2:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RDX_2_NEXT_3:%.*]], %[[LOOP]] ]950; APPLE-NEXT: [[GEP_A:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV]]951; APPLE-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP_A]], align 2952; APPLE-NEXT: [[RES_2]] = add i32 [[RDX]], [[TMP0]]953; APPLE-NEXT: [[RDX_2_NEXT:%.*]] = mul i32 [[RDX_2]], [[TMP0]]954; APPLE-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 1955; APPLE-NEXT: [[GEP_A_1:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT]]956; APPLE-NEXT: [[TMP1:%.*]] = load i32, ptr [[GEP_A_1]], align 2957; APPLE-NEXT: [[BIN_RDX3]] = add i32 [[RDX_1]], [[TMP1]]958; APPLE-NEXT: [[RDX_2_NEXT_1:%.*]] = mul i32 [[RDX_2_NEXT]], [[TMP1]]959; APPLE-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i64 [[IV]], 2960; APPLE-NEXT: [[GEP_A_2:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT_1]]961; APPLE-NEXT: [[TMP2:%.*]] = load i32, ptr [[GEP_A_2]], align 2962; APPLE-NEXT: [[RDX_NEXT_2]] = add i32 [[RDX_21]], [[TMP2]]963; APPLE-NEXT: [[RDX_2_NEXT_2:%.*]] = mul i32 [[RDX_2_NEXT_1]], [[TMP2]]964; APPLE-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i64 [[IV]], 3965; APPLE-NEXT: [[GEP_A_3:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT_2]]966; APPLE-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_3]], align 2967; APPLE-NEXT: [[RDX_NEXT_3]] = add i32 [[RDX_3]], [[TMP3]]968; APPLE-NEXT: [[RDX_2_NEXT_3]] = mul i32 [[RDX_2_NEXT_2]], [[TMP3]]969; APPLE-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV]], 4970; APPLE-NEXT: [[EC_3:%.*]] = icmp eq i64 [[IV_NEXT_3]], 1024971; APPLE-NEXT: br i1 [[EC_3]], label %[[EXIT:.*]], label %[[LOOP]]972; APPLE: [[EXIT]]:973; APPLE-NEXT: [[RES_1:%.*]] = phi i32 [ [[RDX_NEXT_3]], %[[LOOP]] ]974; APPLE-NEXT: [[RES_3:%.*]] = phi i32 [ [[RDX_2_NEXT_3]], %[[LOOP]] ]975; APPLE-NEXT: [[SUM:%.*]] = add i32 [[BIN_RDX3]], [[RES_2]]976; APPLE-NEXT: [[BIN_RDX2:%.*]] = add i32 [[RDX_NEXT_2]], [[SUM]]977; APPLE-NEXT: [[BIN_RDX4:%.*]] = add i32 [[RDX_NEXT_3]], [[BIN_RDX2]]978; APPLE-NEXT: [[SUM1:%.*]] = add i32 [[BIN_RDX4]], [[RES_3]]979; APPLE-NEXT: ret i32 [[SUM1]]980;981; OTHER-LABEL: define i32 @test_add_and_mul_reduction_unroll_partial(982; OTHER-SAME: ptr [[A:%.*]], i64 noundef [[N:%.*]]) #[[ATTR0]] {983; OTHER-NEXT: [[ENTRY:.*]]:984; OTHER-NEXT: br label %[[LOOP:.*]]985; OTHER: [[LOOP]]:986; OTHER-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT_1:%.*]], %[[LOOP]] ]987; OTHER-NEXT: [[RDX:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RDX_NEXT_1:%.*]], %[[LOOP]] ]988; OTHER-NEXT: [[RDX_2:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RDX_2_NEXT_1:%.*]], %[[LOOP]] ]989; OTHER-NEXT: [[GEP_A:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV]]990; OTHER-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP_A]], align 2991; OTHER-NEXT: [[RDX_NEXT:%.*]] = add nuw nsw i32 [[RDX]], [[TMP0]]992; OTHER-NEXT: [[RDX_2_NEXT:%.*]] = mul i32 [[RDX_2]], [[TMP0]]993; OTHER-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 1994; OTHER-NEXT: [[GEP_A_1:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT]]995; OTHER-NEXT: [[TMP1:%.*]] = load i32, ptr [[GEP_A_1]], align 2996; OTHER-NEXT: [[RDX_NEXT_1]] = add nuw nsw i32 [[RDX_NEXT]], [[TMP1]]997; OTHER-NEXT: [[RDX_2_NEXT_1]] = mul i32 [[RDX_2_NEXT]], [[TMP1]]998; OTHER-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2999; OTHER-NEXT: [[EC_1:%.*]] = icmp eq i64 [[IV_NEXT_1]], 10241000; OTHER-NEXT: br i1 [[EC_1]], label %[[EXIT:.*]], label %[[LOOP]]1001; OTHER: [[EXIT]]:1002; OTHER-NEXT: [[BIN_RDX:%.*]] = phi i32 [ [[RDX_NEXT_1]], %[[LOOP]] ]1003; OTHER-NEXT: [[RES_2:%.*]] = phi i32 [ [[RDX_2_NEXT_1]], %[[LOOP]] ]1004; OTHER-NEXT: [[SUM:%.*]] = add i32 [[BIN_RDX]], [[RES_2]]1005; OTHER-NEXT: ret i32 [[SUM]]1006;1007entry:1008 br label %loop1009 1010loop:1011 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]1012 %rdx = phi i32 [ 0, %entry ], [ %rdx.next, %loop ]1013 %rdx.2 = phi i32 [ 0, %entry ], [ %rdx.2.next, %loop ]1014 %gep.a = getelementptr inbounds nuw i32, ptr %a, i64 %iv1015 %1 = load i32, ptr %gep.a, align 21016 %rdx.next = add nuw nsw i32 %rdx, %11017 %rdx.2.next = mul i32 %rdx.2, %11018 %iv.next = add nuw nsw i64 %iv, 11019 %ec = icmp eq i64 %iv.next, 10241020 br i1 %ec, label %exit, label %loop1021 1022exit:1023 %res.1 = phi i32 [ %rdx.next, %loop ]1024 %res.2 = phi i32 [ %rdx.2.next, %loop ]1025 %sum = add i32 %res.1, %res.21026 ret i32 %sum1027}1028 1029 1030define i32 @test_add_reduction_runtime(ptr %a, i64 noundef %n) {1031; APPLE-LABEL: define i32 @test_add_reduction_runtime(1032; APPLE-SAME: ptr [[A:%.*]], i64 noundef [[N:%.*]]) #[[ATTR0]] {1033; APPLE-NEXT: [[ENTRY:.*]]:1034; APPLE-NEXT: [[TMP0:%.*]] = add i64 [[N]], -11035; APPLE-NEXT: [[XTRAITER:%.*]] = and i64 [[N]], 31036; APPLE-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 31037; APPLE-NEXT: br i1 [[TMP1]], label %[[LOOP_EPIL_PREHEADER:.*]], label %[[ENTRY_NEW:.*]]1038; APPLE: [[ENTRY_NEW]]:1039; APPLE-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[N]], [[XTRAITER]]1040; APPLE-NEXT: br label %[[LOOP:.*]]1041; APPLE: [[LOOP]]:1042; APPLE-NEXT: [[IV_EPIL:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[IV_NEXT_3:%.*]], %[[LOOP]] ]1043; APPLE-NEXT: [[RDX_1:%.*]] = phi i32 [ 0, %[[ENTRY_NEW]] ], [ [[RDX_NEXT_1:%.*]], %[[LOOP]] ]1044; APPLE-NEXT: [[RDX_2:%.*]] = phi i32 [ 0, %[[ENTRY_NEW]] ], [ [[RDX_NEXT_2:%.*]], %[[LOOP]] ]1045; APPLE-NEXT: [[RDX_3:%.*]] = phi i32 [ 0, %[[ENTRY_NEW]] ], [ [[RDX_NEXT_3:%.*]], %[[LOOP]] ]1046; APPLE-NEXT: [[RDX:%.*]] = phi i32 [ 0, %[[ENTRY_NEW]] ], [ [[RDX_NEXT:%.*]], %[[LOOP]] ]1047; APPLE-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_3:%.*]], %[[LOOP]] ]1048; APPLE-NEXT: [[GEP_A_EPIL:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_EPIL]]1049; APPLE-NEXT: [[TMP6:%.*]] = load i32, ptr [[GEP_A_EPIL]], align 21050; APPLE-NEXT: [[RDX_NEXT]] = add i32 [[RDX]], [[TMP6]]1051; APPLE-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV_EPIL]], 11052; APPLE-NEXT: [[GEP_A_1:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT]]1053; APPLE-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 21054; APPLE-NEXT: [[RDX_NEXT_1]] = add i32 [[RDX_1]], [[TMP3]]1055; APPLE-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i64 [[IV_EPIL]], 21056; APPLE-NEXT: [[GEP_A_2:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT_1]]1057; APPLE-NEXT: [[TMP4:%.*]] = load i32, ptr [[GEP_A_2]], align 21058; APPLE-NEXT: [[RDX_NEXT_2]] = add i32 [[RDX_2]], [[TMP4]]1059; APPLE-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i64 [[IV_EPIL]], 31060; APPLE-NEXT: [[GEP_A_3:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT_2]]1061; APPLE-NEXT: [[TMP5:%.*]] = load i32, ptr [[GEP_A_3]], align 21062; APPLE-NEXT: [[RDX_NEXT_3]] = add i32 [[RDX_3]], [[TMP5]]1063; APPLE-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV_EPIL]], 41064; APPLE-NEXT: [[NITER_NEXT_3]] = add nuw i64 [[NITER]], 41065; APPLE-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]1066; APPLE-NEXT: br i1 [[NITER_NCMP_3]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]1067; APPLE: [[EXIT_UNR_LCSSA]]:1068; APPLE-NEXT: [[RES_PH:%.*]] = phi i32 [ [[RDX_NEXT_3]], %[[LOOP]] ]1069; APPLE-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_3]], %[[LOOP]] ]1070; APPLE-NEXT: [[RDX_UNR:%.*]] = phi i32 [ [[RDX_NEXT_3]], %[[LOOP]] ]1071; APPLE-NEXT: [[BIN_RDX:%.*]] = add i32 [[RDX_NEXT_1]], [[RDX_NEXT]]1072; APPLE-NEXT: [[BIN_RDX2:%.*]] = add i32 [[RDX_NEXT_2]], [[BIN_RDX]]1073; APPLE-NEXT: [[BIN_RDX3:%.*]] = add i32 [[RDX_NEXT_3]], [[BIN_RDX2]]1074; APPLE-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 01075; APPLE-NEXT: br i1 [[LCMP_MOD]], label %[[LOOP_EPIL_PREHEADER]], label %[[EXIT:.*]]1076; APPLE: [[LOOP_EPIL_PREHEADER]]:1077; APPLE-NEXT: [[IV_EPIL_INIT:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_UNR]], %[[EXIT_UNR_LCSSA]] ]1078; APPLE-NEXT: [[RDX_EPIL_INIT:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[BIN_RDX3]], %[[EXIT_UNR_LCSSA]] ]1079; APPLE-NEXT: [[LCMP_MOD2:%.*]] = icmp ne i64 [[XTRAITER]], 01080; APPLE-NEXT: call void @llvm.assume(i1 [[LCMP_MOD2]])1081; APPLE-NEXT: br label %[[LOOP_EPIL:.*]]1082; APPLE: [[LOOP_EPIL]]:1083; APPLE-NEXT: [[IV_EPIL1:%.*]] = phi i64 [ [[IV_EPIL_INIT]], %[[LOOP_EPIL_PREHEADER]] ], [ [[IV_NEXT_EPIL:%.*]], %[[LOOP_EPIL]] ]1084; APPLE-NEXT: [[RDX_EPIL:%.*]] = phi i32 [ [[RDX_EPIL_INIT]], %[[LOOP_EPIL_PREHEADER]] ], [ [[RDX_NEXT_EPIL:%.*]], %[[LOOP_EPIL]] ]1085; APPLE-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ 0, %[[LOOP_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], %[[LOOP_EPIL]] ]1086; APPLE-NEXT: [[GEP_A_EPIL1:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_EPIL1]]1087; APPLE-NEXT: [[TMP7:%.*]] = load i32, ptr [[GEP_A_EPIL1]], align 21088; APPLE-NEXT: [[RDX_NEXT_EPIL]] = add nuw nsw i32 [[RDX_EPIL]], [[TMP7]]1089; APPLE-NEXT: [[IV_NEXT_EPIL]] = add nuw nsw i64 [[IV_EPIL1]], 11090; APPLE-NEXT: [[EC_EPIL:%.*]] = icmp eq i64 [[IV_NEXT_EPIL]], [[N]]1091; APPLE-NEXT: [[EPIL_ITER_NEXT]] = add i64 [[EPIL_ITER]], 11092; APPLE-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i64 [[EPIL_ITER_NEXT]], [[XTRAITER]]1093; APPLE-NEXT: br i1 [[EPIL_ITER_CMP]], label %[[LOOP_EPIL]], label %[[EXIT_EPILOG_LCSSA:.*]], !llvm.loop [[LOOP3:![0-9]+]]1094; APPLE: [[EXIT_EPILOG_LCSSA]]:1095; APPLE-NEXT: [[RES_PH1:%.*]] = phi i32 [ [[RDX_NEXT_EPIL]], %[[LOOP_EPIL]] ]1096; APPLE-NEXT: br label %[[EXIT]]1097; APPLE: [[EXIT]]:1098; APPLE-NEXT: [[RES:%.*]] = phi i32 [ [[BIN_RDX3]], %[[EXIT_UNR_LCSSA]] ], [ [[RES_PH1]], %[[EXIT_EPILOG_LCSSA]] ]1099; APPLE-NEXT: ret i32 [[RES]]1100;1101; OTHER-LABEL: define i32 @test_add_reduction_runtime(1102; OTHER-SAME: ptr [[A:%.*]], i64 noundef [[N:%.*]]) #[[ATTR0]] {1103; OTHER-NEXT: [[ENTRY:.*]]:1104; OTHER-NEXT: [[TMP0:%.*]] = add i64 [[N]], -11105; OTHER-NEXT: [[XTRAITER:%.*]] = and i64 [[N]], 31106; OTHER-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 31107; OTHER-NEXT: br i1 [[TMP1]], label %[[LOOP_EPIL_PREHEADER:.*]], label %[[ENTRY_NEW:.*]]1108; OTHER: [[ENTRY_NEW]]:1109; OTHER-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[N]], [[XTRAITER]]1110; OTHER-NEXT: br label %[[LOOP:.*]]1111; OTHER: [[LOOP]]:1112; OTHER-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[IV_NEXT_3:%.*]], %[[LOOP]] ]1113; OTHER-NEXT: [[RDX:%.*]] = phi i32 [ 0, %[[ENTRY_NEW]] ], [ [[RDX_NEXT_3:%.*]], %[[LOOP]] ]1114; OTHER-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_3:%.*]], %[[LOOP]] ]1115; OTHER-NEXT: [[GEP_A:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV]]1116; OTHER-NEXT: [[TMP2:%.*]] = load i32, ptr [[GEP_A]], align 21117; OTHER-NEXT: [[RDX_NEXT:%.*]] = add nuw nsw i32 [[RDX]], [[TMP2]]1118; OTHER-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 11119; OTHER-NEXT: [[GEP_A_1:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT]]1120; OTHER-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 21121; OTHER-NEXT: [[RDX_2:%.*]] = add nuw nsw i32 [[RDX_NEXT]], [[TMP3]]1122; OTHER-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i64 [[IV]], 21123; OTHER-NEXT: [[GEP_A_2:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT_1]]1124; OTHER-NEXT: [[TMP4:%.*]] = load i32, ptr [[GEP_A_2]], align 21125; OTHER-NEXT: [[RDX_NEXT_2:%.*]] = add nuw nsw i32 [[RDX_2]], [[TMP4]]1126; OTHER-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i64 [[IV]], 31127; OTHER-NEXT: [[GEP_A_3:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_NEXT_2]]1128; OTHER-NEXT: [[TMP5:%.*]] = load i32, ptr [[GEP_A_3]], align 21129; OTHER-NEXT: [[RDX_NEXT_3]] = add nuw nsw i32 [[RDX_NEXT_2]], [[TMP5]]1130; OTHER-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV]], 41131; OTHER-NEXT: [[NITER_NEXT_3]] = add i64 [[NITER]], 41132; OTHER-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NEXT_3]], [[UNROLL_ITER]]1133; OTHER-NEXT: br i1 [[NITER_NCMP_3]], label %[[EXIT_UNR_LCSSA:.*]], label %[[LOOP]]1134; OTHER: [[EXIT_UNR_LCSSA]]:1135; OTHER-NEXT: [[RES_PH:%.*]] = phi i32 [ [[RDX_NEXT_3]], %[[LOOP]] ]1136; OTHER-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_3]], %[[LOOP]] ]1137; OTHER-NEXT: [[RDX_UNR:%.*]] = phi i32 [ [[RDX_NEXT_3]], %[[LOOP]] ]1138; OTHER-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 01139; OTHER-NEXT: br i1 [[LCMP_MOD]], label %[[LOOP_EPIL_PREHEADER]], label %[[EXIT:.*]]1140; OTHER: [[LOOP_EPIL_PREHEADER]]:1141; OTHER-NEXT: [[IV_EPIL_INIT:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_UNR]], %[[EXIT_UNR_LCSSA]] ]1142; OTHER-NEXT: [[RDX_EPIL_INIT:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[RDX_UNR]], %[[EXIT_UNR_LCSSA]] ]1143; OTHER-NEXT: [[LCMP_MOD2:%.*]] = icmp ne i64 [[XTRAITER]], 01144; OTHER-NEXT: call void @llvm.assume(i1 [[LCMP_MOD2]])1145; OTHER-NEXT: br label %[[LOOP_EPIL:.*]]1146; OTHER: [[LOOP_EPIL]]:1147; OTHER-NEXT: [[IV_EPIL:%.*]] = phi i64 [ [[IV_EPIL_INIT]], %[[LOOP_EPIL_PREHEADER]] ], [ [[IV_NEXT_EPIL:%.*]], %[[LOOP_EPIL]] ]1148; OTHER-NEXT: [[RDX_EPIL:%.*]] = phi i32 [ [[RDX_EPIL_INIT]], %[[LOOP_EPIL_PREHEADER]] ], [ [[RDX_NEXT_EPIL:%.*]], %[[LOOP_EPIL]] ]1149; OTHER-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ 0, %[[LOOP_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], %[[LOOP_EPIL]] ]1150; OTHER-NEXT: [[GEP_A_EPIL:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IV_EPIL]]1151; OTHER-NEXT: [[TMP6:%.*]] = load i32, ptr [[GEP_A_EPIL]], align 21152; OTHER-NEXT: [[RDX_NEXT_EPIL]] = add nuw nsw i32 [[RDX_EPIL]], [[TMP6]]1153; OTHER-NEXT: [[IV_NEXT_EPIL]] = add nuw nsw i64 [[IV_EPIL]], 11154; OTHER-NEXT: [[EC_EPIL:%.*]] = icmp eq i64 [[IV_NEXT_EPIL]], [[N]]1155; OTHER-NEXT: [[EPIL_ITER_NEXT]] = add i64 [[EPIL_ITER]], 11156; OTHER-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i64 [[EPIL_ITER_NEXT]], [[XTRAITER]]1157; OTHER-NEXT: br i1 [[EPIL_ITER_CMP]], label %[[LOOP_EPIL]], label %[[EXIT_EPILOG_LCSSA:.*]], !llvm.loop [[LOOP0:![0-9]+]]1158; OTHER: [[EXIT_EPILOG_LCSSA]]:1159; OTHER-NEXT: [[RES_PH1:%.*]] = phi i32 [ [[RDX_NEXT_EPIL]], %[[LOOP_EPIL]] ]1160; OTHER-NEXT: br label %[[EXIT]]1161; OTHER: [[EXIT]]:1162; OTHER-NEXT: [[RES:%.*]] = phi i32 [ [[RES_PH]], %[[EXIT_UNR_LCSSA]] ], [ [[RES_PH1]], %[[EXIT_EPILOG_LCSSA]] ]1163; OTHER-NEXT: ret i32 [[RES]]1164;1165entry:1166 br label %loop1167 1168loop:1169 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]1170 %rdx = phi i32 [ 0, %entry ], [ %rdx.next, %loop ]1171 %gep.a = getelementptr inbounds nuw i32, ptr %a, i64 %iv1172 %1 = load i32, ptr %gep.a, align 21173 %rdx.next = add nuw nsw i32 %rdx, %11174 %iv.next = add nuw nsw i64 %iv, 11175 %ec = icmp eq i64 %iv.next, %n1176 br i1 %ec, label %exit, label %loop1177 1178exit:1179 %res = phi i32 [ %rdx.next, %loop ]1180 ret i32 %res1181}1182;.1183; APPLE: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]]}1184; APPLE: [[META1]] = !{!"llvm.loop.unroll.disable"}1185; APPLE: [[LOOP2]] = distinct !{[[LOOP2]], [[META1]]}1186; APPLE: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}1187;.1188; OTHER: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]]}1189; OTHER: [[META1]] = !{!"llvm.loop.unroll.disable"}1190;.1191