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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 32; RUN: opt -passes=loop-unroll,simplifycfg -S -mtriple aarch64 %s | FileCheck %s3 4;; This test contains IR similar to what would be generated when SVE ACLE5;; routines are used with fixed-width vector types -- lots of subvector inserts6;; and extracts that are effectively just bitcasts since the types are the7;; same at a given SVE bit size. We want to make sure that they are not a8;; barrier to unrolling simple loops with a fixed trip count which could be9;; further optimized.10 11define void @test_ins_ext_cost(ptr readonly %a, ptr readonly %b, ptr readonly %c, ptr noalias %d) #0 {12; CHECK-LABEL: define void @test_ins_ext_cost(13; CHECK-SAME: ptr readonly [[A:%.*]], ptr readonly [[B:%.*]], ptr readonly [[C:%.*]], ptr noalias [[D:%.*]]) #[[ATTR0:[0-9]+]] {14; CHECK-NEXT: entry:15; CHECK-NEXT: [[LOAD_A:%.*]] = load <8 x float>, ptr [[A]], align 1616; CHECK-NEXT: [[LOAD_B:%.*]] = load <8 x float>, ptr [[B]], align 1617; CHECK-NEXT: [[LOAD_C:%.*]] = load <8 x float>, ptr [[C]], align 1618; CHECK-NEXT: [[CAST_SCALABLE_B:%.*]] = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> [[LOAD_B]], i64 0)19; CHECK-NEXT: [[CAST_SCALABLE_C:%.*]] = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> [[LOAD_C]], i64 0)20; CHECK-NEXT: [[ADD:%.*]] = fadd <vscale x 4 x float> [[CAST_SCALABLE_B]], [[CAST_SCALABLE_C]]21; CHECK-NEXT: [[CAST_SCALABLE_A:%.*]] = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> [[LOAD_A]], i64 0)22; CHECK-NEXT: [[MUL:%.*]] = fmul <vscale x 4 x float> [[CAST_SCALABLE_A]], [[ADD]]23; CHECK-NEXT: [[CAST_FIXED_D:%.*]] = tail call <8 x float> @llvm.vector.extract.v8f32.nxv4f32(<vscale x 4 x float> [[MUL]], i64 0)24; CHECK-NEXT: store <8 x float> [[CAST_FIXED_D]], ptr [[D]], align 1625; CHECK-NEXT: [[GEP_A_1:%.*]] = getelementptr inbounds <8 x float>, ptr [[A]], i64 126; CHECK-NEXT: [[LOAD_A_1:%.*]] = load <8 x float>, ptr [[GEP_A_1]], align 1627; CHECK-NEXT: [[GEP_B_1:%.*]] = getelementptr inbounds <8 x float>, ptr [[B]], i64 128; CHECK-NEXT: [[LOAD_B_1:%.*]] = load <8 x float>, ptr [[GEP_B_1]], align 1629; CHECK-NEXT: [[GEP_C_1:%.*]] = getelementptr inbounds <8 x float>, ptr [[C]], i64 130; CHECK-NEXT: [[LOAD_C_1:%.*]] = load <8 x float>, ptr [[GEP_C_1]], align 1631; CHECK-NEXT: [[CAST_SCALABLE_B_1:%.*]] = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> [[LOAD_B_1]], i64 0)32; CHECK-NEXT: [[CAST_SCALABLE_C_1:%.*]] = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> [[LOAD_C_1]], i64 0)33; CHECK-NEXT: [[ADD_1:%.*]] = fadd <vscale x 4 x float> [[CAST_SCALABLE_B_1]], [[CAST_SCALABLE_C_1]]34; CHECK-NEXT: [[CAST_SCALABLE_A_1:%.*]] = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> [[LOAD_A_1]], i64 0)35; CHECK-NEXT: [[MUL_1:%.*]] = fmul <vscale x 4 x float> [[CAST_SCALABLE_A_1]], [[ADD_1]]36; CHECK-NEXT: [[CAST_FIXED_D_1:%.*]] = tail call <8 x float> @llvm.vector.extract.v8f32.nxv4f32(<vscale x 4 x float> [[MUL_1]], i64 0)37; CHECK-NEXT: [[GEP_D_1:%.*]] = getelementptr inbounds <8 x float>, ptr [[D]], i64 0, i64 138; CHECK-NEXT: store <8 x float> [[CAST_FIXED_D_1]], ptr [[GEP_D_1]], align 1639; CHECK-NEXT: ret void40;41entry:42 br label %for.body43 44for.body:45 %exit.cond = phi i1 [ true, %entry ], [ false, %for.body ]46 %iv = phi i64 [ 0, %entry ], [ 1, %for.body ]47 %gep.a = getelementptr inbounds <8 x float>, ptr %a, i64 %iv48 %load.a = load <8 x float>, ptr %gep.a, align 1649 %gep.b = getelementptr inbounds <8 x float>, ptr %b, i64 %iv50 %load.b = load <8 x float>, ptr %gep.b, align 1651 %gep.c = getelementptr inbounds <8 x float>, ptr %c, i64 %iv52 %load.c = load <8 x float>, ptr %gep.c, align 1653 %cast.scalable.b = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> %load.b, i64 0)54 %cast.scalable.c = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> %load.c, i64 0)55 %add = fadd <vscale x 4 x float> %cast.scalable.b, %cast.scalable.c56 %cast.scalable.a = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> %load.a, i64 0)57 %mul = fmul <vscale x 4 x float> %cast.scalable.a, %add58 %cast.fixed.d = tail call <8 x float> @llvm.vector.extract.v8f32.nxv4f32(<vscale x 4 x float> %mul, i64 0)59 %gep.d = getelementptr inbounds <8 x float>, ptr %d, i64 0, i64 %iv60 store <8 x float> %cast.fixed.d, ptr %gep.d, align 1661 br i1 %exit.cond, label %for.body, label %exit62 63exit:64 ret void65}66 67attributes #0 = { "target-features"="+sve" vscale_range(2, 16) }68