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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes='default<O2>' -mtriple=powerpc64le-- -o - %s | \3; RUN: FileCheck %s4 5%0 = type <{ double }>6 7define dso_local void @test(ptr %arg) #0 {8; CHECK-LABEL: @test(9; CHECK-NEXT: bb:10; CHECK-NEXT: [[I19:%.*]] = getelementptr i8, ptr [[ARG:%.*]], i64 -3211; CHECK-NEXT: [[I21:%.*]] = getelementptr inbounds nuw i8, ptr [[ARG]], i64 4812; CHECK-NEXT: [[I21_REPACK1:%.*]] = getelementptr inbounds nuw i8, ptr [[ARG]], i64 6413; CHECK-NEXT: br label [[BB16:%.*]]14; CHECK: bb16:15; CHECK-NEXT: [[I20:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])16; CHECK-NEXT: [[I24:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20]])17; CHECK-NEXT: [[I24_ELT:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24]], 018; CHECK-NEXT: store <16 x i8> [[I24_ELT]], ptr [[I21]], align 1619; CHECK-NEXT: [[I24_ELT1:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24]], 120; CHECK-NEXT: store <16 x i8> [[I24_ELT1]], ptr [[I21_REPACK1]], align 1621; CHECK-NEXT: [[I20_1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])22; CHECK-NEXT: [[I24_1:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_1]])23; CHECK-NEXT: [[I24_ELT_1:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_1]], 024; CHECK-NEXT: store <16 x i8> [[I24_ELT_1]], ptr [[I21]], align 1625; CHECK-NEXT: [[I24_ELT1_1:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_1]], 126; CHECK-NEXT: store <16 x i8> [[I24_ELT1_1]], ptr [[I21_REPACK1]], align 1627; CHECK-NEXT: [[I20_2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])28; CHECK-NEXT: [[I24_2:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_2]])29; CHECK-NEXT: [[I24_ELT_2:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_2]], 030; CHECK-NEXT: store <16 x i8> [[I24_ELT_2]], ptr [[I21]], align 1631; CHECK-NEXT: [[I24_ELT1_2:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_2]], 132; CHECK-NEXT: store <16 x i8> [[I24_ELT1_2]], ptr [[I21_REPACK1]], align 1633; CHECK-NEXT: [[I20_3:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])34; CHECK-NEXT: [[I24_3:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_3]])35; CHECK-NEXT: [[I24_ELT_3:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_3]], 036; CHECK-NEXT: store <16 x i8> [[I24_ELT_3]], ptr [[I21]], align 1637; CHECK-NEXT: [[I24_ELT1_3:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_3]], 138; CHECK-NEXT: store <16 x i8> [[I24_ELT1_3]], ptr [[I21_REPACK1]], align 1639; CHECK-NEXT: [[I20_4:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])40; CHECK-NEXT: [[I24_4:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_4]])41; CHECK-NEXT: [[I24_ELT_4:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_4]], 042; CHECK-NEXT: store <16 x i8> [[I24_ELT_4]], ptr [[I21]], align 1643; CHECK-NEXT: [[I24_ELT1_4:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_4]], 144; CHECK-NEXT: store <16 x i8> [[I24_ELT1_4]], ptr [[I21_REPACK1]], align 1645; CHECK-NEXT: [[I20_5:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])46; CHECK-NEXT: [[I24_5:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_5]])47; CHECK-NEXT: [[I24_ELT_5:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_5]], 048; CHECK-NEXT: store <16 x i8> [[I24_ELT_5]], ptr [[I21]], align 1649; CHECK-NEXT: [[I24_ELT1_5:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_5]], 150; CHECK-NEXT: store <16 x i8> [[I24_ELT1_5]], ptr [[I21_REPACK1]], align 1651; CHECK-NEXT: [[I20_6:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])52; CHECK-NEXT: [[I24_6:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_6]])53; CHECK-NEXT: [[I24_ELT_6:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_6]], 054; CHECK-NEXT: store <16 x i8> [[I24_ELT_6]], ptr [[I21]], align 1655; CHECK-NEXT: [[I24_ELT1_6:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_6]], 156; CHECK-NEXT: store <16 x i8> [[I24_ELT1_6]], ptr [[I21_REPACK1]], align 1657; CHECK-NEXT: [[I20_7:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])58; CHECK-NEXT: [[I24_7:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_7]])59; CHECK-NEXT: [[I24_ELT_7:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_7]], 060; CHECK-NEXT: store <16 x i8> [[I24_ELT_7]], ptr [[I21]], align 1661; CHECK-NEXT: [[I24_ELT1_7:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_7]], 162; CHECK-NEXT: store <16 x i8> [[I24_ELT1_7]], ptr [[I21_REPACK1]], align 1663; CHECK-NEXT: [[I20_8:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])64; CHECK-NEXT: [[I24_8:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_8]])65; CHECK-NEXT: [[I24_ELT_8:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_8]], 066; CHECK-NEXT: store <16 x i8> [[I24_ELT_8]], ptr [[I21]], align 1667; CHECK-NEXT: [[I24_ELT1_8:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_8]], 168; CHECK-NEXT: store <16 x i8> [[I24_ELT1_8]], ptr [[I21_REPACK1]], align 1669; CHECK-NEXT: [[I20_9:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])70; CHECK-NEXT: [[I24_9:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_9]])71; CHECK-NEXT: [[I24_ELT_9:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_9]], 072; CHECK-NEXT: store <16 x i8> [[I24_ELT_9]], ptr [[I21]], align 1673; CHECK-NEXT: [[I24_ELT1_9:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_9]], 174; CHECK-NEXT: store <16 x i8> [[I24_ELT1_9]], ptr [[I21_REPACK1]], align 1675; CHECK-NEXT: [[I20_10:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])76; CHECK-NEXT: [[I24_10:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_10]])77; CHECK-NEXT: [[I24_ELT_10:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_10]], 078; CHECK-NEXT: store <16 x i8> [[I24_ELT_10]], ptr [[I21]], align 1679; CHECK-NEXT: [[I24_ELT1_10:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_10]], 180; CHECK-NEXT: store <16 x i8> [[I24_ELT1_10]], ptr [[I21_REPACK1]], align 1681; CHECK-NEXT: [[I20_11:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])82; CHECK-NEXT: [[I24_11:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_11]])83; CHECK-NEXT: [[I24_ELT_11:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_11]], 084; CHECK-NEXT: store <16 x i8> [[I24_ELT_11]], ptr [[I21]], align 1685; CHECK-NEXT: [[I24_ELT1_11:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_11]], 186; CHECK-NEXT: store <16 x i8> [[I24_ELT1_11]], ptr [[I21_REPACK1]], align 1687; CHECK-NEXT: [[I20_12:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])88; CHECK-NEXT: [[I24_12:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_12]])89; CHECK-NEXT: [[I24_ELT_12:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_12]], 090; CHECK-NEXT: store <16 x i8> [[I24_ELT_12]], ptr [[I21]], align 1691; CHECK-NEXT: [[I24_ELT1_12:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_12]], 192; CHECK-NEXT: store <16 x i8> [[I24_ELT1_12]], ptr [[I21_REPACK1]], align 1693; CHECK-NEXT: [[I20_13:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])94; CHECK-NEXT: [[I24_13:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_13]])95; CHECK-NEXT: [[I24_ELT_13:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_13]], 096; CHECK-NEXT: store <16 x i8> [[I24_ELT_13]], ptr [[I21]], align 1697; CHECK-NEXT: [[I24_ELT1_13:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_13]], 198; CHECK-NEXT: store <16 x i8> [[I24_ELT1_13]], ptr [[I21_REPACK1]], align 1699; CHECK-NEXT: [[I20_14:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])100; CHECK-NEXT: [[I24_14:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_14]])101; CHECK-NEXT: [[I24_ELT_14:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_14]], 0102; CHECK-NEXT: store <16 x i8> [[I24_ELT_14]], ptr [[I21]], align 16103; CHECK-NEXT: [[I24_ELT1_14:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_14]], 1104; CHECK-NEXT: store <16 x i8> [[I24_ELT1_14]], ptr [[I21_REPACK1]], align 16105; CHECK-NEXT: [[I20_15:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[I19]])106; CHECK-NEXT: [[I24_15:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[I20_15]])107; CHECK-NEXT: [[I24_ELT_15:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_15]], 0108; CHECK-NEXT: store <16 x i8> [[I24_ELT_15]], ptr [[I21]], align 16109; CHECK-NEXT: [[I24_ELT1_15:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[I24_15]], 1110; CHECK-NEXT: store <16 x i8> [[I24_ELT1_15]], ptr [[I21_REPACK1]], align 16111; CHECK-NEXT: br label [[BB16]], !llvm.loop [[LOOP0:![0-9]+]]112;113bb:114 %i = alloca ptr, align 8115 store ptr %arg, ptr %i, align 8116 %i1 = alloca ptr, align 8117 %i2 = alloca ptr, align 8118 %i3 = alloca i32, align 4119 %i4 = alloca i32, align 4120 %i5 = alloca i64, align 8121 %i6 = alloca i64, align 8122 %i7 = alloca <256 x i1>, align 32123 %i8 = load ptr, ptr %i, align 8124 %i9 = load i32, ptr %i8, align 4125 %i10 = sub nsw i32 %i9, 0126 store i32 %i10, ptr %i4, align 4127 %i11 = load i32, ptr %i4, align 4128 %i12 = ashr i32 %i11, 5129 %i13 = sext i32 %i12 to i64130 %i14 = load i64, ptr %i6, align 8131 %i15 = sub nsw i64 %i14, 1132 br label %bb16133 134bb16: ; preds = %bb16, %bb135 %i17 = load i64, ptr %i5, align 8136 %i18 = icmp sge i64 %i17, 1137 %i19 = getelementptr i8, ptr %arg, i64 -32138 %i20 = call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %i19)139 store <256 x i1> %i20, ptr %i7, align 32140 %i21 = getelementptr inbounds i8, ptr %arg, i64 48141 %i23 = load <256 x i1>, ptr %i7, align 32142 %i24 = call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %i23)143 store { <16 x i8>, <16 x i8> } %i24, ptr %i21, align 16144 br label %bb16, !llvm.loop !1145}146 147; Function Attrs: argmemonly nounwind readonly148declare <256 x i1> @llvm.ppc.vsx.lxvp(ptr) #1149 150; Function Attrs: nounwind readnone151declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>) #2152 153attributes #0 = { "no-trapping-math"="true" }154attributes #1 = { argmemonly nounwind readonly }155attributes #2 = { nounwind readnone }156 157!1 = distinct !{!1, !2, !3, !4}158!2 = !{!"llvm.loop.vectorize.width", i32 1}159!3 = !{!"llvm.loop.interleave.count", i32 1}160!4 = !{!"llvm.loop.unroll.count", i32 16}161