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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -passes=loop-unroll -unroll-runtime < %s | FileCheck %s3 4target triple = "x86_64-unknown-linux-gnu"5 6define void @selsort(ptr %array) #0 {7; CHECK-LABEL: define void @selsort(8; CHECK-SAME: ptr [[ARRAY:%.*]]) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: [[ENTRY:.*:]]10; CHECK-NEXT: [[SIZE:%.*]] = getelementptr inbounds nuw i8, ptr [[ARRAY]], i64 811; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[SIZE]], align 812; CHECK-NEXT: [[CMP21_NOT:%.*]] = icmp eq i64 [[TMP0]], 013; CHECK-NEXT: br i1 [[CMP21_NOT]], label %[[FOR_END18:.*]], label %[[FOR_BODY_LR_PH:.*]]14; CHECK: [[FOR_BODY_LR_PH]]:15; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARRAY]], align 816; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP0]], -117; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP0]], -218; CHECK-NEXT: br label %[[FOR_BODY:.*]]19; CHECK: [[FOR_BODY]]:20; CHECK-NEXT: [[BASE_022:%.*]] = phi i64 [ 0, %[[FOR_BODY_LR_PH]] ], [ [[ADD:%.*]], %[[FOR_END:.*]] ]21; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[BASE_022]], -122; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[TMP7]], [[TMP10]]23; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP8]], [[TMP10]]24; CHECK-NEXT: [[ADD]] = add nuw i64 [[BASE_022]], 125; CHECK-NEXT: [[CMP318:%.*]] = icmp ult i64 [[ADD]], [[TMP0]]26; CHECK-NEXT: br i1 [[CMP318]], label %[[FOR_BODY4_PREHEADER:.*]], label %[[FOR_END]]27; CHECK: [[FOR_BODY4_PREHEADER]]:28; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP11]], 329; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 030; CHECK-NEXT: br i1 [[LCMP_MOD]], label %[[FOR_BODY4_PROL_PREHEADER:.*]], label %[[FOR_BODY4_PROL_LOOPEXIT:.*]]31; CHECK: [[FOR_BODY4_PROL_PREHEADER]]:32; CHECK-NEXT: br label %[[FOR_BODY4_PROL:.*]]33; CHECK: [[FOR_BODY4_PROL]]:34; CHECK-NEXT: [[MIN_020:%.*]] = phi i64 [ [[SPEC_SELECT:%.*]], %[[FOR_BODY4_PROL]] ], [ [[BASE_022]], %[[FOR_BODY4_PROL_PREHEADER]] ]35; CHECK-NEXT: [[C_019:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY4_PROL]] ], [ [[ADD]], %[[FOR_BODY4_PROL_PREHEADER]] ]36; CHECK-NEXT: [[PROL_ITER:%.*]] = phi i64 [ 0, %[[FOR_BODY4_PROL_PREHEADER]] ], [ [[PROL_ITER_NEXT:%.*]], %[[FOR_BODY4_PROL]] ]37; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[C_019]]38; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 439; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[MIN_020]]40; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX6]], align 441; CHECK-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP2]], [[TMP3]]42; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[CMP7]], i64 [[C_019]], i64 [[MIN_020]]43; CHECK-NEXT: [[INC]] = add nuw i64 [[C_019]], 144; CHECK-NEXT: [[CMP3:%.*]] = icmp ult i64 [[INC]], [[TMP0]]45; CHECK-NEXT: [[PROL_ITER_NEXT]] = add i64 [[PROL_ITER]], 146; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i64 [[PROL_ITER_NEXT]], [[XTRAITER]]47; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label %[[FOR_BODY4_PROL]], label %[[FOR_BODY4_PROL_LOOPEXIT_UNR_LCSSA:.*]], !llvm.loop [[LOOP0:![0-9]+]]48; CHECK: [[FOR_BODY4_PROL_LOOPEXIT_UNR_LCSSA]]:49; CHECK-NEXT: [[MIN_020_UNR_PH:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[FOR_BODY4_PROL]] ]50; CHECK-NEXT: [[C_019_UNR_PH:%.*]] = phi i64 [ [[INC]], %[[FOR_BODY4_PROL]] ]51; CHECK-NEXT: [[SPEC_SELECT_LCSSA_UNR_PH:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[FOR_BODY4_PROL]] ]52; CHECK-NEXT: br label %[[FOR_BODY4_PROL_LOOPEXIT]]53; CHECK: [[FOR_BODY4_PROL_LOOPEXIT]]:54; CHECK-NEXT: [[MIN_020_UNR:%.*]] = phi i64 [ [[BASE_022]], %[[FOR_BODY4_PREHEADER]] ], [ [[MIN_020_UNR_PH]], %[[FOR_BODY4_PROL_LOOPEXIT_UNR_LCSSA]] ]55; CHECK-NEXT: [[C_019_UNR:%.*]] = phi i64 [ [[ADD]], %[[FOR_BODY4_PREHEADER]] ], [ [[C_019_UNR_PH]], %[[FOR_BODY4_PROL_LOOPEXIT_UNR_LCSSA]] ]56; CHECK-NEXT: [[SPEC_SELECT_LCSSA_UNR:%.*]] = phi i64 [ poison, %[[FOR_BODY4_PREHEADER]] ], [ [[SPEC_SELECT_LCSSA_UNR_PH]], %[[FOR_BODY4_PROL_LOOPEXIT_UNR_LCSSA]] ]57; CHECK-NEXT: [[TMP9:%.*]] = icmp ult i64 [[TMP6]], 358; CHECK-NEXT: br i1 [[TMP9]], label %[[FOR_END_LOOPEXIT:.*]], label %[[FOR_BODY4_PREHEADER_NEW:.*]]59; CHECK: [[FOR_BODY4_PREHEADER_NEW]]:60; CHECK-NEXT: br label %[[FOR_BODY4:.*]]61; CHECK: [[FOR_BODY4]]:62; CHECK-NEXT: [[MIN_20:%.*]] = phi i64 [ [[MIN_020_UNR]], %[[FOR_BODY4_PREHEADER_NEW]] ], [ [[SPEC_SELECT_3:%.*]], %[[FOR_BODY4]] ]63; CHECK-NEXT: [[MIN_0_LCSSA:%.*]] = phi i64 [ [[C_019_UNR]], %[[FOR_BODY4_PREHEADER_NEW]] ], [ [[INC_3:%.*]], %[[FOR_BODY4]] ]64; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[MIN_0_LCSSA]]65; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX9]], align 466; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[MIN_20]]67; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX11]], align 468; CHECK-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP4]], [[TMP5]]69; CHECK-NEXT: [[SPEC_SELECT1:%.*]] = select i1 [[CMP8]], i64 [[MIN_0_LCSSA]], i64 [[MIN_20]]70; CHECK-NEXT: [[INC1:%.*]] = add nuw i64 [[MIN_0_LCSSA]], 171; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[INC1]]72; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 473; CHECK-NEXT: [[ARRAYIDX6_1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[SPEC_SELECT1]]74; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX6_1]], align 475; CHECK-NEXT: [[CMP7_1:%.*]] = icmp ult i32 [[TMP12]], [[TMP13]]76; CHECK-NEXT: [[SPEC_SELECT_1:%.*]] = select i1 [[CMP7_1]], i64 [[INC1]], i64 [[SPEC_SELECT1]]77; CHECK-NEXT: [[INC_1:%.*]] = add nuw i64 [[MIN_0_LCSSA]], 278; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[INC_1]]79; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 480; CHECK-NEXT: [[ARRAYIDX6_2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[SPEC_SELECT_1]]81; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX6_2]], align 482; CHECK-NEXT: [[CMP7_2:%.*]] = icmp ult i32 [[TMP14]], [[TMP15]]83; CHECK-NEXT: [[SPEC_SELECT_2:%.*]] = select i1 [[CMP7_2]], i64 [[INC_1]], i64 [[SPEC_SELECT_1]]84; CHECK-NEXT: [[INC_2:%.*]] = add nuw i64 [[MIN_0_LCSSA]], 385; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[INC_2]]86; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 487; CHECK-NEXT: [[ARRAYIDX6_3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[SPEC_SELECT_2]]88; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARRAYIDX6_3]], align 489; CHECK-NEXT: [[CMP7_3:%.*]] = icmp ult i32 [[TMP16]], [[TMP17]]90; CHECK-NEXT: [[SPEC_SELECT_3]] = select i1 [[CMP7_3]], i64 [[INC_2]], i64 [[SPEC_SELECT_2]]91; CHECK-NEXT: [[INC_3]] = add nuw i64 [[MIN_0_LCSSA]], 492; CHECK-NEXT: [[CMP3_3:%.*]] = icmp ult i64 [[INC_3]], [[TMP0]]93; CHECK-NEXT: br i1 [[CMP3_3]], label %[[FOR_BODY4]], label %[[FOR_END_LOOPEXIT_UNR_LCSSA:.*]]94; CHECK: [[FOR_END_LOOPEXIT_UNR_LCSSA]]:95; CHECK-NEXT: [[SPEC_SELECT_LCSSA_PH:%.*]] = phi i64 [ [[SPEC_SELECT_3]], %[[FOR_BODY4]] ]96; CHECK-NEXT: br label %[[FOR_END_LOOPEXIT]]97; CHECK: [[FOR_END_LOOPEXIT]]:98; CHECK-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT_LCSSA_UNR]], %[[FOR_BODY4_PROL_LOOPEXIT]] ], [ [[SPEC_SELECT_LCSSA_PH]], %[[FOR_END_LOOPEXIT_UNR_LCSSA]] ]99; CHECK-NEXT: br label %[[FOR_END]]100; CHECK: [[FOR_END]]:101; CHECK-NEXT: [[MIN_0_LCSSA1:%.*]] = phi i64 [ [[BASE_022]], %[[FOR_BODY]] ], [ [[SPEC_SELECT_LCSSA]], %[[FOR_END_LOOPEXIT]] ]102; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[MIN_0_LCSSA1]]103; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4104; CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[BASE_022]]105; CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4106; CHECK-NEXT: store i32 [[TMP19]], ptr [[ARRAYIDX10]], align 4107; CHECK-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX12]], align 4108; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[ADD]], [[TMP0]]109; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_END18_LOOPEXIT:.*]], label %[[FOR_BODY]]110; CHECK: [[FOR_END18_LOOPEXIT]]:111; CHECK-NEXT: br label %[[FOR_END18]]112; CHECK: [[FOR_END18]]:113; CHECK-NEXT: ret void114;115entry:116 %size = getelementptr inbounds nuw i8, ptr %array, i64 8117 %0 = load i64, ptr %size, align 8118 %cmp21.not = icmp eq i64 %0, 0119 br i1 %cmp21.not, label %for.end18, label %for.body.lr.ph120 121for.body.lr.ph: ; preds = %entry122 %1 = load ptr, ptr %array, align 8123 br label %for.body124 125for.body: ; preds = %for.body.lr.ph, %for.end126 %base.022 = phi i64 [ 0, %for.body.lr.ph ], [ %add, %for.end ]127 %add = add nuw i64 %base.022, 1128 %cmp318 = icmp ult i64 %add, %0129 br i1 %cmp318, label %for.body4, label %for.end130 131for.body4: ; preds = %for.body, %for.body4132 %min.020 = phi i64 [ %spec.select, %for.body4 ], [ %base.022, %for.body ]133 %c.019 = phi i64 [ %inc, %for.body4 ], [ %add, %for.body ]134 %arrayidx = getelementptr inbounds i32, ptr %1, i64 %c.019135 %2 = load i32, ptr %arrayidx, align 4136 %arrayidx6 = getelementptr inbounds i32, ptr %1, i64 %min.020137 %3 = load i32, ptr %arrayidx6, align 4138 %cmp7 = icmp ult i32 %2, %3139 %spec.select = select i1 %cmp7, i64 %c.019, i64 %min.020140 %inc = add nuw i64 %c.019, 1141 %cmp3 = icmp ult i64 %inc, %0142 br i1 %cmp3, label %for.body4, label %for.end143 144for.end: ; preds = %for.body4, %for.body145 %min.0.lcssa = phi i64 [ %base.022, %for.body ], [ %spec.select, %for.body4 ]146 %arrayidx9 = getelementptr inbounds i32, ptr %1, i64 %min.0.lcssa147 %4 = load i32, ptr %arrayidx9, align 4148 %arrayidx11 = getelementptr inbounds i32, ptr %1, i64 %base.022149 %5 = load i32, ptr %arrayidx11, align 4150 store i32 %5, ptr %arrayidx9, align 4151 store i32 %4, ptr %arrayidx11, align 4152 %exitcond.not = icmp eq i64 %add, %0153 br i1 %exitcond.not, label %for.end18, label %for.body154 155for.end18: ; preds = %for.end, %entry156 ret void157}158 159attributes #0 = { "tune-cpu"="generic" }160;.161; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]]}162; CHECK: [[META1]] = !{!"llvm.loop.unroll.disable"}163;.164