356 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes='loop-unroll<runtime;partial>' -S %s | FileCheck %s3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-ni:1-p2:32:8:8:32-ni:2"5 6; Make sure SCEVs for phis are properly invalidated after phis are modified.7 8declare void @llvm.experimental.deoptimize.isVoid(...)9 10declare i32 @get()11 12define void @pr56282() {13; CHECK-LABEL: @pr56282(14; CHECK-NEXT: entry:15; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]16; CHECK: outer.header:17; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[INNER_2:%.*]] ]18; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OUTER_IV]], 119; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[TMP0]]20; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], -121; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP1]], 722; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], 723; CHECK-NEXT: br i1 [[TMP3]], label [[INNER_1_HEADER_EPIL_PREHEADER:%.*]], label [[OUTER_HEADER_NEW:%.*]]24; CHECK: outer.header.new:25; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[TMP1]], [[XTRAITER]]26; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]]27; CHECK: inner.1.header:28; CHECK-NEXT: [[INNER_1_IV:%.*]] = phi i64 [ 0, [[OUTER_HEADER_NEW]] ], [ [[INNER_1_IV_NEXT_7:%.*]], [[INNER_1_LATCH_7:%.*]] ]29; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[OUTER_HEADER_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[INNER_1_LATCH_7]] ]30; CHECK-NEXT: [[V:%.*]] = call i32 @get()31; CHECK-NEXT: [[C_1:%.*]] = icmp ugt i32 [[V]], 032; CHECK-NEXT: br i1 [[C_1]], label [[INNER_1_LATCH:%.*]], label [[EXIT_DEOPT_LOOPEXIT:%.*]]33; CHECK: inner.1.latch:34; CHECK-NEXT: [[V_1:%.*]] = call i32 @get()35; CHECK-NEXT: [[C_1_1:%.*]] = icmp ugt i32 [[V_1]], 036; CHECK-NEXT: br i1 [[C_1_1]], label [[INNER_1_LATCH_1:%.*]], label [[EXIT_DEOPT_LOOPEXIT]]37; CHECK: inner.1.latch.1:38; CHECK-NEXT: [[V_2:%.*]] = call i32 @get()39; CHECK-NEXT: [[C_1_2:%.*]] = icmp ugt i32 [[V_2]], 040; CHECK-NEXT: br i1 [[C_1_2]], label [[INNER_1_LATCH_2:%.*]], label [[EXIT_DEOPT_LOOPEXIT]]41; CHECK: inner.1.latch.2:42; CHECK-NEXT: [[V_3:%.*]] = call i32 @get()43; CHECK-NEXT: [[C_1_3:%.*]] = icmp ugt i32 [[V_3]], 044; CHECK-NEXT: br i1 [[C_1_3]], label [[INNER_1_LATCH_3:%.*]], label [[EXIT_DEOPT_LOOPEXIT]]45; CHECK: inner.1.latch.3:46; CHECK-NEXT: [[V_4:%.*]] = call i32 @get()47; CHECK-NEXT: [[C_1_4:%.*]] = icmp ugt i32 [[V_4]], 048; CHECK-NEXT: br i1 [[C_1_4]], label [[INNER_1_LATCH_4:%.*]], label [[EXIT_DEOPT_LOOPEXIT]]49; CHECK: inner.1.latch.4:50; CHECK-NEXT: [[V_5:%.*]] = call i32 @get()51; CHECK-NEXT: [[C_1_5:%.*]] = icmp ugt i32 [[V_5]], 052; CHECK-NEXT: br i1 [[C_1_5]], label [[INNER_1_LATCH_5:%.*]], label [[EXIT_DEOPT_LOOPEXIT]]53; CHECK: inner.1.latch.5:54; CHECK-NEXT: [[V_6:%.*]] = call i32 @get()55; CHECK-NEXT: [[C_1_6:%.*]] = icmp ugt i32 [[V_6]], 056; CHECK-NEXT: br i1 [[C_1_6]], label [[INNER_1_LATCH_6:%.*]], label [[EXIT_DEOPT_LOOPEXIT]]57; CHECK: inner.1.latch.6:58; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add nuw nsw i64 [[INNER_1_IV]], 859; CHECK-NEXT: [[V_7:%.*]] = call i32 @get()60; CHECK-NEXT: [[C_1_7:%.*]] = icmp ugt i32 [[V_7]], 061; CHECK-NEXT: br i1 [[C_1_7]], label [[INNER_1_LATCH_7]], label [[EXIT_DEOPT_LOOPEXIT]]62; CHECK: inner.1.latch.7:63; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 864; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp ne i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]65; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[INNER_1_HEADER]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]]66; CHECK: outer.middle.unr-lcssa:67; CHECK-NEXT: [[V_LCSSA1_PH_PH:%.*]] = phi i32 [ [[V_7]], [[INNER_1_LATCH_7]] ]68; CHECK-NEXT: [[INNER_1_IV_UNR_PH:%.*]] = phi i64 [ [[INNER_1_IV_NEXT_7]], [[INNER_1_LATCH_7]] ]69; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 070; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[INNER_1_HEADER_EPIL_PREHEADER]], label [[OUTER_MIDDLE:%.*]]71; CHECK: inner.1.header.epil.preheader:72; CHECK-NEXT: [[INNER_1_IV_UNR:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ [[INNER_1_IV_UNR_PH]], [[OUTER_MIDDLE_UNR_LCSSA]] ]73; CHECK-NEXT: [[LCMP_MOD3:%.*]] = icmp ne i64 [[XTRAITER]], 074; CHECK-NEXT: call void @llvm.assume(i1 [[LCMP_MOD3]])75; CHECK-NEXT: br label [[INNER_1_HEADER_EPIL:%.*]]76; CHECK: inner.1.header.epil:77; CHECK-NEXT: [[INNER_1_IV_EPIL:%.*]] = phi i64 [ [[INNER_1_IV_UNR]], [[INNER_1_HEADER_EPIL_PREHEADER]] ], [ [[INNER_1_IV_NEXT_EPIL:%.*]], [[INNER_1_LATCH_EPIL:%.*]] ]78; CHECK-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ 0, [[INNER_1_HEADER_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], [[INNER_1_LATCH_EPIL]] ]79; CHECK-NEXT: [[INNER_1_IV_NEXT_EPIL]] = add nuw nsw i64 [[INNER_1_IV_EPIL]], 180; CHECK-NEXT: [[V_EPIL:%.*]] = call i32 @get()81; CHECK-NEXT: [[C_1_EPIL:%.*]] = icmp ugt i32 [[V_EPIL]], 082; CHECK-NEXT: br i1 [[C_1_EPIL]], label [[INNER_1_LATCH_EPIL]], label [[EXIT_DEOPT_LOOPEXIT3:%.*]]83; CHECK: inner.1.latch.epil:84; CHECK-NEXT: [[C_2_EPIL:%.*]] = icmp ult i64 [[INNER_1_IV_EPIL]], [[OUTER_IV]]85; CHECK-NEXT: [[EPIL_ITER_NEXT]] = add i64 [[EPIL_ITER]], 186; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i64 [[EPIL_ITER_NEXT]], [[XTRAITER]]87; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[INNER_1_HEADER_EPIL]], label [[OUTER_MIDDLE_EPILOG_LCSSA:%.*]], !llvm.loop [[LOOP0:![0-9]+]]88; CHECK: outer.middle.epilog-lcssa:89; CHECK-NEXT: [[V_LCSSA1_PH2:%.*]] = phi i32 [ [[V_EPIL]], [[INNER_1_LATCH_EPIL]] ]90; CHECK-NEXT: br label [[OUTER_MIDDLE]]91; CHECK: outer.middle:92; CHECK-NEXT: [[V_LCSSA1:%.*]] = phi i32 [ [[V_LCSSA1_PH_PH]], [[OUTER_MIDDLE_UNR_LCSSA]] ], [ [[V_LCSSA1_PH2]], [[OUTER_MIDDLE_EPILOG_LCSSA]] ]93; CHECK-NEXT: [[C_3:%.*]] = icmp ugt i32 [[V_LCSSA1]], 094; CHECK-NEXT: br i1 [[C_3]], label [[INNER_2_PREHEADER:%.*]], label [[EXIT:%.*]]95; CHECK: inner.2.preheader:96; CHECK-NEXT: br label [[INNER_2]]97; CHECK: inner.2:98; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nuw i64 [[OUTER_IV]], 199; CHECK-NEXT: br label [[OUTER_HEADER]]100; CHECK: exit:101; CHECK-NEXT: ret void102; CHECK: exit.deopt.loopexit:103; CHECK-NEXT: br label [[EXIT_DEOPT:%.*]]104; CHECK: exit.deopt.loopexit4:105; CHECK-NEXT: br label [[EXIT_DEOPT]]106; CHECK: exit.deopt:107; CHECK-NEXT: call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ]108; CHECK-NEXT: ret void109;110entry:111 br label %outer.header112 113outer.header:114 %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]115 br label %inner.1.header116 117inner.1.header:118 %inner.1.iv = phi i64 [ 0, %outer.header ], [ %inner.1.iv.next, %inner.1.latch ]119 %inner.1.iv.next = add nuw nsw i64 %inner.1.iv, 1120 %v = call i32 @get()121 %c.1 = icmp ugt i32 %v, 0122 br i1 %c.1, label %inner.1.latch, label %exit.deopt123 124inner.1.latch: ; preds = %inner.1.header125 %c.2 = icmp ult i64 %inner.1.iv, %outer.iv126 br i1 %c.2, label %inner.1.header, label %outer.middle127 128outer.middle:129 %c.3 = icmp ugt i32 %v, 0130 br i1 %c.3, label %inner.2, label %exit131 132inner.2:133 %inner.2.iv = phi i64 [ 0, %outer.middle ], [ %inner.2.iv.next, %inner.2 ]134 %inner.2.iv.next = add nsw i64 %inner.2.iv, -1135 %iv.trunc = trunc i64 %inner.2.iv to i32136 %c.4 = icmp ult i32 %v, %iv.trunc137 br i1 %c.4, label %inner.2, label %outer.latch138 139outer.latch:140 %outer.iv.next = add nuw nsw i64 %outer.iv, 1141 br label %outer.header142 143exit:144 ret void145 146exit.deopt:147 call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ]148 ret void149}150 151declare void @bar()152declare void @use.2(ptr, i32)153 154define void @pr56286(i64 %x, ptr %src, ptr %dst, ptr %ptr.src) !prof !0 {155; CHECK-LABEL: @pr56286(156; CHECK-NEXT: bb:157; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[X:%.*]], i64 1)158; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[SMAX]], 1159; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[X]]160; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]161; CHECK: outer.header:162; CHECK-NEXT: [[OUTER_P:%.*]] = phi i32 [ 0, [[BB:%.*]] ], [ [[L_1_LCSSA:%.*]], [[OUTER_LATCH:%.*]] ]163; CHECK-NEXT: [[TMP2:%.*]] = freeze i64 [[TMP1]]164; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], -1165; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP2]], 7166; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0167; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[INNER_1_HEADER_PROL_PREHEADER:%.*]], label [[INNER_1_HEADER_PROL_LOOPEXIT:%.*]], !prof [[PROF3:![0-9]+]]168; CHECK: inner.1.header.prol.preheader:169; CHECK-NEXT: br label [[INNER_1_HEADER_PROL:%.*]]170; CHECK: inner.1.header.prol:171; CHECK-NEXT: [[INNER_1_IV_PROL:%.*]] = phi i64 [ [[X]], [[INNER_1_HEADER_PROL_PREHEADER]] ], [ [[INNER_1_IV_NEXT_PROL:%.*]], [[INNER_1_LATCH_PROL:%.*]] ]172; CHECK-NEXT: [[PROL_ITER:%.*]] = phi i64 [ 0, [[INNER_1_HEADER_PROL_PREHEADER]] ], [ [[PROL_ITER_NEXT:%.*]], [[INNER_1_LATCH_PROL]] ]173; CHECK-NEXT: [[CMP_1_PROL:%.*]] = icmp sgt i32 [[OUTER_P]], 0174; CHECK-NEXT: br i1 [[CMP_1_PROL]], label [[EXIT_DEOPT_LOOPEXIT1:%.*]], label [[INNER_1_LATCH_PROL]]175; CHECK: inner.1.latch.prol:176; CHECK-NEXT: [[L_1_PROL:%.*]] = load i32, ptr [[SRC:%.*]], align 4177; CHECK-NEXT: store i32 [[L_1_PROL]], ptr [[DST:%.*]], align 8178; CHECK-NEXT: [[INNER_1_IV_NEXT_PROL]] = add i64 [[INNER_1_IV_PROL]], 1179; CHECK-NEXT: [[CMP_2_PROL:%.*]] = icmp sgt i64 [[INNER_1_IV_PROL]], 0180; CHECK-NEXT: [[PROL_ITER_NEXT]] = add i64 [[PROL_ITER]], 1181; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i64 [[PROL_ITER_NEXT]], [[XTRAITER]]182; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[INNER_1_HEADER_PROL]], label [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !prof [[PROF4:![0-9]+]], !llvm.loop [[LOOP5:![0-9]+]]183; CHECK: inner.1.header.prol.loopexit.unr-lcssa:184; CHECK-NEXT: [[L_1_LCSSA_UNR_PH:%.*]] = phi i32 [ [[L_1_PROL]], [[INNER_1_LATCH_PROL]] ]185; CHECK-NEXT: [[INNER_1_IV_UNR_PH:%.*]] = phi i64 [ [[INNER_1_IV_NEXT_PROL]], [[INNER_1_LATCH_PROL]] ]186; CHECK-NEXT: br label [[INNER_1_HEADER_PROL_LOOPEXIT]]187; CHECK: inner.1.header.prol.loopexit:188; CHECK-NEXT: [[L_1_LCSSA_UNR:%.*]] = phi i32 [ poison, [[OUTER_HEADER]] ], [ [[L_1_LCSSA_UNR_PH]], [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ]189; CHECK-NEXT: [[INNER_1_IV_UNR:%.*]] = phi i64 [ [[X]], [[OUTER_HEADER]] ], [ [[INNER_1_IV_UNR_PH]], [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ]190; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 7191; CHECK-NEXT: br i1 [[TMP4]], label [[OUTER_MIDDLE:%.*]], label [[OUTER_HEADER_NEW:%.*]], !prof [[PROF6:![0-9]+]]192; CHECK: outer.header.new:193; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]]194; CHECK: inner.1.header:195; CHECK-NEXT: [[INNER_1_IV:%.*]] = phi i64 [ [[INNER_1_IV_UNR]], [[OUTER_HEADER_NEW]] ], [ [[INNER_1_IV_NEXT_7:%.*]], [[INNER_1_LATCH_7:%.*]] ]196; CHECK-NEXT: [[CMP_1:%.*]] = icmp sgt i32 [[OUTER_P]], 0197; CHECK-NEXT: br i1 [[CMP_1]], label [[EXIT_DEOPT_LOOPEXIT:%.*]], label [[INNER_1_LATCH:%.*]]198; CHECK: inner.1.latch:199; CHECK-NEXT: [[L_1:%.*]] = load i32, ptr [[SRC]], align 4200; CHECK-NEXT: store i32 [[L_1]], ptr [[DST]], align 8201; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_1:%.*]]202; CHECK: inner.1.latch.1:203; CHECK-NEXT: [[L_1_1:%.*]] = load i32, ptr [[SRC]], align 4204; CHECK-NEXT: store i32 [[L_1_1]], ptr [[DST]], align 8205; CHECK-NEXT: [[CMP_1_2:%.*]] = icmp sgt i32 [[OUTER_P]], 0206; CHECK-NEXT: br i1 [[CMP_1_2]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_2:%.*]]207; CHECK: inner.1.latch.2:208; CHECK-NEXT: [[L_1_2:%.*]] = load i32, ptr [[SRC]], align 4209; CHECK-NEXT: store i32 [[L_1_2]], ptr [[DST]], align 8210; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_3:%.*]]211; CHECK: inner.1.latch.3:212; CHECK-NEXT: [[L_1_3:%.*]] = load i32, ptr [[SRC]], align 4213; CHECK-NEXT: store i32 [[L_1_3]], ptr [[DST]], align 8214; CHECK-NEXT: [[CMP_1_4:%.*]] = icmp sgt i32 [[OUTER_P]], 0215; CHECK-NEXT: br i1 [[CMP_1_4]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_4:%.*]]216; CHECK: inner.1.latch.4:217; CHECK-NEXT: [[L_1_4:%.*]] = load i32, ptr [[SRC]], align 4218; CHECK-NEXT: store i32 [[L_1_4]], ptr [[DST]], align 8219; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_5:%.*]]220; CHECK: inner.1.latch.5:221; CHECK-NEXT: [[L_1_5:%.*]] = load i32, ptr [[SRC]], align 4222; CHECK-NEXT: store i32 [[L_1_5]], ptr [[DST]], align 8223; CHECK-NEXT: [[CMP_1_6:%.*]] = icmp sgt i32 [[OUTER_P]], 0224; CHECK-NEXT: br i1 [[CMP_1_6]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_6:%.*]]225; CHECK: inner.1.latch.6:226; CHECK-NEXT: [[L_1_6:%.*]] = load i32, ptr [[SRC]], align 4227; CHECK-NEXT: store i32 [[L_1_6]], ptr [[DST]], align 8228; CHECK-NEXT: [[INNER_1_IV_NEXT_6:%.*]] = add i64 [[INNER_1_IV]], 7229; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_7]]230; CHECK: inner.1.latch.7:231; CHECK-NEXT: [[L_1_7:%.*]] = load i32, ptr [[SRC]], align 4232; CHECK-NEXT: store i32 [[L_1_7]], ptr [[DST]], align 8233; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add i64 [[INNER_1_IV]], 8234; CHECK-NEXT: [[CMP_2_7:%.*]] = icmp sgt i64 [[INNER_1_IV_NEXT_6]], 0235; CHECK-NEXT: br i1 [[CMP_2_7]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[INNER_1_HEADER]], !prof [[PROF7:![0-9]+]], !llvm.loop [[LOOP8:![0-9]+]]236; CHECK: outer.middle.unr-lcssa:237; CHECK-NEXT: [[L_1_LCSSA_PH:%.*]] = phi i32 [ [[L_1_7]], [[INNER_1_LATCH_7]] ]238; CHECK-NEXT: br label [[OUTER_MIDDLE]]239; CHECK: outer.middle:240; CHECK-NEXT: [[L_1_LCSSA]] = phi i32 [ [[L_1_LCSSA_UNR]], [[INNER_1_HEADER_PROL_LOOPEXIT]] ], [ [[L_1_LCSSA_PH]], [[OUTER_MIDDLE_UNR_LCSSA]] ]241; CHECK-NEXT: br label [[INNER_2:%.*]]242; CHECK: inner.2:243; CHECK-NEXT: [[INNER_2_IV:%.*]] = phi i32 [ [[L_1_LCSSA]], [[OUTER_MIDDLE]] ], [ [[INNER_2_IV_NEXT_2:%.*]], [[INNER_2]] ]244; CHECK-NEXT: [[TMP15:%.*]] = phi i32 [ 0, [[OUTER_MIDDLE]] ], [ [[TMP33_2:%.*]], [[INNER_2]] ]245; CHECK-NEXT: [[L_2:%.*]] = load i32, ptr [[SRC]], align 8246; CHECK-NEXT: [[INNER_2_IV_NEXT:%.*]] = add i32 [[INNER_2_IV]], 1247; CHECK-NEXT: [[TMP27:%.*]] = load ptr, ptr [[PTR_SRC:%.*]], align 8248; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[INNER_2_IV]], [[L_2]]249; CHECK-NEXT: [[TMP281:%.*]] = call i32 @use.2(ptr [[TMP27]], i32 [[ADD_1]])250; CHECK-NEXT: [[TMP31:%.*]] = shl nuw nsw i32 [[TMP15]], 16251; CHECK-NEXT: call void @bar()252; CHECK-NEXT: call void @bar()253; CHECK-NEXT: call void @bar()254; CHECK-NEXT: call void @bar()255; CHECK-NEXT: call void @bar()256; CHECK-NEXT: call void @bar()257; CHECK-NEXT: call void @bar()258; CHECK-NEXT: call void @bar()259; CHECK-NEXT: [[L_2_1:%.*]] = load i32, ptr [[SRC]], align 8260; CHECK-NEXT: [[INNER_2_IV_NEXT_1:%.*]] = add i32 [[INNER_2_IV]], 2261; CHECK-NEXT: [[TMP27_1:%.*]] = load ptr, ptr [[PTR_SRC]], align 8262; CHECK-NEXT: [[ADD_1_1:%.*]] = add i32 [[INNER_2_IV_NEXT]], [[L_2_1]]263; CHECK-NEXT: [[TMP281_1:%.*]] = call i32 @use.2(ptr [[TMP27_1]], i32 [[ADD_1_1]])264; CHECK-NEXT: [[TMP32_1:%.*]] = add nuw i32 [[TMP31]], 524288265; CHECK-NEXT: call void @bar()266; CHECK-NEXT: call void @bar()267; CHECK-NEXT: call void @bar()268; CHECK-NEXT: call void @bar()269; CHECK-NEXT: call void @bar()270; CHECK-NEXT: call void @bar()271; CHECK-NEXT: call void @bar()272; CHECK-NEXT: call void @bar()273; CHECK-NEXT: [[L_2_2:%.*]] = load i32, ptr [[SRC]], align 8274; CHECK-NEXT: [[INNER_2_IV_NEXT_2]] = add i32 [[INNER_2_IV]], 3275; CHECK-NEXT: [[TMP27_2:%.*]] = load ptr, ptr [[PTR_SRC]], align 8276; CHECK-NEXT: [[ADD_1_2:%.*]] = add i32 [[INNER_2_IV_NEXT_1]], [[L_2_2]]277; CHECK-NEXT: [[TMP281_2:%.*]] = call i32 @use.2(ptr [[TMP27_2]], i32 [[ADD_1_2]])278; CHECK-NEXT: [[TMP32_2:%.*]] = add nuw i32 [[TMP31]], 786432279; CHECK-NEXT: [[TMP33_2]] = ashr exact i32 [[TMP32_2]], 16280; CHECK-NEXT: call void @bar()281; CHECK-NEXT: call void @bar()282; CHECK-NEXT: call void @bar()283; CHECK-NEXT: call void @bar()284; CHECK-NEXT: call void @bar()285; CHECK-NEXT: call void @bar()286; CHECK-NEXT: call void @bar()287; CHECK-NEXT: call void @bar()288; CHECK-NEXT: [[CMP_3_2:%.*]] = icmp sgt i32 [[TMP32_1]], 2031616289; CHECK-NEXT: br i1 [[CMP_3_2]], label [[OUTER_LATCH]], label [[INNER_2]]290; CHECK: outer.latch:291; CHECK-NEXT: br label [[OUTER_HEADER]]292; CHECK: exit.deopt.loopexit:293; CHECK-NEXT: br label [[EXIT_DEOPT:%.*]]294; CHECK: exit.deopt.loopexit1:295; CHECK-NEXT: br label [[EXIT_DEOPT]]296; CHECK: exit.deopt:297; CHECK-NEXT: call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ]298; CHECK-NEXT: ret void299;300bb:301 br label %outer.header302 303outer.header:304 %outer.p = phi i32 [ 0, %bb ], [ %l.1, %outer.latch ]305 br label %inner.1.header306 307inner.1.header:308 %inner.1.iv = phi i64 [ %x, %outer.header ], [ %inner.1.iv.next, %inner.1.latch ]309 %cmp.1 = icmp sgt i32 %outer.p, 0310 br i1 %cmp.1, label %exit.deopt, label %inner.1.latch311 312inner.1.latch:313 %l.1 = load i32, ptr %src, align 4314 store i32 %l.1, ptr %dst, align 8315 %inner.1.iv.next = add i64 %inner.1.iv, 1316 %cmp.2 = icmp sgt i64 %inner.1.iv, 0317 br i1 %cmp.2, label %outer.middle, label %inner.1.header, !prof !1318 319outer.middle:320 br label %inner.2321 322inner.2:323 %inner.2.iv = phi i32 [ %l.1, %outer.middle ], [ %inner.2.iv.next, %inner.2 ]324 %tmp15 = phi i32 [ 0, %outer.middle ], [ %tmp33, %inner.2 ]325 %l.2 = load i32, ptr %src , align 8326 %l.3 = load i32, ptr %dst, align 4327 %inner.2.iv.next = add i32 %inner.2.iv, 1328 %tmp27 = load ptr, ptr %ptr.src329 %add.1 = add i32 %inner.2.iv, %l.2330 %add.2 = add i32 %add.1, %l.3331 %tmp281 = call i32 @use.2(ptr %tmp27, i32 %add.1)332 %tmp31 = shl nuw nsw i32 %tmp15, 16333 %tmp32 = add nuw i32 %tmp31, 262144334 %tmp33 = ashr exact i32 %tmp32, 16335 call void @bar()336 call void @bar()337 call void @bar()338 call void @bar()339 call void @bar()340 call void @bar()341 call void @bar()342 call void @bar()343 %cmp.3 = icmp sgt i32 %tmp31, 2031616344 br i1 %cmp.3, label %outer.latch, label %inner.2345 346outer.latch:347 br label %outer.header348 349exit.deopt:350 call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ]351 ret void352}353 354!0 = !{!"function_entry_count", i64 32768}355!1 = !{!"branch_weights", i32 1, i32 32}356