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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=loop-unroll-and-jam -allow-unroll-and-jam -unroll-and-jam-count=4 < %s -S | FileCheck %s3 4target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"5 6define void @test1() {7; CHECK-LABEL: @test1(8; CHECK-NEXT: bb:9; CHECK-NEXT: br i1 false, label [[BB5_PREHEADER_EPIL_PREHEADER:%.*]], label [[BB_NEW:%.*]]10; CHECK: bb.new:11; CHECK-NEXT: br label [[BB5_PREHEADER:%.*]]12; CHECK: bb5.preheader:13; CHECK-NEXT: [[I10:%.*]] = phi i16 [ 0, [[BB_NEW]] ], [ [[I42_3:%.*]], [[BB38:%.*]] ]14; CHECK-NEXT: [[NITER:%.*]] = phi i16 [ 0, [[BB_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[BB38]] ]15; CHECK-NEXT: [[I4017:%.*]] = zext i16 [[I10]] to i6416; CHECK-NEXT: [[I13_I:%.*]] = add nuw nsw i64 [[I4017]], 117; CHECK-NEXT: [[I42:%.*]] = trunc i64 [[I13_I]] to i1618; CHECK-NEXT: [[I4017_1:%.*]] = zext i16 [[I42]] to i6419; CHECK-NEXT: [[I13_I_1:%.*]] = add nuw nsw i64 [[I4017_1]], 120; CHECK-NEXT: [[I42_1:%.*]] = trunc i64 [[I13_I_1]] to i1621; CHECK-NEXT: [[I4017_2:%.*]] = zext i16 [[I42_1]] to i6422; CHECK-NEXT: [[I13_I_2:%.*]] = add nuw nsw i64 [[I4017_2]], 123; CHECK-NEXT: [[I42_2:%.*]] = trunc i64 [[I13_I_2]] to i1624; CHECK-NEXT: [[I4017_3:%.*]] = zext i16 [[I42_2]] to i6425; CHECK-NEXT: [[I13_I_3:%.*]] = add nuw nsw i64 [[I4017_3]], 126; CHECK-NEXT: [[I42_3]] = trunc i64 [[I13_I_3]] to i1627; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw i16 [[NITER]], 428; CHECK-NEXT: br label [[BB10_PREHEADER:%.*]]29; CHECK: bb10.preheader:30; CHECK-NEXT: br i1 true, label [[BB38]], label [[BB10_PREHEADER]]31; CHECK: bb38:32; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i16 [[NITER_NEXT_3]], -2833; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label [[BB1_BB43_CRIT_EDGE_UNR_LCSSA:%.*]], label [[BB5_PREHEADER]], !llvm.loop [[LOOP0:![0-9]+]]34; CHECK: bb1.bb43_crit_edge.unr-lcssa:35; CHECK-NEXT: [[I10_UNR:%.*]] = phi i16 [ [[I42_3]], [[BB38]] ]36; CHECK-NEXT: br i1 true, label [[BB5_PREHEADER_EPIL_PREHEADER]], label [[BB1_BB43_CRIT_EDGE:%.*]]37; CHECK: bb5.preheader.epil.preheader:38; CHECK-NEXT: [[I10_EPIL_INIT:%.*]] = phi i16 [ 0, [[BB:%.*]] ], [ [[I10_UNR]], [[BB1_BB43_CRIT_EDGE_UNR_LCSSA]] ]39; CHECK-NEXT: call void @llvm.assume(i1 true)40; CHECK-NEXT: br label [[BB5_PREHEADER_EPIL:%.*]]41; CHECK: bb5.preheader.epil:42; CHECK-NEXT: [[I10_EPIL:%.*]] = phi i16 [ [[I10_EPIL_INIT]], [[BB5_PREHEADER_EPIL_PREHEADER]] ], [ [[I42_EPIL:%.*]], [[BB38_EPIL:%.*]] ]43; CHECK-NEXT: [[EPIL_ITER:%.*]] = phi i16 [ 0, [[BB5_PREHEADER_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], [[BB38_EPIL]] ]44; CHECK-NEXT: br label [[BB10_PREHEADER_EPIL:%.*]]45; CHECK: bb10.preheader.epil:46; CHECK-NEXT: br i1 true, label [[BB38_EPIL]], label [[BB10_PREHEADER_EPIL]]47; CHECK: bb38.epil:48; CHECK-NEXT: [[I4017_EPIL:%.*]] = zext i16 [[I10_EPIL]] to i6449; CHECK-NEXT: [[I13_I_EPIL:%.*]] = add i64 [[I4017_EPIL]], 150; CHECK-NEXT: [[I14_I_EPIL:%.*]] = select i1 true, i64 [[I13_I_EPIL]], i64 [[I4017_EPIL]]51; CHECK-NEXT: [[I42_EPIL]] = trunc i64 [[I14_I_EPIL]] to i1652; CHECK-NEXT: [[I3_NOT_EPIL:%.*]] = icmp eq i16 [[I10_EPIL]], -2753; CHECK-NEXT: [[EPIL_ITER_NEXT]] = add i16 [[EPIL_ITER]], 154; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i16 [[EPIL_ITER_NEXT]], 255; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[BB5_PREHEADER_EPIL]], label [[BB1_BB43_CRIT_EDGE_EPILOG_LCSSA:%.*]], !llvm.loop [[LOOP2:![0-9]+]]56; CHECK: bb1.bb43_crit_edge.epilog-lcssa:57; CHECK-NEXT: br label [[BB1_BB43_CRIT_EDGE]]58; CHECK: bb1.bb43_crit_edge:59; CHECK-NEXT: ret void60;61bb:62 br label %bb5.preheader63 64bb5.preheader: ; preds = %bb38, %bb65 %i10 = phi i16 [ 0, %bb ], [ %i42, %bb38 ]66 br label %bb10.preheader67 68bb10.preheader: ; preds = %bb10.preheader, %bb5.preheader69 br i1 true, label %bb38, label %bb10.preheader70 71bb38: ; preds = %bb10.preheader72 %i4017 = zext i16 %i10 to i6473 %i13.i = add i64 %i4017, 174 %i14.i = select i1 true, i64 %i13.i, i64 %i401775 %i42 = trunc i64 %i14.i to i1676 %i3.not = icmp eq i16 %i10, -2777 br i1 %i3.not, label %bb1.bb43_crit_edge, label %bb5.preheader78 79bb1.bb43_crit_edge: ; preds = %bb3880 ret void81}82