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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -S %s | FileCheck %s3 4target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32"5target triple = "arm64-apple-macosx14.0.0"6 7define void @test_blend_feeding_replicated_store_1(i64 %N, ptr noalias %src, ptr %dst) {8; CHECK-LABEL: define void @test_blend_feeding_replicated_store_1(9; CHECK-SAME: i64 [[N:%.*]], ptr noalias [[SRC:%.*]], ptr [[DST:%.*]]) {10; CHECK-NEXT: [[ENTRY:.*]]:11; CHECK-NEXT: [[TMP43:%.*]] = add i64 [[N]], 112; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP43]], 1613; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]14; CHECK: [[VECTOR_PH]]:15; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP43]], 1616; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[N_MOD_VF]], 017; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i64 16, i64 [[N_MOD_VF]]18; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP43]], [[TMP2]]19; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]20; CHECK: [[VECTOR_BODY]]:21; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE30:.*]] ]22; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]23; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i32>, ptr [[TMP4]], align 424; CHECK-NEXT: [[TMP5:%.*]] = icmp sge <16 x i32> [[WIDE_LOAD]], zeroinitializer25; CHECK-NEXT: [[TMP21:%.*]] = extractelement <16 x i1> [[TMP5]], i32 026; CHECK-NEXT: br i1 [[TMP21]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]27; CHECK: [[PRED_STORE_IF]]:28; CHECK-NEXT: store i8 0, ptr null, align 129; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]30; CHECK: [[PRED_STORE_CONTINUE]]:31; CHECK-NEXT: [[TMP6:%.*]] = extractelement <16 x i1> [[TMP5]], i32 132; CHECK-NEXT: br i1 [[TMP6]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]33; CHECK: [[PRED_STORE_IF1]]:34; CHECK-NEXT: store i8 0, ptr null, align 135; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE2]]36; CHECK: [[PRED_STORE_CONTINUE2]]:37; CHECK-NEXT: [[TMP7:%.*]] = extractelement <16 x i1> [[TMP5]], i32 238; CHECK-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]39; CHECK: [[PRED_STORE_IF3]]:40; CHECK-NEXT: store i8 0, ptr null, align 141; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]42; CHECK: [[PRED_STORE_CONTINUE4]]:43; CHECK-NEXT: [[TMP8:%.*]] = extractelement <16 x i1> [[TMP5]], i32 344; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]45; CHECK: [[PRED_STORE_IF5]]:46; CHECK-NEXT: store i8 0, ptr null, align 147; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]48; CHECK: [[PRED_STORE_CONTINUE6]]:49; CHECK-NEXT: [[TMP9:%.*]] = extractelement <16 x i1> [[TMP5]], i32 450; CHECK-NEXT: br i1 [[TMP9]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]51; CHECK: [[PRED_STORE_IF7]]:52; CHECK-NEXT: store i8 0, ptr null, align 153; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE8]]54; CHECK: [[PRED_STORE_CONTINUE8]]:55; CHECK-NEXT: [[TMP10:%.*]] = extractelement <16 x i1> [[TMP5]], i32 556; CHECK-NEXT: br i1 [[TMP10]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]57; CHECK: [[PRED_STORE_IF9]]:58; CHECK-NEXT: store i8 0, ptr null, align 159; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE10]]60; CHECK: [[PRED_STORE_CONTINUE10]]:61; CHECK-NEXT: [[TMP11:%.*]] = extractelement <16 x i1> [[TMP5]], i32 662; CHECK-NEXT: br i1 [[TMP11]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]63; CHECK: [[PRED_STORE_IF11]]:64; CHECK-NEXT: store i8 0, ptr null, align 165; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE12]]66; CHECK: [[PRED_STORE_CONTINUE12]]:67; CHECK-NEXT: [[TMP12:%.*]] = extractelement <16 x i1> [[TMP5]], i32 768; CHECK-NEXT: br i1 [[TMP12]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14:.*]]69; CHECK: [[PRED_STORE_IF13]]:70; CHECK-NEXT: store i8 0, ptr null, align 171; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE14]]72; CHECK: [[PRED_STORE_CONTINUE14]]:73; CHECK-NEXT: [[TMP13:%.*]] = extractelement <16 x i1> [[TMP5]], i32 874; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_STORE_IF15:.*]], label %[[PRED_STORE_CONTINUE16:.*]]75; CHECK: [[PRED_STORE_IF15]]:76; CHECK-NEXT: store i8 0, ptr null, align 177; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE16]]78; CHECK: [[PRED_STORE_CONTINUE16]]:79; CHECK-NEXT: [[TMP14:%.*]] = extractelement <16 x i1> [[TMP5]], i32 980; CHECK-NEXT: br i1 [[TMP14]], label %[[PRED_STORE_IF17:.*]], label %[[PRED_STORE_CONTINUE18:.*]]81; CHECK: [[PRED_STORE_IF17]]:82; CHECK-NEXT: store i8 0, ptr null, align 183; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE18]]84; CHECK: [[PRED_STORE_CONTINUE18]]:85; CHECK-NEXT: [[TMP15:%.*]] = extractelement <16 x i1> [[TMP5]], i32 1086; CHECK-NEXT: br i1 [[TMP15]], label %[[PRED_STORE_IF19:.*]], label %[[PRED_STORE_CONTINUE20:.*]]87; CHECK: [[PRED_STORE_IF19]]:88; CHECK-NEXT: store i8 0, ptr null, align 189; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE20]]90; CHECK: [[PRED_STORE_CONTINUE20]]:91; CHECK-NEXT: [[TMP16:%.*]] = extractelement <16 x i1> [[TMP5]], i32 1192; CHECK-NEXT: br i1 [[TMP16]], label %[[PRED_STORE_IF21:.*]], label %[[PRED_STORE_CONTINUE22:.*]]93; CHECK: [[PRED_STORE_IF21]]:94; CHECK-NEXT: store i8 0, ptr null, align 195; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE22]]96; CHECK: [[PRED_STORE_CONTINUE22]]:97; CHECK-NEXT: [[TMP17:%.*]] = extractelement <16 x i1> [[TMP5]], i32 1298; CHECK-NEXT: br i1 [[TMP17]], label %[[PRED_STORE_IF23:.*]], label %[[PRED_STORE_CONTINUE24:.*]]99; CHECK: [[PRED_STORE_IF23]]:100; CHECK-NEXT: store i8 0, ptr null, align 1101; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE24]]102; CHECK: [[PRED_STORE_CONTINUE24]]:103; CHECK-NEXT: [[TMP18:%.*]] = extractelement <16 x i1> [[TMP5]], i32 13104; CHECK-NEXT: br i1 [[TMP18]], label %[[PRED_STORE_IF25:.*]], label %[[PRED_STORE_CONTINUE26:.*]]105; CHECK: [[PRED_STORE_IF25]]:106; CHECK-NEXT: store i8 0, ptr null, align 1107; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE26]]108; CHECK: [[PRED_STORE_CONTINUE26]]:109; CHECK-NEXT: [[TMP19:%.*]] = extractelement <16 x i1> [[TMP5]], i32 14110; CHECK-NEXT: br i1 [[TMP19]], label %[[PRED_STORE_IF27:.*]], label %[[PRED_STORE_CONTINUE28:.*]]111; CHECK: [[PRED_STORE_IF27]]:112; CHECK-NEXT: store i8 0, ptr null, align 1113; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE28]]114; CHECK: [[PRED_STORE_CONTINUE28]]:115; CHECK-NEXT: [[TMP20:%.*]] = extractelement <16 x i1> [[TMP5]], i32 15116; CHECK-NEXT: br i1 [[TMP20]], label %[[PRED_STORE_IF29:.*]], label %[[PRED_STORE_CONTINUE30]]117; CHECK: [[PRED_STORE_IF29]]:118; CHECK-NEXT: store i8 0, ptr null, align 1119; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE30]]120; CHECK: [[PRED_STORE_CONTINUE30]]:121; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16122; CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]123; CHECK-NEXT: br i1 [[TMP42]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]124; CHECK: [[MIDDLE_BLOCK]]:125; CHECK-NEXT: br label %[[SCALAR_PH]]126; CHECK: [[SCALAR_PH]]:127; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]128; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]129; CHECK: [[LOOP_HEADER]]:130; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]131; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]132; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[CONTINUE:.*]]133; CHECK: [[CONTINUE]]:134; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]]135; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP_SRC]], align 4136; CHECK-NEXT: [[CMP2_NOT:%.*]] = icmp slt i32 [[TMP0]], 0137; CHECK-NEXT: br i1 [[CMP2_NOT]], label %[[THEN:.*]], label %[[THEN_2:.*]]138; CHECK: [[THEN]]:139; CHECK-NEXT: br i1 false, label %[[THEN_2]], label %[[LOOP_LATCH]]140; CHECK: [[THEN_2]]:141; CHECK-NEXT: [[P:%.*]] = phi ptr [ null, %[[CONTINUE]] ], [ [[DST]], %[[THEN]] ]142; CHECK-NEXT: store i8 0, ptr [[P]], align 1143; CHECK-NEXT: br label %[[LOOP_LATCH]]144; CHECK: [[LOOP_LATCH]]:145; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1146; CHECK-NEXT: br label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]147; CHECK: [[EXIT]]:148; CHECK-NEXT: ret void149;150entry:151 br label %loop.header152 153loop.header: ; preds = %loop.latch, %entry154 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]155 %ec = icmp eq i64 %iv, %N156 br i1 %ec, label %exit, label %continue157 158continue:159 %gep.src = getelementptr inbounds i32, ptr %src, i64 %iv160 %0 = load i32, ptr %gep.src, align 4161 %cmp2.not = icmp slt i32 %0, 0162 br i1 %cmp2.not, label %then, label %then.2163 164then:165 br i1 false, label %then.2, label %loop.latch166 167then.2:168 %p = phi ptr [ null, %continue ], [ %dst, %then ]169 store i8 0, ptr %p, align 1170 br label %loop.latch171 172loop.latch:173 %iv.next = add i64 %iv, 1174 br label %loop.header175 176exit:177 ret void178}179 180define void @test_blend_feeding_replicated_store_2(ptr noalias %src, ptr %dst, i1 %c.0) {181; CHECK-LABEL: define void @test_blend_feeding_replicated_store_2(182; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr [[DST:%.*]], i1 [[C_0:%.*]]) {183; CHECK-NEXT: [[ENTRY:.*:]]184; CHECK-NEXT: br label %[[VECTOR_PH:.*]]185; CHECK: [[VECTOR_PH]]:186; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i1> poison, i1 [[C_0]], i64 0187; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i1> [[BROADCAST_SPLATINSERT]], <16 x i1> poison, <16 x i32> zeroinitializer188; CHECK-NEXT: [[TMP5:%.*]] = xor <16 x i1> [[BROADCAST_SPLAT]], splat (i1 true)189; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]190; CHECK: [[VECTOR_BODY]]:191; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE30:.*]] ]192; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i32 [[IV]]193; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[GEP_SRC]], align 1194; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <16 x i8> [[WIDE_LOAD]], zeroinitializer195; CHECK-NEXT: [[TMP4:%.*]] = xor <16 x i1> [[TMP3]], splat (i1 true)196; CHECK-NEXT: [[TMP6:%.*]] = select <16 x i1> [[TMP4]], <16 x i1> [[TMP5]], <16 x i1> zeroinitializer197; CHECK-NEXT: [[TMP7:%.*]] = or <16 x i1> [[TMP6]], [[TMP3]]198; CHECK-NEXT: [[PREDPHI:%.*]] = select <16 x i1> [[TMP3]], <16 x i8> splat (i8 1), <16 x i8> zeroinitializer199; CHECK-NEXT: [[TMP8:%.*]] = extractelement <16 x i1> [[TMP7]], i32 0200; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]201; CHECK: [[PRED_STORE_IF]]:202; CHECK-NEXT: [[TMP72:%.*]] = add i32 [[IV]], 0203; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP72]]204; CHECK-NEXT: [[TMP10:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 0205; CHECK-NEXT: store i8 [[TMP10]], ptr [[TMP9]], align 1206; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]207; CHECK: [[PRED_STORE_CONTINUE]]:208; CHECK-NEXT: [[TMP11:%.*]] = extractelement <16 x i1> [[TMP7]], i32 1209; CHECK-NEXT: br i1 [[TMP11]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]210; CHECK: [[PRED_STORE_IF1]]:211; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[IV]], 1212; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP12]]213; CHECK-NEXT: [[TMP14:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 1214; CHECK-NEXT: store i8 [[TMP14]], ptr [[TMP13]], align 1215; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE2]]216; CHECK: [[PRED_STORE_CONTINUE2]]:217; CHECK-NEXT: [[TMP15:%.*]] = extractelement <16 x i1> [[TMP7]], i32 2218; CHECK-NEXT: br i1 [[TMP15]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]219; CHECK: [[PRED_STORE_IF3]]:220; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[IV]], 2221; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP16]]222; CHECK-NEXT: [[TMP18:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 2223; CHECK-NEXT: store i8 [[TMP18]], ptr [[TMP17]], align 1224; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]225; CHECK: [[PRED_STORE_CONTINUE4]]:226; CHECK-NEXT: [[TMP19:%.*]] = extractelement <16 x i1> [[TMP7]], i32 3227; CHECK-NEXT: br i1 [[TMP19]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]228; CHECK: [[PRED_STORE_IF5]]:229; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[IV]], 3230; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP20]]231; CHECK-NEXT: [[TMP22:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 3232; CHECK-NEXT: store i8 [[TMP22]], ptr [[TMP21]], align 1233; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]234; CHECK: [[PRED_STORE_CONTINUE6]]:235; CHECK-NEXT: [[TMP23:%.*]] = extractelement <16 x i1> [[TMP7]], i32 4236; CHECK-NEXT: br i1 [[TMP23]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]237; CHECK: [[PRED_STORE_IF7]]:238; CHECK-NEXT: [[TMP24:%.*]] = add i32 [[IV]], 4239; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP24]]240; CHECK-NEXT: [[TMP26:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 4241; CHECK-NEXT: store i8 [[TMP26]], ptr [[TMP25]], align 1242; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE8]]243; CHECK: [[PRED_STORE_CONTINUE8]]:244; CHECK-NEXT: [[TMP27:%.*]] = extractelement <16 x i1> [[TMP7]], i32 5245; CHECK-NEXT: br i1 [[TMP27]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]246; CHECK: [[PRED_STORE_IF9]]:247; CHECK-NEXT: [[TMP28:%.*]] = add i32 [[IV]], 5248; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP28]]249; CHECK-NEXT: [[TMP30:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 5250; CHECK-NEXT: store i8 [[TMP30]], ptr [[TMP29]], align 1251; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE10]]252; CHECK: [[PRED_STORE_CONTINUE10]]:253; CHECK-NEXT: [[TMP31:%.*]] = extractelement <16 x i1> [[TMP7]], i32 6254; CHECK-NEXT: br i1 [[TMP31]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]255; CHECK: [[PRED_STORE_IF11]]:256; CHECK-NEXT: [[TMP32:%.*]] = add i32 [[IV]], 6257; CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP32]]258; CHECK-NEXT: [[TMP34:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 6259; CHECK-NEXT: store i8 [[TMP34]], ptr [[TMP33]], align 1260; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE12]]261; CHECK: [[PRED_STORE_CONTINUE12]]:262; CHECK-NEXT: [[TMP35:%.*]] = extractelement <16 x i1> [[TMP7]], i32 7263; CHECK-NEXT: br i1 [[TMP35]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14:.*]]264; CHECK: [[PRED_STORE_IF13]]:265; CHECK-NEXT: [[TMP36:%.*]] = add i32 [[IV]], 7266; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP36]]267; CHECK-NEXT: [[TMP38:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 7268; CHECK-NEXT: store i8 [[TMP38]], ptr [[TMP37]], align 1269; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE14]]270; CHECK: [[PRED_STORE_CONTINUE14]]:271; CHECK-NEXT: [[TMP39:%.*]] = extractelement <16 x i1> [[TMP7]], i32 8272; CHECK-NEXT: br i1 [[TMP39]], label %[[PRED_STORE_IF15:.*]], label %[[PRED_STORE_CONTINUE16:.*]]273; CHECK: [[PRED_STORE_IF15]]:274; CHECK-NEXT: [[TMP40:%.*]] = add i32 [[IV]], 8275; CHECK-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP40]]276; CHECK-NEXT: [[TMP42:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 8277; CHECK-NEXT: store i8 [[TMP42]], ptr [[TMP41]], align 1278; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE16]]279; CHECK: [[PRED_STORE_CONTINUE16]]:280; CHECK-NEXT: [[TMP43:%.*]] = extractelement <16 x i1> [[TMP7]], i32 9281; CHECK-NEXT: br i1 [[TMP43]], label %[[PRED_STORE_IF17:.*]], label %[[PRED_STORE_CONTINUE18:.*]]282; CHECK: [[PRED_STORE_IF17]]:283; CHECK-NEXT: [[TMP44:%.*]] = add i32 [[IV]], 9284; CHECK-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP44]]285; CHECK-NEXT: [[TMP46:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 9286; CHECK-NEXT: store i8 [[TMP46]], ptr [[TMP45]], align 1287; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE18]]288; CHECK: [[PRED_STORE_CONTINUE18]]:289; CHECK-NEXT: [[TMP47:%.*]] = extractelement <16 x i1> [[TMP7]], i32 10290; CHECK-NEXT: br i1 [[TMP47]], label %[[PRED_STORE_IF19:.*]], label %[[PRED_STORE_CONTINUE20:.*]]291; CHECK: [[PRED_STORE_IF19]]:292; CHECK-NEXT: [[TMP48:%.*]] = add i32 [[IV]], 10293; CHECK-NEXT: [[TMP49:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP48]]294; CHECK-NEXT: [[TMP50:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 10295; CHECK-NEXT: store i8 [[TMP50]], ptr [[TMP49]], align 1296; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE20]]297; CHECK: [[PRED_STORE_CONTINUE20]]:298; CHECK-NEXT: [[TMP51:%.*]] = extractelement <16 x i1> [[TMP7]], i32 11299; CHECK-NEXT: br i1 [[TMP51]], label %[[PRED_STORE_IF21:.*]], label %[[PRED_STORE_CONTINUE22:.*]]300; CHECK: [[PRED_STORE_IF21]]:301; CHECK-NEXT: [[TMP52:%.*]] = add i32 [[IV]], 11302; CHECK-NEXT: [[TMP53:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP52]]303; CHECK-NEXT: [[TMP54:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 11304; CHECK-NEXT: store i8 [[TMP54]], ptr [[TMP53]], align 1305; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE22]]306; CHECK: [[PRED_STORE_CONTINUE22]]:307; CHECK-NEXT: [[TMP55:%.*]] = extractelement <16 x i1> [[TMP7]], i32 12308; CHECK-NEXT: br i1 [[TMP55]], label %[[PRED_STORE_IF23:.*]], label %[[PRED_STORE_CONTINUE24:.*]]309; CHECK: [[PRED_STORE_IF23]]:310; CHECK-NEXT: [[TMP56:%.*]] = add i32 [[IV]], 12311; CHECK-NEXT: [[TMP57:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP56]]312; CHECK-NEXT: [[TMP58:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 12313; CHECK-NEXT: store i8 [[TMP58]], ptr [[TMP57]], align 1314; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE24]]315; CHECK: [[PRED_STORE_CONTINUE24]]:316; CHECK-NEXT: [[TMP59:%.*]] = extractelement <16 x i1> [[TMP7]], i32 13317; CHECK-NEXT: br i1 [[TMP59]], label %[[PRED_STORE_IF25:.*]], label %[[PRED_STORE_CONTINUE26:.*]]318; CHECK: [[PRED_STORE_IF25]]:319; CHECK-NEXT: [[TMP60:%.*]] = add i32 [[IV]], 13320; CHECK-NEXT: [[TMP61:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP60]]321; CHECK-NEXT: [[TMP62:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 13322; CHECK-NEXT: store i8 [[TMP62]], ptr [[TMP61]], align 1323; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE26]]324; CHECK: [[PRED_STORE_CONTINUE26]]:325; CHECK-NEXT: [[TMP63:%.*]] = extractelement <16 x i1> [[TMP7]], i32 14326; CHECK-NEXT: br i1 [[TMP63]], label %[[PRED_STORE_IF27:.*]], label %[[PRED_STORE_CONTINUE28:.*]]327; CHECK: [[PRED_STORE_IF27]]:328; CHECK-NEXT: [[TMP64:%.*]] = add i32 [[IV]], 14329; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP64]]330; CHECK-NEXT: [[TMP66:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 14331; CHECK-NEXT: store i8 [[TMP66]], ptr [[TMP65]], align 1332; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE28]]333; CHECK: [[PRED_STORE_CONTINUE28]]:334; CHECK-NEXT: [[TMP67:%.*]] = extractelement <16 x i1> [[TMP7]], i32 15335; CHECK-NEXT: br i1 [[TMP67]], label %[[PRED_STORE_IF29:.*]], label %[[PRED_STORE_CONTINUE30]]336; CHECK: [[PRED_STORE_IF29]]:337; CHECK-NEXT: [[TMP68:%.*]] = add i32 [[IV]], 15338; CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP68]]339; CHECK-NEXT: [[TMP70:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 15340; CHECK-NEXT: store i8 [[TMP70]], ptr [[TMP69]], align 1341; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE30]]342; CHECK: [[PRED_STORE_CONTINUE30]]:343; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[IV]], 16344; CHECK-NEXT: [[TMP71:%.*]] = icmp eq i32 [[INDEX_NEXT]], 96345; CHECK-NEXT: br i1 [[TMP71]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]346; CHECK: [[MIDDLE_BLOCK]]:347; CHECK-NEXT: br label %[[SCALAR_PH:.*]]348; CHECK: [[SCALAR_PH]]:349; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]350; CHECK: [[LOOP_HEADER]]:351; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ 96, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]352; CHECK-NEXT: [[GEP_SRC1:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i32 [[IV1]]353; CHECK-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC1]], align 1354; CHECK-NEXT: [[C_1:%.*]] = icmp eq i8 [[L]], 0355; CHECK-NEXT: br i1 [[C_1]], label %[[THEN:.*]], label %[[ELSE:.*]]356; CHECK: [[ELSE]]:357; CHECK-NEXT: br i1 [[C_0]], label %[[LOOP_LATCH]], label %[[THEN]]358; CHECK: [[THEN]]:359; CHECK-NEXT: [[P:%.*]] = phi i8 [ 1, %[[LOOP_HEADER]] ], [ 0, %[[ELSE]] ]360; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[IV1]]361; CHECK-NEXT: store i8 [[P]], ptr [[GEP_DST]], align 1362; CHECK-NEXT: br label %[[LOOP_LATCH]]363; CHECK: [[LOOP_LATCH]]:364; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV1]], 1365; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 100366; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP5:![0-9]+]]367; CHECK: [[EXIT]]:368; CHECK-NEXT: ret void369;370entry:371 br label %loop.header372 373loop.header:374 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]375 %gep.src = getelementptr inbounds i8, ptr %src, i32 %iv376 %l = load i8, ptr %gep.src, align 1377 %c.1 = icmp eq i8 %l, 0378 br i1 %c.1, label %then, label %else379 380else:381 br i1 %c.0, label %loop.latch, label %then382 383then:384 %p = phi i8 [ 1, %loop.header ], [ 0, %else ]385 %gep.dst = getelementptr inbounds i8, ptr %dst, i32 %iv386 store i8 %p, ptr %gep.dst, align 1387 br label %loop.latch388 389loop.latch:390 %iv.next = add i32 %iv, 1391 %ec = icmp eq i32 %iv.next, 100392 br i1 %ec, label %exit, label %loop.header393 394exit:395 ret void396}397 398define void @test_blend_feeding_replicated_store_3(ptr noalias %src.1, ptr noalias %src.2, ptr noalias %dst, i32 %x, i64 %N, i1 %c.2) {399; CHECK-LABEL: define void @test_blend_feeding_replicated_store_3(400; CHECK-SAME: ptr noalias [[SRC_1:%.*]], ptr noalias [[SRC_2:%.*]], ptr noalias [[DST:%.*]], i32 [[X:%.*]], i64 [[N:%.*]], i1 [[C_2:%.*]]) {401; CHECK-NEXT: [[ENTRY:.*]]:402; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]403; CHECK: [[LOOP_HEADER]]:404; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 0, %[[ENTRY]] ]405; CHECK-NEXT: [[L_3:%.*]] = load i8, ptr [[SRC_1]], align 1406; CHECK-NEXT: [[EXT:%.*]] = zext i8 [[L_3]] to i32407; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X]], [[EXT]]408; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[MUL]], [[EXT]]409; CHECK-NEXT: [[L_2:%.*]] = load i8, ptr [[SRC_2]], align 1410; CHECK-NEXT: [[C_1:%.*]] = icmp eq i8 [[L_2]], 0411; CHECK-NEXT: br i1 [[C_1]], label %[[THEN:.*]], label %[[ELSE_1:.*]]412; CHECK: [[ELSE_1]]:413; CHECK-NEXT: br i1 [[C_2]], label %[[LOOP_LATCH]], label %[[ELSE_2:.*]]414; CHECK: [[ELSE_2]]:415; CHECK-NEXT: [[TRUNC_DIV:%.*]] = trunc i32 [[DIV]] to i8416; CHECK-NEXT: br label %[[THEN]]417; CHECK: [[THEN]]:418; CHECK-NEXT: [[P:%.*]] = phi i8 [ 0, %[[LOOP_HEADER]] ], [ [[TRUNC_DIV]], %[[ELSE_2]] ]419; CHECK-NEXT: store i8 [[P]], ptr [[DST]], align 1420; CHECK-NEXT: br label %[[LOOP_LATCH]]421; CHECK: [[LOOP_LATCH]]:422; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1423; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]424; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]425; CHECK: [[EXIT]]:426; CHECK-NEXT: ret void427;428entry:429 br label %loop.header430 431loop.header:432 %iv = phi i64 [ %iv.next, %loop.latch ], [ 0, %entry ]433 %l.1 = load i8, ptr %src.1, align 1434 %ext = zext i8 %l.1 to i32435 %mul = mul i32 %x, %ext436 %div = sdiv i32 %mul, %ext437 %l.2 = load i8, ptr %src.2, align 1438 %c.1 = icmp eq i8 %l.2, 0439 br i1 %c.1, label %then, label %else.1440 441else.1:442 br i1 %c.2, label %loop.latch, label %else.2443 444else.2:445 %trunc.div = trunc i32 %div to i8446 br label %then447 448then:449 %p = phi i8 [ 0, %loop.header ], [ %trunc.div, %else.2 ]450 store i8 %p, ptr %dst, align 1451 br label %loop.latch452 453loop.latch:454 %iv.next = add i64 %iv, 1455 %ec = icmp eq i64 %iv, %N456 br i1 %ec, label %exit, label %loop.header457 458exit:459 ret void460}461;.462; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}463; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}464; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}465; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}466; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}467; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}468;.469