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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "scalar.ph\:" --version 52; RUN: opt -p loop-vectorize -S %s | FileCheck --check-prefixes=COMMON,DEFAULT %s3; RUN: opt -p loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -S %s | FileCheck --check-prefixes=COMMON,PRED %s4 5target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"6target triple = "arm64-apple-macosx14.0.0"7 8define void @invar_cond_gep_store(ptr %dst, i32 %0) {9; COMMON-LABEL: define void @invar_cond_gep_store(10; COMMON-SAME: ptr [[DST:%.*]], i32 [[TMP0:%.*]]) {11; COMMON-NEXT: [[ENTRY:.*]]:12; COMMON-NEXT: br label %[[LOOP_HEADER:.*]]13; COMMON: [[LOOP_HEADER]]:14; COMMON-NEXT: [[IV:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]15; COMMON-NEXT: [[IV_NEXT]] = add i64 [[IV]], 116; COMMON-NEXT: [[CMP9:%.*]] = icmp eq i32 [[TMP0]], 017; COMMON-NEXT: br i1 [[CMP9]], label %[[THEN:.*]], label %[[LOOP_LATCH]]18; COMMON: [[THEN]]:19; COMMON-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_NEXT]]20; COMMON-NEXT: store i32 1, ptr [[GEP]], align 421; COMMON-NEXT: br label %[[LOOP_LATCH]]22; COMMON: [[LOOP_LATCH]]:23; COMMON-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 10024; COMMON-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]25; COMMON: [[EXIT]]:26; COMMON-NEXT: ret void27;28entry:29 br label %loop.header30 31loop.header:32 %iv = phi i64 [ 1, %entry ], [ %iv.next, %loop.latch ]33 %iv.next = add i64 %iv, 134 %cmp9 = icmp eq i32 %0, 035 br i1 %cmp9, label %then, label %loop.latch36 37then:38 %gep = getelementptr i32, ptr %dst, i64 %iv.next39 store i32 1, ptr %gep, align 440 br label %loop.latch41 42loop.latch:43 %ec = icmp eq i64 %iv, 10044 br i1 %ec, label %exit, label %loop.header45 46exit:47 ret void48}49 50declare double @llvm.fabs.f64(double) #051 52define void @loop_dependent_cond(ptr %src, ptr noalias %dst, i64 %N) {53; DEFAULT-LABEL: define void @loop_dependent_cond(54; DEFAULT-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {55; DEFAULT-NEXT: [[ENTRY:.*:]]56; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 157; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 458; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]59; DEFAULT: [[VECTOR_PH]]:60; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 461; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]62; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]63; DEFAULT: [[VECTOR_BODY]]:64; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE7:.*]] ]65; DEFAULT-NEXT: [[TMP3:%.*]] = getelementptr double, ptr [[SRC]], i64 [[INDEX]]66; DEFAULT-NEXT: [[TMP6:%.*]] = getelementptr double, ptr [[TMP3]], i64 267; DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, ptr [[TMP3]], align 868; DEFAULT-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x double>, ptr [[TMP6]], align 869; DEFAULT-NEXT: [[TMP7:%.*]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> [[WIDE_LOAD]])70; DEFAULT-NEXT: [[TMP8:%.*]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> [[WIDE_LOAD1]])71; DEFAULT-NEXT: [[TMP9:%.*]] = fcmp ogt <2 x double> [[TMP7]], splat (double 1.000000e+00)72; DEFAULT-NEXT: [[TMP10:%.*]] = fcmp ogt <2 x double> [[TMP8]], splat (double 1.000000e+00)73; DEFAULT-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP9]], i32 074; DEFAULT-NEXT: br i1 [[TMP11]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]75; DEFAULT: [[PRED_STORE_IF]]:76; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 477; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE]]78; DEFAULT: [[PRED_STORE_CONTINUE]]:79; DEFAULT-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP9]], i32 180; DEFAULT-NEXT: br i1 [[TMP12]], label %[[PRED_STORE_IF2:.*]], label %[[PRED_STORE_CONTINUE3:.*]]81; DEFAULT: [[PRED_STORE_IF2]]:82; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 483; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE3]]84; DEFAULT: [[PRED_STORE_CONTINUE3]]:85; DEFAULT-NEXT: [[TMP13:%.*]] = extractelement <2 x i1> [[TMP10]], i32 086; DEFAULT-NEXT: br i1 [[TMP13]], label %[[PRED_STORE_IF4:.*]], label %[[PRED_STORE_CONTINUE5:.*]]87; DEFAULT: [[PRED_STORE_IF4]]:88; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 489; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE5]]90; DEFAULT: [[PRED_STORE_CONTINUE5]]:91; DEFAULT-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP10]], i32 192; DEFAULT-NEXT: br i1 [[TMP14]], label %[[PRED_STORE_IF6:.*]], label %[[PRED_STORE_CONTINUE7]]93; DEFAULT: [[PRED_STORE_IF6]]:94; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 495; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE7]]96; DEFAULT: [[PRED_STORE_CONTINUE7]]:97; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 498; DEFAULT-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]99; DEFAULT-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]100; DEFAULT: [[MIDDLE_BLOCK]]:101; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]102; DEFAULT-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]103; DEFAULT: [[SCALAR_PH]]:104;105; PRED-LABEL: define void @loop_dependent_cond(106; PRED-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {107; PRED-NEXT: [[ENTRY:.*]]:108; PRED-NEXT: br label %[[LOOP_HEADER:.*]]109; PRED: [[LOOP_HEADER]]:110; PRED-NEXT: [[IV175:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT176:%.*]], %[[LOOP_LATCH:.*]] ]111; PRED-NEXT: [[ARRAYIDX114:%.*]] = getelementptr double, ptr [[SRC]], i64 [[IV175]]112; PRED-NEXT: [[TMP0:%.*]] = load double, ptr [[ARRAYIDX114]], align 8113; PRED-NEXT: [[TMP1:%.*]] = tail call double @llvm.fabs.f64(double [[TMP0]])114; PRED-NEXT: [[CMP115:%.*]] = fcmp ogt double [[TMP1]], 1.000000e+00115; PRED-NEXT: br i1 [[CMP115]], label %[[THEN:.*]], label %[[LOOP_LATCH]]116; PRED: [[THEN]]:117; PRED-NEXT: store i32 0, ptr [[DST]], align 4118; PRED-NEXT: br label %[[LOOP_LATCH]]119; PRED: [[LOOP_LATCH]]:120; PRED-NEXT: [[IV_NEXT176]] = add i64 [[IV175]], 1121; PRED-NEXT: [[EXITCOND180_NOT:%.*]] = icmp eq i64 [[IV175]], [[N]]122; PRED-NEXT: br i1 [[EXITCOND180_NOT]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]123; PRED: [[EXIT]]:124; PRED-NEXT: ret void125;126entry:127 br label %loop.header128 129loop.header:130 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]131 %gep = getelementptr double, ptr %src, i64 %iv132 %l = load double, ptr %gep, align 8133 %abs = tail call double @llvm.fabs.f64(double %l)134 %cmp = fcmp ogt double %abs, 1.000000e+00135 br i1 %cmp, label %then, label %loop.latch136 137then:138 store i32 0, ptr %dst, align 4139 br label %loop.latch140 141loop.latch:142 %iv.next = add i64 %iv, 1143 %ec = icmp eq i64 %iv, %N144 br i1 %ec, label %exit, label %loop.header145 146exit:147 ret void148}149 150define void @invar_cond_chain_1(ptr %I, ptr noalias %src, i1 %c) {151; COMMON-LABEL: define void @invar_cond_chain_1(152; COMMON-SAME: ptr [[I:%.*]], ptr noalias [[SRC:%.*]], i1 [[C:%.*]]) {153; COMMON-NEXT: [[ENTRY:.*]]:154; COMMON-NEXT: br label %[[LOOP_HEADER:.*]]155; COMMON: [[LOOP_HEADER]]:156; COMMON-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[SRC]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]157; COMMON-NEXT: [[L:%.*]] = load i32, ptr [[PTR_IV]], align 4158; COMMON-NEXT: br i1 true, label %[[ELSE_1:.*]], label %[[IF:.*]]159; COMMON: [[IF]]:160; COMMON-NEXT: br label %[[SPLIT:.*]]161; COMMON: [[ELSE_1]]:162; COMMON-NEXT: br i1 [[C]], label %[[ELSE_2:.*]], label %[[LOOP_LATCH]]163; COMMON: [[ELSE_2]]:164; COMMON-NEXT: br label %[[SPLIT]]165; COMMON: [[SPLIT]]:166; COMMON-NEXT: store i32 [[L]], ptr [[I]], align 4167; COMMON-NEXT: br label %[[LOOP_LATCH]]168; COMMON: [[LOOP_LATCH]]:169; COMMON-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i8, ptr [[PTR_IV]], i64 4170; COMMON-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV]], [[I]]171; COMMON-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]172; COMMON: [[EXIT]]:173; COMMON-NEXT: ret void174;175entry:176 br label %loop.header177 178loop.header:179 %ptr.iv = phi ptr [ %src, %entry ], [ %ptr.iv.next, %loop.latch ]180 %l = load i32, ptr %ptr.iv, align 4181 br i1 true, label %else.1, label %if182 183if:184 br label %split185 186else.1:187 br i1 %c, label %else.2, label %loop.latch188 189else.2:190 br label %split191 192split:193 store i32 %l, ptr %I, align 4194 br label %loop.latch195 196loop.latch:197 %ptr.iv.next = getelementptr inbounds i8, ptr %ptr.iv, i64 4198 %ec = icmp eq ptr %ptr.iv, %I199 br i1 %ec, label %exit, label %loop.header200 201exit:202 ret void203}204 205define void @invar_cond_chain_2(ptr %I, ptr noalias %src, ptr noalias %dst, i32 %a) {206; COMMON-LABEL: define void @invar_cond_chain_2(207; COMMON-SAME: ptr [[I:%.*]], ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i32 [[A:%.*]]) {208; COMMON-NEXT: [[ENTRY:.*]]:209; COMMON-NEXT: br label %[[LOOP_HEADER:.*]]210; COMMON: [[LOOP_HEADER]]:211; COMMON-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[SRC]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]212; COMMON-NEXT: [[CMP315_NOT:%.*]] = icmp sgt i32 [[A]], 0213; COMMON-NEXT: br i1 [[CMP315_NOT]], label %[[LOOP_LATCH]], label %[[IF:.*]]214; COMMON: [[IF]]:215; COMMON-NEXT: br label %[[ELSE:.*]]216; COMMON: [[ELSE]]:217; COMMON-NEXT: store i32 0, ptr [[DST]], align 4218; COMMON-NEXT: br label %[[LOOP_LATCH]]219; COMMON: [[LOOP_LATCH]]:220; COMMON-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i8, ptr [[PTR_IV]], i64 4221; COMMON-NEXT: [[CMP311_NOT:%.*]] = icmp eq ptr [[PTR_IV]], [[I]]222; COMMON-NEXT: br i1 [[CMP311_NOT]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]223; COMMON: [[EXIT]]:224; COMMON-NEXT: ret void225;226entry:227 br label %loop.header228 229loop.header:230 %ptr.iv = phi ptr [ %src, %entry ], [ %ptr.iv.next, %loop.latch ]231 %cmp315.not = icmp sgt i32 %a, 0232 br i1 %cmp315.not, label %loop.latch, label %if233 234if:235 br label %else236 237else:238 store i32 0, ptr %dst, align 4239 br label %loop.latch240 241loop.latch:242 %ptr.iv.next = getelementptr inbounds i8, ptr %ptr.iv, i64 4243 %cmp311.not = icmp eq ptr %ptr.iv, %I244 br i1 %cmp311.not, label %exit, label %loop.header245 246exit:247 ret void248}249 250define void @latch_branch_cost(ptr %dst) {251; DEFAULT-LABEL: define void @latch_branch_cost(252; DEFAULT-SAME: ptr [[DST:%.*]]) {253; DEFAULT-NEXT: [[ITER_CHECK:.*:]]254; DEFAULT-NEXT: br i1 false, label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]255; DEFAULT: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:256; DEFAULT-NEXT: br i1 false, label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]257; DEFAULT: [[VECTOR_PH]]:258; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]259; DEFAULT: [[VECTOR_BODY]]:260; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]261; DEFAULT-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX]]262; DEFAULT-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP2]], i64 16263; DEFAULT-NEXT: store <16 x i8> zeroinitializer, ptr [[TMP2]], align 1264; DEFAULT-NEXT: store <16 x i8> zeroinitializer, ptr [[TMP5]], align 1265; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32266; DEFAULT-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96267; DEFAULT-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]268; DEFAULT: [[MIDDLE_BLOCK]]:269; DEFAULT-NEXT: br i1 false, [[EXIT:label %.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]270; DEFAULT: [[VEC_EPILOG_ITER_CHECK]]:271; DEFAULT-NEXT: br i1 false, label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF5:![0-9]+]]272; DEFAULT: [[VEC_EPILOG_PH]]:273; DEFAULT-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ 96, %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]274; DEFAULT-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]]275; DEFAULT: [[VEC_EPILOG_VECTOR_BODY]]:276; DEFAULT-NEXT: [[INDEX1:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT2:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]277; DEFAULT-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX1]]278; DEFAULT-NEXT: store <4 x i8> zeroinitializer, ptr [[TMP8]], align 1279; DEFAULT-NEXT: [[INDEX_NEXT2]] = add nuw i64 [[INDEX1]], 4280; DEFAULT-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT2]], 100281; DEFAULT-NEXT: br i1 [[TMP10]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]282; DEFAULT: [[VEC_EPILOG_MIDDLE_BLOCK]]:283; DEFAULT-NEXT: br i1 true, [[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]]284; DEFAULT: [[VEC_EPILOG_SCALAR_PH]]:285;286; PRED-LABEL: define void @latch_branch_cost(287; PRED-SAME: ptr [[DST:%.*]]) {288; PRED-NEXT: [[ENTRY:.*:]]289; PRED-NEXT: br label %[[VECTOR_PH:.*]]290; PRED: [[VECTOR_PH]]:291; PRED-NEXT: br label %[[VECTOR_BODY:.*]]292; PRED: [[VECTOR_BODY]]:293; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE14:.*]] ]294; PRED-NEXT: [[VEC_IND:%.*]] = phi <8 x i8> [ <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE14]] ]295; PRED-NEXT: [[TMP0:%.*]] = icmp ule <8 x i8> [[VEC_IND]], splat (i8 99)296; PRED-NEXT: [[TMP1:%.*]] = extractelement <8 x i1> [[TMP0]], i32 0297; PRED-NEXT: br i1 [[TMP1]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]298; PRED: [[PRED_STORE_IF]]:299; PRED-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 0300; PRED-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP2]]301; PRED-NEXT: store i8 0, ptr [[TMP3]], align 1302; PRED-NEXT: br label %[[PRED_STORE_CONTINUE]]303; PRED: [[PRED_STORE_CONTINUE]]:304; PRED-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[TMP0]], i32 1305; PRED-NEXT: br i1 [[TMP4]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]306; PRED: [[PRED_STORE_IF1]]:307; PRED-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 1308; PRED-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP5]]309; PRED-NEXT: store i8 0, ptr [[TMP6]], align 1310; PRED-NEXT: br label %[[PRED_STORE_CONTINUE2]]311; PRED: [[PRED_STORE_CONTINUE2]]:312; PRED-NEXT: [[TMP7:%.*]] = extractelement <8 x i1> [[TMP0]], i32 2313; PRED-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]314; PRED: [[PRED_STORE_IF3]]:315; PRED-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 2316; PRED-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP8]]317; PRED-NEXT: store i8 0, ptr [[TMP9]], align 1318; PRED-NEXT: br label %[[PRED_STORE_CONTINUE4]]319; PRED: [[PRED_STORE_CONTINUE4]]:320; PRED-NEXT: [[TMP10:%.*]] = extractelement <8 x i1> [[TMP0]], i32 3321; PRED-NEXT: br i1 [[TMP10]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]322; PRED: [[PRED_STORE_IF5]]:323; PRED-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 3324; PRED-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP11]]325; PRED-NEXT: store i8 0, ptr [[TMP12]], align 1326; PRED-NEXT: br label %[[PRED_STORE_CONTINUE6]]327; PRED: [[PRED_STORE_CONTINUE6]]:328; PRED-NEXT: [[TMP13:%.*]] = extractelement <8 x i1> [[TMP0]], i32 4329; PRED-NEXT: br i1 [[TMP13]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]330; PRED: [[PRED_STORE_IF7]]:331; PRED-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 4332; PRED-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP14]]333; PRED-NEXT: store i8 0, ptr [[TMP15]], align 1334; PRED-NEXT: br label %[[PRED_STORE_CONTINUE8]]335; PRED: [[PRED_STORE_CONTINUE8]]:336; PRED-NEXT: [[TMP16:%.*]] = extractelement <8 x i1> [[TMP0]], i32 5337; PRED-NEXT: br i1 [[TMP16]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]338; PRED: [[PRED_STORE_IF9]]:339; PRED-NEXT: [[TMP17:%.*]] = add i64 [[INDEX]], 5340; PRED-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP17]]341; PRED-NEXT: store i8 0, ptr [[TMP18]], align 1342; PRED-NEXT: br label %[[PRED_STORE_CONTINUE10]]343; PRED: [[PRED_STORE_CONTINUE10]]:344; PRED-NEXT: [[TMP19:%.*]] = extractelement <8 x i1> [[TMP0]], i32 6345; PRED-NEXT: br i1 [[TMP19]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]346; PRED: [[PRED_STORE_IF11]]:347; PRED-NEXT: [[TMP20:%.*]] = add i64 [[INDEX]], 6348; PRED-NEXT: [[TMP21:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP20]]349; PRED-NEXT: store i8 0, ptr [[TMP21]], align 1350; PRED-NEXT: br label %[[PRED_STORE_CONTINUE12]]351; PRED: [[PRED_STORE_CONTINUE12]]:352; PRED-NEXT: [[TMP22:%.*]] = extractelement <8 x i1> [[TMP0]], i32 7353; PRED-NEXT: br i1 [[TMP22]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14]]354; PRED: [[PRED_STORE_IF13]]:355; PRED-NEXT: [[TMP23:%.*]] = add i64 [[INDEX]], 7356; PRED-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP23]]357; PRED-NEXT: store i8 0, ptr [[TMP24]], align 1358; PRED-NEXT: br label %[[PRED_STORE_CONTINUE14]]359; PRED: [[PRED_STORE_CONTINUE14]]:360; PRED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8361; PRED-NEXT: [[VEC_IND_NEXT]] = add <8 x i8> [[VEC_IND]], splat (i8 8)362; PRED-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], 104363; PRED-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]364; PRED: [[MIDDLE_BLOCK]]:365; PRED-NEXT: br label %[[EXIT:.*]]366; PRED: [[EXIT]]:367; PRED-NEXT: ret void368;369entry:370 br label %loop371 372loop:373 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]374 %gep = getelementptr i8, ptr %dst, i64 %iv375 store i8 0, ptr %gep, align 1376 %iv.next = add i64 %iv, 1377 %ec = icmp eq i64 %iv.next, 100378 br i1 %ec, label %exit, label %loop379 380exit:381 ret void382}383 384define i32 @header_mask_and_invariant_compare(ptr %A, ptr %B, ptr %C, ptr %D, ptr %E, i64 %N) "target-features"="+sve" {385; DEFAULT-LABEL: define i32 @header_mask_and_invariant_compare(386; DEFAULT-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], ptr [[E:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {387; DEFAULT-NEXT: [[ENTRY:.*:]]388; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1389; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 28390; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]391; DEFAULT: [[VECTOR_MEMCHECK]]:392; DEFAULT-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[E]], i64 4393; DEFAULT-NEXT: [[TMP1:%.*]] = shl i64 [[N]], 2394; DEFAULT-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 4395; DEFAULT-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[D]], i64 [[TMP2]]396; DEFAULT-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[A]], i64 4397; DEFAULT-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[B]], i64 4398; DEFAULT-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[C]], i64 4399; DEFAULT-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[E]], [[SCEVGEP1]]400; DEFAULT-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[D]], [[SCEVGEP]]401; DEFAULT-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]402; DEFAULT-NEXT: [[BOUND05:%.*]] = icmp ult ptr [[E]], [[SCEVGEP2]]403; DEFAULT-NEXT: [[BOUND16:%.*]] = icmp ult ptr [[A]], [[SCEVGEP]]404; DEFAULT-NEXT: [[FOUND_CONFLICT7:%.*]] = and i1 [[BOUND05]], [[BOUND16]]405; DEFAULT-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT7]]406; DEFAULT-NEXT: [[BOUND08:%.*]] = icmp ult ptr [[E]], [[SCEVGEP3]]407; DEFAULT-NEXT: [[BOUND19:%.*]] = icmp ult ptr [[B]], [[SCEVGEP]]408; DEFAULT-NEXT: [[FOUND_CONFLICT10:%.*]] = and i1 [[BOUND08]], [[BOUND19]]409; DEFAULT-NEXT: [[CONFLICT_RDX11:%.*]] = or i1 [[CONFLICT_RDX]], [[FOUND_CONFLICT10]]410; DEFAULT-NEXT: [[BOUND012:%.*]] = icmp ult ptr [[E]], [[SCEVGEP4]]411; DEFAULT-NEXT: [[BOUND113:%.*]] = icmp ult ptr [[C]], [[SCEVGEP]]412; DEFAULT-NEXT: [[FOUND_CONFLICT14:%.*]] = and i1 [[BOUND012]], [[BOUND113]]413; DEFAULT-NEXT: [[CONFLICT_RDX15:%.*]] = or i1 [[CONFLICT_RDX11]], [[FOUND_CONFLICT14]]414; DEFAULT-NEXT: [[BOUND016:%.*]] = icmp ult ptr [[D]], [[SCEVGEP2]]415; DEFAULT-NEXT: [[BOUND117:%.*]] = icmp ult ptr [[A]], [[SCEVGEP1]]416; DEFAULT-NEXT: [[FOUND_CONFLICT18:%.*]] = and i1 [[BOUND016]], [[BOUND117]]417; DEFAULT-NEXT: [[CONFLICT_RDX19:%.*]] = or i1 [[CONFLICT_RDX15]], [[FOUND_CONFLICT18]]418; DEFAULT-NEXT: [[BOUND020:%.*]] = icmp ult ptr [[D]], [[SCEVGEP3]]419; DEFAULT-NEXT: [[BOUND121:%.*]] = icmp ult ptr [[B]], [[SCEVGEP1]]420; DEFAULT-NEXT: [[FOUND_CONFLICT22:%.*]] = and i1 [[BOUND020]], [[BOUND121]]421; DEFAULT-NEXT: [[CONFLICT_RDX23:%.*]] = or i1 [[CONFLICT_RDX19]], [[FOUND_CONFLICT22]]422; DEFAULT-NEXT: [[BOUND024:%.*]] = icmp ult ptr [[D]], [[SCEVGEP4]]423; DEFAULT-NEXT: [[BOUND125:%.*]] = icmp ult ptr [[C]], [[SCEVGEP1]]424; DEFAULT-NEXT: [[FOUND_CONFLICT26:%.*]] = and i1 [[BOUND024]], [[BOUND125]]425; DEFAULT-NEXT: [[CONFLICT_RDX27:%.*]] = or i1 [[CONFLICT_RDX23]], [[FOUND_CONFLICT26]]426; DEFAULT-NEXT: br i1 [[CONFLICT_RDX27]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]427; DEFAULT: [[VECTOR_PH]]:428; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 4429; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]430; DEFAULT-NEXT: [[TMP6:%.*]] = load i32, ptr [[C]], align 4, !alias.scope [[META8:![0-9]+]]431; DEFAULT-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4, !alias.scope [[META11:![0-9]+]]432; DEFAULT-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4, !alias.scope [[META13:![0-9]+]]433; DEFAULT-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], [[TMP3]]434; DEFAULT-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], [[TMP5]]435; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[TMP7]], i64 0436; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer437; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]438; DEFAULT: [[VECTOR_BODY]]:439; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE33:.*]] ]440; DEFAULT-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[D]], i64 [[INDEX]]441; DEFAULT-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]442; DEFAULT: [[PRED_STORE_IF]]:443; DEFAULT-NEXT: store i32 [[TMP5]], ptr [[E]], align 4, !alias.scope [[META15:![0-9]+]], !noalias [[META17:![0-9]+]]444; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE]]445; DEFAULT: [[PRED_STORE_CONTINUE]]:446; DEFAULT-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF28:.*]], label %[[PRED_STORE_CONTINUE29:.*]]447; DEFAULT: [[PRED_STORE_IF28]]:448; DEFAULT-NEXT: store i32 [[TMP5]], ptr [[E]], align 4, !alias.scope [[META15]], !noalias [[META17]]449; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE29]]450; DEFAULT: [[PRED_STORE_CONTINUE29]]:451; DEFAULT-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF30:.*]], label %[[PRED_STORE_CONTINUE31:.*]]452; DEFAULT: [[PRED_STORE_IF30]]:453; DEFAULT-NEXT: store i32 [[TMP5]], ptr [[E]], align 4, !alias.scope [[META15]], !noalias [[META17]]454; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE31]]455; DEFAULT: [[PRED_STORE_CONTINUE31]]:456; DEFAULT-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF32:.*]], label %[[PRED_STORE_CONTINUE33]]457; DEFAULT: [[PRED_STORE_IF32]]:458; DEFAULT-NEXT: store i32 [[TMP5]], ptr [[E]], align 4, !alias.scope [[META15]], !noalias [[META17]]459; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE33]]460; DEFAULT: [[PRED_STORE_CONTINUE33]]:461; DEFAULT-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> zeroinitializer, ptr align 4 [[TMP16]], <4 x i1> [[BROADCAST_SPLAT]]), !alias.scope [[META19:![0-9]+]], !noalias [[META20:![0-9]+]]462; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4463; DEFAULT-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]464; DEFAULT-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]465; DEFAULT: [[MIDDLE_BLOCK]]:466; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]467; DEFAULT-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]468; DEFAULT: [[SCALAR_PH]]:469;470; PRED-LABEL: define i32 @header_mask_and_invariant_compare(471; PRED-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], ptr [[E:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {472; PRED-NEXT: [[ENTRY:.*]]:473; PRED-NEXT: br label %[[LOOP_HEADER:.*]]474; PRED: [[LOOP_HEADER]]:475; PRED-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]476; PRED-NEXT: [[L_A:%.*]] = load i32, ptr [[A]], align 4477; PRED-NEXT: [[L_B:%.*]] = load i32, ptr [[B]], align 4478; PRED-NEXT: [[OR:%.*]] = or i32 [[L_B]], [[L_A]]479; PRED-NEXT: [[L_C:%.*]] = load i32, ptr [[C]], align 4480; PRED-NEXT: [[C_0:%.*]] = icmp ugt i32 [[L_C]], [[OR]]481; PRED-NEXT: br i1 [[C_0]], label %[[IF_THEN:.*]], label %[[LOOP_LATCH]]482; PRED: [[IF_THEN]]:483; PRED-NEXT: [[GEP_D:%.*]] = getelementptr i32, ptr [[D]], i64 [[IV]]484; PRED-NEXT: store i32 [[OR]], ptr [[E]], align 4485; PRED-NEXT: store i32 0, ptr [[GEP_D]], align 4486; PRED-NEXT: br label %[[LOOP_LATCH]]487; PRED: [[LOOP_LATCH]]:488; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1489; PRED-NEXT: [[C_1:%.*]] = icmp eq i64 [[IV]], [[N]]490; PRED-NEXT: br i1 [[C_1]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]491; PRED: [[EXIT]]:492; PRED-NEXT: ret i32 0493;494entry:495 br label %loop.header496 497loop.header:498 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]499 %l.A = load i32, ptr %A, align 4500 %l.B = load i32, ptr %B, align 4501 %or = or i32 %l.B, %l.A502 %l.C = load i32, ptr %C, align 4503 %c.0 = icmp ugt i32 %l.C, %or504 br i1 %c.0, label %if.then, label %loop.latch505 506if.then:507 %gep.D = getelementptr i32, ptr %D, i64 %iv508 store i32 %or, ptr %E, align 4509 store i32 0, ptr %gep.D, align 4510 br label %loop.latch511 512loop.latch:513 %iv.next = add i64 %iv, 1514 %c.1 = icmp eq i64 %iv, %N515 br i1 %c.1, label %exit, label %loop.header516 517exit:518 ret i32 0519}520 521define void @multiple_exit_conditions(ptr %src, ptr noalias %dst) #1 {522; DEFAULT-LABEL: define void @multiple_exit_conditions(523; DEFAULT-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR2:[0-9]+]] {524; DEFAULT-NEXT: [[ENTRY:.*:]]525; DEFAULT-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()526; DEFAULT-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 4527; DEFAULT-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 257, [[TMP3]]528; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]529; DEFAULT: [[VECTOR_PH]]:530; DEFAULT-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()531; DEFAULT-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 16532; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 257, [[TMP5]]533; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 257, [[N_MOD_VF]]534; DEFAULT-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[N_VEC]], 8535; DEFAULT-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET_IDX]]536; DEFAULT-NEXT: [[TMP6:%.*]] = mul i64 [[N_VEC]], 2537; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]538; DEFAULT: [[VECTOR_BODY]]:539; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]540; DEFAULT-NEXT: [[OFFSET_IDX1:%.*]] = mul i64 [[INDEX]], 8541; DEFAULT-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET_IDX1]]542; DEFAULT-NEXT: [[TMP1:%.*]] = load i16, ptr [[SRC]], align 2543; DEFAULT-NEXT: [[TMP8:%.*]] = or i16 [[TMP1]], 1544; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i16> poison, i16 [[TMP8]], i64 0545; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i16> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer546; DEFAULT-NEXT: [[TMP9:%.*]] = uitofp <vscale x 4 x i16> [[BROADCAST_SPLAT]] to <vscale x 4 x double>547; DEFAULT-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()548; DEFAULT-NEXT: [[TMP11:%.*]] = shl nuw i64 [[TMP10]], 2549; DEFAULT-NEXT: [[TMP12:%.*]] = getelementptr double, ptr [[NEXT_GEP1]], i64 [[TMP11]]550; DEFAULT-NEXT: [[TMP13:%.*]] = call i64 @llvm.vscale.i64()551; DEFAULT-NEXT: [[TMP14:%.*]] = shl nuw i64 [[TMP13]], 3552; DEFAULT-NEXT: [[TMP15:%.*]] = getelementptr double, ptr [[NEXT_GEP1]], i64 [[TMP14]]553; DEFAULT-NEXT: [[TMP16:%.*]] = call i64 @llvm.vscale.i64()554; DEFAULT-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP16]], 12555; DEFAULT-NEXT: [[TMP18:%.*]] = getelementptr double, ptr [[NEXT_GEP1]], i64 [[TMP17]]556; DEFAULT-NEXT: store <vscale x 4 x double> [[TMP9]], ptr [[NEXT_GEP1]], align 8557; DEFAULT-NEXT: store <vscale x 4 x double> [[TMP9]], ptr [[TMP12]], align 8558; DEFAULT-NEXT: store <vscale x 4 x double> [[TMP9]], ptr [[TMP15]], align 8559; DEFAULT-NEXT: store <vscale x 4 x double> [[TMP9]], ptr [[TMP18]], align 8560; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]]561; DEFAULT-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]562; DEFAULT-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]]563; DEFAULT: [[MIDDLE_BLOCK]]:564; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 257, [[N_VEC]]565; DEFAULT-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]566; DEFAULT: [[SCALAR_PH]]:567;568; PRED-LABEL: define void @multiple_exit_conditions(569; PRED-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR2:[0-9]+]] {570; PRED-NEXT: [[ENTRY:.*:]]571; PRED-NEXT: br label %[[VECTOR_PH:.*]]572; PRED: [[VECTOR_PH]]:573; PRED-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()574; PRED-NEXT: [[TMP1:%.*]] = mul nuw i64 [[TMP0]], 4575; PRED-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()576; PRED-NEXT: [[TMP7:%.*]] = shl nuw i64 [[TMP6]], 2577; PRED-NEXT: [[TMP8:%.*]] = sub i64 257, [[TMP7]]578; PRED-NEXT: [[TMP9:%.*]] = icmp ugt i64 257, [[TMP7]]579; PRED-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i64 [[TMP8]], i64 0580; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 257)581; PRED-NEXT: br label %[[VECTOR_BODY:.*]]582; PRED: [[VECTOR_BODY]]:583; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]584; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]585; PRED-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8586; PRED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET_IDX]]587; PRED-NEXT: [[TMP12:%.*]] = load i16, ptr [[SRC]], align 2588; PRED-NEXT: [[TMP11:%.*]] = or i16 [[TMP12]], 1589; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i16> poison, i16 [[TMP11]], i64 0590; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i16> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer591; PRED-NEXT: [[TMP13:%.*]] = uitofp <vscale x 4 x i16> [[BROADCAST_SPLAT]] to <vscale x 4 x double>592; PRED-NEXT: call void @llvm.masked.store.nxv4f64.p0(<vscale x 4 x double> [[TMP13]], ptr align 8 [[NEXT_GEP]], <vscale x 4 x i1> [[ACTIVE_LANE_MASK]])593; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP1]]594; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX]], i64 [[TMP10]])595; PRED-NEXT: [[TMP15:%.*]] = extractelement <vscale x 4 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 0596; PRED-NEXT: [[TMP16:%.*]] = xor i1 [[TMP15]], true597; PRED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]598; PRED: [[MIDDLE_BLOCK]]:599; PRED-NEXT: br label %[[EXIT:.*]]600; PRED: [[EXIT]]:601; PRED-NEXT: ret void602;603entry:604 br label %loop605 606loop:607 %ptr.iv = phi ptr [ %dst, %entry ], [ %ptr.iv.next, %loop ]608 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]609 %l = load i16, ptr %src, align 2610 %o = or i16 %l, 1611 %conv = uitofp i16 %o to double612 store double %conv, ptr %ptr.iv, align 8613 %iv.next = add nsw i64 %iv, 2614 %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 8615 %iv.clamp = and i64 %iv, 4294967294616 %ec = icmp eq i64 %iv.clamp, 512617 br i1 %ec, label %exit, label %loop618 619exit:620 ret void621}622 623define void @low_trip_count_fold_tail_scalarized_store(ptr %dst) {624; COMMON-LABEL: define void @low_trip_count_fold_tail_scalarized_store(625; COMMON-SAME: ptr [[DST:%.*]]) {626; COMMON-NEXT: [[ENTRY:.*]]:627; COMMON-NEXT: br label %[[LOOP:.*]]628; COMMON: [[LOOP]]:629; COMMON-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]630; COMMON-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV]] to i8631; COMMON-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]]632; COMMON-NEXT: store i8 [[IV_TRUNC]], ptr [[GEP]], align 1633; COMMON-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1634; COMMON-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 7635; COMMON-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]636; COMMON: [[EXIT]]:637; COMMON-NEXT: ret void638;639entry:640 br label %loop641 642loop:643 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]644 %iv.trunc = trunc i64 %iv to i8645 %gep = getelementptr i8, ptr %dst, i64 %iv646 store i8 %iv.trunc, ptr %gep, align 1647 %iv.next = add i64 %iv, 1648 %ec = icmp eq i64 %iv.next, 7649 br i1 %ec, label %exit, label %loop650 651exit:652 ret void653}654 655define void @test_conditional_interleave_group (ptr noalias %src.1, ptr noalias %src.2, ptr noalias %src.3, ptr noalias %src.4, ptr noalias %dst, i64 %N) #2 {656; DEFAULT-LABEL: define void @test_conditional_interleave_group(657; DEFAULT-SAME: ptr noalias [[SRC_1:%.*]], ptr noalias [[SRC_2:%.*]], ptr noalias [[SRC_3:%.*]], ptr noalias [[SRC_4:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR3:[0-9]+]] {658; DEFAULT-NEXT: [[ENTRY:.*:]]659; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1660; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8661; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]662; DEFAULT: [[VECTOR_SCEVCHECK]]:663; DEFAULT-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[N]])664; DEFAULT-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0665; DEFAULT-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1666; DEFAULT-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[MUL_RESULT]]667; DEFAULT-NEXT: [[TMP3:%.*]] = icmp ult ptr [[TMP2]], [[DST]]668; DEFAULT-NEXT: [[TMP4:%.*]] = or i1 [[TMP3]], [[MUL_OVERFLOW]]669; DEFAULT-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 4670; DEFAULT-NEXT: [[MUL1:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[N]])671; DEFAULT-NEXT: [[MUL_RESULT2:%.*]] = extractvalue { i64, i1 } [[MUL1]], 0672; DEFAULT-NEXT: [[MUL_OVERFLOW3:%.*]] = extractvalue { i64, i1 } [[MUL1]], 1673; DEFAULT-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[MUL_RESULT2]]674; DEFAULT-NEXT: [[TMP7:%.*]] = icmp ult ptr [[TMP6]], [[SCEVGEP]]675; DEFAULT-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW3]]676; DEFAULT-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[DST]], i64 8677; DEFAULT-NEXT: [[MUL5:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[N]])678; DEFAULT-NEXT: [[MUL_RESULT6:%.*]] = extractvalue { i64, i1 } [[MUL5]], 0679; DEFAULT-NEXT: [[MUL_OVERFLOW7:%.*]] = extractvalue { i64, i1 } [[MUL5]], 1680; DEFAULT-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[SCEVGEP4]], i64 [[MUL_RESULT6]]681; DEFAULT-NEXT: [[TMP11:%.*]] = icmp ult ptr [[TMP10]], [[SCEVGEP4]]682; DEFAULT-NEXT: [[TMP12:%.*]] = or i1 [[TMP11]], [[MUL_OVERFLOW7]]683; DEFAULT-NEXT: [[TMP13:%.*]] = or i1 [[TMP4]], [[TMP8]]684; DEFAULT-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[TMP12]]685; DEFAULT-NEXT: br i1 [[TMP14]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]686; DEFAULT: [[VECTOR_PH]]:687; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 8688; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]689; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]690; DEFAULT: [[VECTOR_BODY]]:691; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE27:.*]] ]692; DEFAULT-NEXT: [[VEC_IND:%.*]] = phi <8 x i64> [ <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE27]] ]693; DEFAULT-NEXT: [[TMP15:%.*]] = load float, ptr [[SRC_1]], align 4694; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT8:%.*]] = insertelement <8 x float> poison, float [[TMP15]], i64 0695; DEFAULT-NEXT: [[BROADCAST_SPLAT9:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT8]], <8 x float> poison, <8 x i32> zeroinitializer696; DEFAULT-NEXT: [[TMP16:%.*]] = load float, ptr [[SRC_2]], align 4697; DEFAULT-NEXT: [[TMP17:%.*]] = fmul float [[TMP16]], 0.000000e+00698; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x float> poison, float [[TMP17]], i64 0699; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT]], <8 x float> poison, <8 x i32> zeroinitializer700; DEFAULT-NEXT: [[TMP18:%.*]] = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> [[BROADCAST_SPLAT9]], <8 x float> zeroinitializer, <8 x float> [[BROADCAST_SPLAT]])701; DEFAULT-NEXT: [[TMP19:%.*]] = load float, ptr [[SRC_3]], align 4702; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT10:%.*]] = insertelement <8 x float> poison, float [[TMP19]], i64 0703; DEFAULT-NEXT: [[BROADCAST_SPLAT11:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT10]], <8 x float> poison, <8 x i32> zeroinitializer704; DEFAULT-NEXT: [[TMP20:%.*]] = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> [[BROADCAST_SPLAT11]], <8 x float> zeroinitializer, <8 x float> [[TMP18]])705; DEFAULT-NEXT: [[TMP21:%.*]] = load float, ptr [[SRC_3]], align 4706; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT12:%.*]] = insertelement <8 x float> poison, float [[TMP21]], i64 0707; DEFAULT-NEXT: [[BROADCAST_SPLAT13:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT12]], <8 x float> poison, <8 x i32> zeroinitializer708; DEFAULT-NEXT: [[TMP22:%.*]] = fcmp ogt <8 x float> [[TMP20]], [[BROADCAST_SPLAT13]]709; DEFAULT-NEXT: [[TMP23:%.*]] = getelementptr { [4 x float] }, ptr [[DST]], <8 x i64> [[VEC_IND]]710; DEFAULT-NEXT: [[TMP24:%.*]] = extractelement <8 x i1> [[TMP22]], i32 0711; DEFAULT-NEXT: br i1 [[TMP24]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]712; DEFAULT: [[PRED_STORE_IF]]:713; DEFAULT-NEXT: [[TMP25:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 0714; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP25]], align 4715; DEFAULT-NEXT: [[TMP26:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 0716; DEFAULT-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP26]], i64 4717; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP27]], align 4718; DEFAULT-NEXT: [[TMP28:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 0719; DEFAULT-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP28]], i64 8720; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP29]], align 4721; DEFAULT-NEXT: [[TMP30:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 0722; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP30]], align 4723; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE]]724; DEFAULT: [[PRED_STORE_CONTINUE]]:725; DEFAULT-NEXT: [[TMP31:%.*]] = extractelement <8 x i1> [[TMP22]], i32 1726; DEFAULT-NEXT: br i1 [[TMP31]], label %[[PRED_STORE_IF14:.*]], label %[[PRED_STORE_CONTINUE15:.*]]727; DEFAULT: [[PRED_STORE_IF14]]:728; DEFAULT-NEXT: [[TMP32:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 1729; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP32]], align 4730; DEFAULT-NEXT: [[TMP33:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 1731; DEFAULT-NEXT: [[TMP34:%.*]] = getelementptr i8, ptr [[TMP33]], i64 4732; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP34]], align 4733; DEFAULT-NEXT: [[TMP35:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 1734; DEFAULT-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[TMP35]], i64 8735; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP36]], align 4736; DEFAULT-NEXT: [[TMP37:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 1737; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP37]], align 4738; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE15]]739; DEFAULT: [[PRED_STORE_CONTINUE15]]:740; DEFAULT-NEXT: [[TMP38:%.*]] = extractelement <8 x i1> [[TMP22]], i32 2741; DEFAULT-NEXT: br i1 [[TMP38]], label %[[PRED_STORE_IF16:.*]], label %[[PRED_STORE_CONTINUE17:.*]]742; DEFAULT: [[PRED_STORE_IF16]]:743; DEFAULT-NEXT: [[TMP39:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 2744; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP39]], align 4745; DEFAULT-NEXT: [[TMP40:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 2746; DEFAULT-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr [[TMP40]], i64 4747; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP41]], align 4748; DEFAULT-NEXT: [[TMP42:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 2749; DEFAULT-NEXT: [[TMP43:%.*]] = getelementptr i8, ptr [[TMP42]], i64 8750; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP43]], align 4751; DEFAULT-NEXT: [[TMP44:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 2752; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP44]], align 4753; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE17]]754; DEFAULT: [[PRED_STORE_CONTINUE17]]:755; DEFAULT-NEXT: [[TMP45:%.*]] = extractelement <8 x i1> [[TMP22]], i32 3756; DEFAULT-NEXT: br i1 [[TMP45]], label %[[PRED_STORE_IF18:.*]], label %[[PRED_STORE_CONTINUE19:.*]]757; DEFAULT: [[PRED_STORE_IF18]]:758; DEFAULT-NEXT: [[TMP46:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 3759; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP46]], align 4760; DEFAULT-NEXT: [[TMP47:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 3761; DEFAULT-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[TMP47]], i64 4762; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP48]], align 4763; DEFAULT-NEXT: [[TMP49:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 3764; DEFAULT-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr [[TMP49]], i64 8765; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP50]], align 4766; DEFAULT-NEXT: [[TMP51:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 3767; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP51]], align 4768; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE19]]769; DEFAULT: [[PRED_STORE_CONTINUE19]]:770; DEFAULT-NEXT: [[TMP52:%.*]] = extractelement <8 x i1> [[TMP22]], i32 4771; DEFAULT-NEXT: br i1 [[TMP52]], label %[[PRED_STORE_IF20:.*]], label %[[PRED_STORE_CONTINUE21:.*]]772; DEFAULT: [[PRED_STORE_IF20]]:773; DEFAULT-NEXT: [[TMP53:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 4774; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP53]], align 4775; DEFAULT-NEXT: [[TMP54:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 4776; DEFAULT-NEXT: [[TMP55:%.*]] = getelementptr i8, ptr [[TMP54]], i64 4777; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP55]], align 4778; DEFAULT-NEXT: [[TMP56:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 4779; DEFAULT-NEXT: [[TMP57:%.*]] = getelementptr i8, ptr [[TMP56]], i64 8780; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP57]], align 4781; DEFAULT-NEXT: [[TMP58:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 4782; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP58]], align 4783; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE21]]784; DEFAULT: [[PRED_STORE_CONTINUE21]]:785; DEFAULT-NEXT: [[TMP59:%.*]] = extractelement <8 x i1> [[TMP22]], i32 5786; DEFAULT-NEXT: br i1 [[TMP59]], label %[[PRED_STORE_IF22:.*]], label %[[PRED_STORE_CONTINUE23:.*]]787; DEFAULT: [[PRED_STORE_IF22]]:788; DEFAULT-NEXT: [[TMP60:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 5789; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP60]], align 4790; DEFAULT-NEXT: [[TMP61:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 5791; DEFAULT-NEXT: [[TMP62:%.*]] = getelementptr i8, ptr [[TMP61]], i64 4792; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP62]], align 4793; DEFAULT-NEXT: [[TMP63:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 5794; DEFAULT-NEXT: [[TMP64:%.*]] = getelementptr i8, ptr [[TMP63]], i64 8795; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP64]], align 4796; DEFAULT-NEXT: [[TMP65:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 5797; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP65]], align 4798; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE23]]799; DEFAULT: [[PRED_STORE_CONTINUE23]]:800; DEFAULT-NEXT: [[TMP66:%.*]] = extractelement <8 x i1> [[TMP22]], i32 6801; DEFAULT-NEXT: br i1 [[TMP66]], label %[[PRED_STORE_IF24:.*]], label %[[PRED_STORE_CONTINUE25:.*]]802; DEFAULT: [[PRED_STORE_IF24]]:803; DEFAULT-NEXT: [[TMP67:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 6804; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP67]], align 4805; DEFAULT-NEXT: [[TMP68:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 6806; DEFAULT-NEXT: [[TMP69:%.*]] = getelementptr i8, ptr [[TMP68]], i64 4807; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP69]], align 4808; DEFAULT-NEXT: [[TMP70:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 6809; DEFAULT-NEXT: [[TMP71:%.*]] = getelementptr i8, ptr [[TMP70]], i64 8810; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP71]], align 4811; DEFAULT-NEXT: [[TMP72:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 6812; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP72]], align 4813; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE25]]814; DEFAULT: [[PRED_STORE_CONTINUE25]]:815; DEFAULT-NEXT: [[TMP73:%.*]] = extractelement <8 x i1> [[TMP22]], i32 7816; DEFAULT-NEXT: br i1 [[TMP73]], label %[[PRED_STORE_IF26:.*]], label %[[PRED_STORE_CONTINUE27]]817; DEFAULT: [[PRED_STORE_IF26]]:818; DEFAULT-NEXT: [[TMP74:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 7819; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP74]], align 4820; DEFAULT-NEXT: [[TMP75:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 7821; DEFAULT-NEXT: [[TMP76:%.*]] = getelementptr i8, ptr [[TMP75]], i64 4822; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP76]], align 4823; DEFAULT-NEXT: [[TMP77:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 7824; DEFAULT-NEXT: [[TMP78:%.*]] = getelementptr i8, ptr [[TMP77]], i64 8825; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP78]], align 4826; DEFAULT-NEXT: [[TMP79:%.*]] = extractelement <8 x ptr> [[TMP23]], i32 7827; DEFAULT-NEXT: store float 0.000000e+00, ptr [[TMP79]], align 4828; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE27]]829; DEFAULT: [[PRED_STORE_CONTINUE27]]:830; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8831; DEFAULT-NEXT: [[VEC_IND_NEXT]] = add <8 x i64> [[VEC_IND]], splat (i64 8)832; DEFAULT-NEXT: [[TMP80:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]833; DEFAULT-NEXT: br i1 [[TMP80]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP25:![0-9]+]]834; DEFAULT: [[MIDDLE_BLOCK]]:835; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]836; DEFAULT-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]837; DEFAULT: [[SCALAR_PH]]:838;839; PRED-LABEL: define void @test_conditional_interleave_group(840; PRED-SAME: ptr noalias [[SRC_1:%.*]], ptr noalias [[SRC_2:%.*]], ptr noalias [[SRC_3:%.*]], ptr noalias [[SRC_4:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR3:[0-9]+]] {841; PRED-NEXT: [[ENTRY:.*:]]842; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1843; PRED-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]844; PRED: [[VECTOR_SCEVCHECK]]:845; PRED-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[N]])846; PRED-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0847; PRED-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1848; PRED-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[MUL_RESULT]]849; PRED-NEXT: [[TMP3:%.*]] = icmp ult ptr [[TMP2]], [[DST]]850; PRED-NEXT: [[TMP4:%.*]] = or i1 [[TMP3]], [[MUL_OVERFLOW]]851; PRED-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 4852; PRED-NEXT: [[MUL1:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[N]])853; PRED-NEXT: [[MUL_RESULT2:%.*]] = extractvalue { i64, i1 } [[MUL1]], 0854; PRED-NEXT: [[MUL_OVERFLOW3:%.*]] = extractvalue { i64, i1 } [[MUL1]], 1855; PRED-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[MUL_RESULT2]]856; PRED-NEXT: [[TMP7:%.*]] = icmp ult ptr [[TMP6]], [[SCEVGEP]]857; PRED-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW3]]858; PRED-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[DST]], i64 8859; PRED-NEXT: [[MUL5:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[N]])860; PRED-NEXT: [[MUL_RESULT6:%.*]] = extractvalue { i64, i1 } [[MUL5]], 0861; PRED-NEXT: [[MUL_OVERFLOW7:%.*]] = extractvalue { i64, i1 } [[MUL5]], 1862; PRED-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[SCEVGEP4]], i64 [[MUL_RESULT6]]863; PRED-NEXT: [[TMP11:%.*]] = icmp ult ptr [[TMP10]], [[SCEVGEP4]]864; PRED-NEXT: [[TMP12:%.*]] = or i1 [[TMP11]], [[MUL_OVERFLOW7]]865; PRED-NEXT: [[TMP13:%.*]] = or i1 [[TMP4]], [[TMP8]]866; PRED-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[TMP12]]867; PRED-NEXT: br i1 [[TMP14]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]868; PRED: [[VECTOR_PH]]:869; PRED-NEXT: [[TMP15:%.*]] = sub i64 [[TMP0]], 8870; PRED-NEXT: [[TMP16:%.*]] = icmp ugt i64 [[TMP0]], 8871; PRED-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i64 [[TMP15]], i64 0872; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 0, i64 [[TMP0]])873; PRED-NEXT: br label %[[VECTOR_BODY:.*]]874; PRED: [[VECTOR_BODY]]:875; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE27:.*]] ]876; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <8 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[PRED_STORE_CONTINUE27]] ]877; PRED-NEXT: [[VEC_IND:%.*]] = phi <8 x i64> [ <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE27]] ]878; PRED-NEXT: [[TMP18:%.*]] = load float, ptr [[SRC_1]], align 4879; PRED-NEXT: [[BROADCAST_SPLATINSERT8:%.*]] = insertelement <8 x float> poison, float [[TMP18]], i64 0880; PRED-NEXT: [[BROADCAST_SPLAT9:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT8]], <8 x float> poison, <8 x i32> zeroinitializer881; PRED-NEXT: [[TMP19:%.*]] = load float, ptr [[SRC_2]], align 4882; PRED-NEXT: [[TMP20:%.*]] = fmul float [[TMP19]], 0.000000e+00883; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x float> poison, float [[TMP20]], i64 0884; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT]], <8 x float> poison, <8 x i32> zeroinitializer885; PRED-NEXT: [[TMP21:%.*]] = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> [[BROADCAST_SPLAT9]], <8 x float> zeroinitializer, <8 x float> [[BROADCAST_SPLAT]])886; PRED-NEXT: [[TMP22:%.*]] = load float, ptr [[SRC_3]], align 4887; PRED-NEXT: [[BROADCAST_SPLATINSERT10:%.*]] = insertelement <8 x float> poison, float [[TMP22]], i64 0888; PRED-NEXT: [[BROADCAST_SPLAT11:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT10]], <8 x float> poison, <8 x i32> zeroinitializer889; PRED-NEXT: [[TMP23:%.*]] = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> [[BROADCAST_SPLAT11]], <8 x float> zeroinitializer, <8 x float> [[TMP21]])890; PRED-NEXT: [[TMP24:%.*]] = load float, ptr [[SRC_3]], align 4891; PRED-NEXT: [[BROADCAST_SPLATINSERT12:%.*]] = insertelement <8 x float> poison, float [[TMP24]], i64 0892; PRED-NEXT: [[BROADCAST_SPLAT13:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT12]], <8 x float> poison, <8 x i32> zeroinitializer893; PRED-NEXT: [[TMP25:%.*]] = fcmp ogt <8 x float> [[TMP23]], [[BROADCAST_SPLAT13]]894; PRED-NEXT: [[TMP26:%.*]] = select <8 x i1> [[ACTIVE_LANE_MASK]], <8 x i1> [[TMP25]], <8 x i1> zeroinitializer895; PRED-NEXT: [[TMP27:%.*]] = getelementptr { [4 x float] }, ptr [[DST]], <8 x i64> [[VEC_IND]]896; PRED-NEXT: [[TMP28:%.*]] = extractelement <8 x i1> [[TMP26]], i32 0897; PRED-NEXT: br i1 [[TMP28]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]898; PRED: [[PRED_STORE_IF]]:899; PRED-NEXT: [[TMP29:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 0900; PRED-NEXT: store float 0.000000e+00, ptr [[TMP29]], align 4901; PRED-NEXT: [[TMP30:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 0902; PRED-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[TMP30]], i64 4903; PRED-NEXT: store float 0.000000e+00, ptr [[TMP31]], align 4904; PRED-NEXT: [[TMP32:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 0905; PRED-NEXT: [[TMP33:%.*]] = getelementptr i8, ptr [[TMP32]], i64 8906; PRED-NEXT: store float 0.000000e+00, ptr [[TMP33]], align 4907; PRED-NEXT: [[TMP34:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 0908; PRED-NEXT: store float 0.000000e+00, ptr [[TMP34]], align 4909; PRED-NEXT: br label %[[PRED_STORE_CONTINUE]]910; PRED: [[PRED_STORE_CONTINUE]]:911; PRED-NEXT: [[TMP35:%.*]] = extractelement <8 x i1> [[TMP26]], i32 1912; PRED-NEXT: br i1 [[TMP35]], label %[[PRED_STORE_IF14:.*]], label %[[PRED_STORE_CONTINUE15:.*]]913; PRED: [[PRED_STORE_IF14]]:914; PRED-NEXT: [[TMP36:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 1915; PRED-NEXT: store float 0.000000e+00, ptr [[TMP36]], align 4916; PRED-NEXT: [[TMP37:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 1917; PRED-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[TMP37]], i64 4918; PRED-NEXT: store float 0.000000e+00, ptr [[TMP38]], align 4919; PRED-NEXT: [[TMP39:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 1920; PRED-NEXT: [[TMP40:%.*]] = getelementptr i8, ptr [[TMP39]], i64 8921; PRED-NEXT: store float 0.000000e+00, ptr [[TMP40]], align 4922; PRED-NEXT: [[TMP41:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 1923; PRED-NEXT: store float 0.000000e+00, ptr [[TMP41]], align 4924; PRED-NEXT: br label %[[PRED_STORE_CONTINUE15]]925; PRED: [[PRED_STORE_CONTINUE15]]:926; PRED-NEXT: [[TMP42:%.*]] = extractelement <8 x i1> [[TMP26]], i32 2927; PRED-NEXT: br i1 [[TMP42]], label %[[PRED_STORE_IF16:.*]], label %[[PRED_STORE_CONTINUE17:.*]]928; PRED: [[PRED_STORE_IF16]]:929; PRED-NEXT: [[TMP43:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 2930; PRED-NEXT: store float 0.000000e+00, ptr [[TMP43]], align 4931; PRED-NEXT: [[TMP44:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 2932; PRED-NEXT: [[TMP45:%.*]] = getelementptr i8, ptr [[TMP44]], i64 4933; PRED-NEXT: store float 0.000000e+00, ptr [[TMP45]], align 4934; PRED-NEXT: [[TMP46:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 2935; PRED-NEXT: [[TMP47:%.*]] = getelementptr i8, ptr [[TMP46]], i64 8936; PRED-NEXT: store float 0.000000e+00, ptr [[TMP47]], align 4937; PRED-NEXT: [[TMP48:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 2938; PRED-NEXT: store float 0.000000e+00, ptr [[TMP48]], align 4939; PRED-NEXT: br label %[[PRED_STORE_CONTINUE17]]940; PRED: [[PRED_STORE_CONTINUE17]]:941; PRED-NEXT: [[TMP49:%.*]] = extractelement <8 x i1> [[TMP26]], i32 3942; PRED-NEXT: br i1 [[TMP49]], label %[[PRED_STORE_IF18:.*]], label %[[PRED_STORE_CONTINUE19:.*]]943; PRED: [[PRED_STORE_IF18]]:944; PRED-NEXT: [[TMP50:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 3945; PRED-NEXT: store float 0.000000e+00, ptr [[TMP50]], align 4946; PRED-NEXT: [[TMP51:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 3947; PRED-NEXT: [[TMP52:%.*]] = getelementptr i8, ptr [[TMP51]], i64 4948; PRED-NEXT: store float 0.000000e+00, ptr [[TMP52]], align 4949; PRED-NEXT: [[TMP53:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 3950; PRED-NEXT: [[TMP54:%.*]] = getelementptr i8, ptr [[TMP53]], i64 8951; PRED-NEXT: store float 0.000000e+00, ptr [[TMP54]], align 4952; PRED-NEXT: [[TMP55:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 3953; PRED-NEXT: store float 0.000000e+00, ptr [[TMP55]], align 4954; PRED-NEXT: br label %[[PRED_STORE_CONTINUE19]]955; PRED: [[PRED_STORE_CONTINUE19]]:956; PRED-NEXT: [[TMP56:%.*]] = extractelement <8 x i1> [[TMP26]], i32 4957; PRED-NEXT: br i1 [[TMP56]], label %[[PRED_STORE_IF20:.*]], label %[[PRED_STORE_CONTINUE21:.*]]958; PRED: [[PRED_STORE_IF20]]:959; PRED-NEXT: [[TMP57:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 4960; PRED-NEXT: store float 0.000000e+00, ptr [[TMP57]], align 4961; PRED-NEXT: [[TMP58:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 4962; PRED-NEXT: [[TMP59:%.*]] = getelementptr i8, ptr [[TMP58]], i64 4963; PRED-NEXT: store float 0.000000e+00, ptr [[TMP59]], align 4964; PRED-NEXT: [[TMP60:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 4965; PRED-NEXT: [[TMP61:%.*]] = getelementptr i8, ptr [[TMP60]], i64 8966; PRED-NEXT: store float 0.000000e+00, ptr [[TMP61]], align 4967; PRED-NEXT: [[TMP62:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 4968; PRED-NEXT: store float 0.000000e+00, ptr [[TMP62]], align 4969; PRED-NEXT: br label %[[PRED_STORE_CONTINUE21]]970; PRED: [[PRED_STORE_CONTINUE21]]:971; PRED-NEXT: [[TMP63:%.*]] = extractelement <8 x i1> [[TMP26]], i32 5972; PRED-NEXT: br i1 [[TMP63]], label %[[PRED_STORE_IF22:.*]], label %[[PRED_STORE_CONTINUE23:.*]]973; PRED: [[PRED_STORE_IF22]]:974; PRED-NEXT: [[TMP64:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 5975; PRED-NEXT: store float 0.000000e+00, ptr [[TMP64]], align 4976; PRED-NEXT: [[TMP65:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 5977; PRED-NEXT: [[TMP66:%.*]] = getelementptr i8, ptr [[TMP65]], i64 4978; PRED-NEXT: store float 0.000000e+00, ptr [[TMP66]], align 4979; PRED-NEXT: [[TMP67:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 5980; PRED-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP67]], i64 8981; PRED-NEXT: store float 0.000000e+00, ptr [[TMP68]], align 4982; PRED-NEXT: [[TMP69:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 5983; PRED-NEXT: store float 0.000000e+00, ptr [[TMP69]], align 4984; PRED-NEXT: br label %[[PRED_STORE_CONTINUE23]]985; PRED: [[PRED_STORE_CONTINUE23]]:986; PRED-NEXT: [[TMP70:%.*]] = extractelement <8 x i1> [[TMP26]], i32 6987; PRED-NEXT: br i1 [[TMP70]], label %[[PRED_STORE_IF24:.*]], label %[[PRED_STORE_CONTINUE25:.*]]988; PRED: [[PRED_STORE_IF24]]:989; PRED-NEXT: [[TMP71:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 6990; PRED-NEXT: store float 0.000000e+00, ptr [[TMP71]], align 4991; PRED-NEXT: [[TMP72:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 6992; PRED-NEXT: [[TMP73:%.*]] = getelementptr i8, ptr [[TMP72]], i64 4993; PRED-NEXT: store float 0.000000e+00, ptr [[TMP73]], align 4994; PRED-NEXT: [[TMP74:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 6995; PRED-NEXT: [[TMP75:%.*]] = getelementptr i8, ptr [[TMP74]], i64 8996; PRED-NEXT: store float 0.000000e+00, ptr [[TMP75]], align 4997; PRED-NEXT: [[TMP76:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 6998; PRED-NEXT: store float 0.000000e+00, ptr [[TMP76]], align 4999; PRED-NEXT: br label %[[PRED_STORE_CONTINUE25]]1000; PRED: [[PRED_STORE_CONTINUE25]]:1001; PRED-NEXT: [[TMP77:%.*]] = extractelement <8 x i1> [[TMP26]], i32 71002; PRED-NEXT: br i1 [[TMP77]], label %[[PRED_STORE_IF26:.*]], label %[[PRED_STORE_CONTINUE27]]1003; PRED: [[PRED_STORE_IF26]]:1004; PRED-NEXT: [[TMP78:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 71005; PRED-NEXT: store float 0.000000e+00, ptr [[TMP78]], align 41006; PRED-NEXT: [[TMP79:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 71007; PRED-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP79]], i64 41008; PRED-NEXT: store float 0.000000e+00, ptr [[TMP80]], align 41009; PRED-NEXT: [[TMP81:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 71010; PRED-NEXT: [[TMP82:%.*]] = getelementptr i8, ptr [[TMP81]], i64 81011; PRED-NEXT: store float 0.000000e+00, ptr [[TMP82]], align 41012; PRED-NEXT: [[TMP83:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 71013; PRED-NEXT: store float 0.000000e+00, ptr [[TMP83]], align 41014; PRED-NEXT: br label %[[PRED_STORE_CONTINUE27]]1015; PRED: [[PRED_STORE_CONTINUE27]]:1016; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 81017; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 [[INDEX]], i64 [[TMP17]])1018; PRED-NEXT: [[TMP84:%.*]] = extractelement <8 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 01019; PRED-NEXT: [[TMP85:%.*]] = xor i1 [[TMP84]], true1020; PRED-NEXT: [[VEC_IND_NEXT]] = add <8 x i64> [[VEC_IND]], splat (i64 8)1021; PRED-NEXT: br i1 [[TMP85]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]1022; PRED: [[MIDDLE_BLOCK]]:1023; PRED-NEXT: br [[EXIT:label %.*]]1024; PRED: [[SCALAR_PH]]:1025;1026entry:1027 br label %loop.header1028 1029loop.header:1030 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]1031 %0 = load float, ptr %src.1, align 41032 %1 = load float, ptr %src.2, align 41033 %mul8.i.us = fmul float %1, 0.000000e+001034 %2 = tail call float @llvm.fmuladd.f32(float %0, float 0.000000e+00, float %mul8.i.us)1035 %3 = load float, ptr %src.3, align 41036 %4 = tail call float @llvm.fmuladd.f32(float %3, float 0.000000e+00, float %2)1037 %5 = load float, ptr %src.3, align 41038 %c = fcmp ogt float %4, %51039 br i1 %c, label %if.then, label %loop.latch1040 1041if.then:1042 %dst.0 = getelementptr { [4 x float] }, ptr %dst, i64 %iv1043 store float 0.000000e+00, ptr %dst.0, align 41044 %dst.1 = getelementptr i8, ptr %dst.0, i64 41045 store float 0.000000e+00, ptr %dst.1, align 41046 %dst.2 = getelementptr i8, ptr %dst.0, i64 81047 store float 0.000000e+00, ptr %dst.2, align 41048 %dst.3 = getelementptr i8, ptr %dst.0, i64 161049 store float 0.000000e+00, ptr %dst.0, align 41050 br label %loop.latch1051 1052loop.latch:1053 %iv.next = add i64 %iv, 11054 %ec = icmp eq i64 %iv, %N1055 br i1 %ec, label %exit, label %loop.header, !llvm.loop !01056 1057exit:1058 ret void1059}1060 1061define void @redundant_branch_and_tail_folding(ptr %dst, i1 %c) {1062; DEFAULT-LABEL: define void @redundant_branch_and_tail_folding(1063; DEFAULT-SAME: ptr [[DST:%.*]], i1 [[C:%.*]]) {1064; DEFAULT-NEXT: [[ENTRY:.*:]]1065; DEFAULT-NEXT: br label %[[VECTOR_PH:.*]]1066; DEFAULT: [[VECTOR_PH]]:1067; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]1068; DEFAULT: [[VECTOR_BODY]]:1069; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1070; DEFAULT-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]1071; DEFAULT-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 4)1072; DEFAULT-NEXT: [[TMP0:%.*]] = add nuw nsw <4 x i64> [[STEP_ADD]], splat (i64 1)1073; DEFAULT-NEXT: [[TMP1:%.*]] = trunc nuw nsw <4 x i64> [[TMP0]] to <4 x i32>1074; DEFAULT-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 31075; DEFAULT-NEXT: store i32 [[TMP2]], ptr [[DST]], align 41076; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 81077; DEFAULT-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[STEP_ADD]], splat (i64 4)1078; DEFAULT-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 161079; DEFAULT-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP27:![0-9]+]]1080; DEFAULT: [[MIDDLE_BLOCK]]:1081; DEFAULT-NEXT: br label %[[SCALAR_PH:.*]]1082; DEFAULT: [[SCALAR_PH]]:1083;1084; PRED-LABEL: define void @redundant_branch_and_tail_folding(1085; PRED-SAME: ptr [[DST:%.*]], i1 [[C:%.*]]) {1086; PRED-NEXT: [[ENTRY:.*:]]1087; PRED-NEXT: br label %[[VECTOR_PH:.*]]1088; PRED: [[VECTOR_PH]]:1089; PRED-NEXT: br label %[[VECTOR_BODY:.*]]1090; PRED: [[VECTOR_BODY]]:1091; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE6:.*]] ]1092; PRED-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE6]] ]1093; PRED-NEXT: [[TMP0:%.*]] = icmp ule <4 x i64> [[VEC_IND]], splat (i64 20)1094; PRED-NEXT: [[TMP1:%.*]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 1)1095; PRED-NEXT: [[TMP2:%.*]] = trunc nuw nsw <4 x i64> [[TMP1]] to <4 x i32>1096; PRED-NEXT: [[TMP3:%.*]] = extractelement <4 x i1> [[TMP0]], i32 01097; PRED-NEXT: br i1 [[TMP3]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]1098; PRED: [[PRED_STORE_IF]]:1099; PRED-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP2]], i32 01100; PRED-NEXT: store i32 [[TMP4]], ptr [[DST]], align 41101; PRED-NEXT: br label %[[PRED_STORE_CONTINUE]]1102; PRED: [[PRED_STORE_CONTINUE]]:1103; PRED-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP0]], i32 11104; PRED-NEXT: br i1 [[TMP5]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]1105; PRED: [[PRED_STORE_IF1]]:1106; PRED-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP2]], i32 11107; PRED-NEXT: store i32 [[TMP6]], ptr [[DST]], align 41108; PRED-NEXT: br label %[[PRED_STORE_CONTINUE2]]1109; PRED: [[PRED_STORE_CONTINUE2]]:1110; PRED-NEXT: [[TMP7:%.*]] = extractelement <4 x i1> [[TMP0]], i32 21111; PRED-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]1112; PRED: [[PRED_STORE_IF3]]:1113; PRED-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP2]], i32 21114; PRED-NEXT: store i32 [[TMP8]], ptr [[DST]], align 41115; PRED-NEXT: br label %[[PRED_STORE_CONTINUE4]]1116; PRED: [[PRED_STORE_CONTINUE4]]:1117; PRED-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP0]], i32 31118; PRED-NEXT: br i1 [[TMP9]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6]]1119; PRED: [[PRED_STORE_IF5]]:1120; PRED-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> [[TMP2]], i32 31121; PRED-NEXT: store i32 [[TMP10]], ptr [[DST]], align 41122; PRED-NEXT: br label %[[PRED_STORE_CONTINUE6]]1123; PRED: [[PRED_STORE_CONTINUE6]]:1124; PRED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 41125; PRED-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4)1126; PRED-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 241127; PRED-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]1128; PRED: [[MIDDLE_BLOCK]]:1129; PRED-NEXT: br label %[[EXIT:.*]]1130; PRED: [[EXIT]]:1131; PRED-NEXT: ret void1132;1133entry:1134 br label %loop.header1135 1136loop.header:1137 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]1138 br i1 %c, label %loop.latch, label %then1139 1140then:1141 br label %loop.latch1142 1143loop.latch:1144 %iv.next = add nuw nsw i64 %iv, 11145 %t = trunc nuw nsw i64 %iv.next to i321146 store i32 %t, ptr %dst, align 41147 %ec = icmp eq i64 %iv.next, 211148 br i1 %ec, label %exit, label %loop.header1149 1150exit:1151 ret void1152}1153 1154define double @test_cond_intrinsics(ptr %A, i1 %c) {1155; COMMON-LABEL: define double @test_cond_intrinsics(1156; COMMON-SAME: ptr [[A:%.*]], i1 [[C:%.*]]) {1157; COMMON-NEXT: [[ENTRY:.*]]:1158; COMMON-NEXT: br label %[[LOOP_HEADER:.*]]1159; COMMON: [[LOOP_HEADER]]:1160; COMMON-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]1161; COMMON-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]]1162; COMMON: [[THEN]]:1163; COMMON-NEXT: [[GEP:%.*]] = getelementptr inbounds double, ptr [[A]], i64 [[IV]]1164; COMMON-NEXT: [[L:%.*]] = load double, ptr [[GEP]], align 81165; COMMON-NEXT: [[POW:%.*]] = tail call double @llvm.pow.f64(double 2.000000e+00, double [[L]])1166; COMMON-NEXT: store double [[POW]], ptr [[GEP]], align 81167; COMMON-NEXT: br label %[[LOOP_LATCH]]1168; COMMON: [[LOOP_LATCH]]:1169; COMMON-NEXT: [[P:%.*]] = phi double [ 0.000000e+00, %[[LOOP_HEADER]] ], [ [[POW]], %[[THEN]] ]1170; COMMON-NEXT: [[IV_NEXT]] = add i64 [[IV]], 11171; COMMON-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 10241172; COMMON-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]1173; COMMON: [[EXIT]]:1174; COMMON-NEXT: [[P_LCSSA:%.*]] = phi double [ [[P]], %[[LOOP_LATCH]] ]1175; COMMON-NEXT: ret double [[P_LCSSA]]1176;1177entry:1178 br label %loop.header1179 1180loop.header: ; preds = %loop.latch, %entry1181 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]1182 br i1 %c, label %then, label %loop.latch1183 1184then:1185 %gep = getelementptr inbounds double, ptr %A, i64 %iv1186 %l = load double, ptr %gep, align 81187 %pow = tail call double @llvm.pow.f64(double 2.0, double %l)1188 store double %pow, ptr %gep1189 br label %loop.latch1190 1191loop.latch:1192 %p = phi double [ 0.000000e+00, %loop.header ], [ %pow, %then ]1193 %iv.next = add i64 %iv, 11194 %ec = icmp eq i64 %iv, 10241195 br i1 %ec, label %exit, label %loop.header1196 1197exit:1198 ret double %p1199}1200 1201define void @pred_udiv_select_cost(ptr %A, ptr %B, ptr %C, i64 %n, i8 %y) #1 {1202; DEFAULT-LABEL: define void @pred_udiv_select_cost(1203; DEFAULT-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]], i8 [[Y:%.*]]) #[[ATTR2]] {1204; DEFAULT-NEXT: [[ENTRY:.*:]]1205; DEFAULT-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i641206; DEFAULT-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i641207; DEFAULT-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i641208; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 11209; DEFAULT-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()1210; DEFAULT-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 21211; DEFAULT-NEXT: [[TMP3:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP2]], i64 8)1212; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP3]]1213; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]1214; DEFAULT: [[VECTOR_MEMCHECK]]:1215; DEFAULT-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()1216; DEFAULT-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 41217; DEFAULT-NEXT: [[TMP6:%.*]] = sub i64 [[C1]], [[A2]]1218; DEFAULT-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]1219; DEFAULT-NEXT: [[TMP7:%.*]] = sub i64 [[C1]], [[B3]]1220; DEFAULT-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP7]], [[TMP5]]1221; DEFAULT-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]1222; DEFAULT-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]1223; DEFAULT: [[VECTOR_PH]]:1224; DEFAULT-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()1225; DEFAULT-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 41226; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], [[TMP9]]1227; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]1228; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i8> poison, i8 [[Y]], i64 01229; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i8> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer1230; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]1231; DEFAULT: [[VECTOR_BODY]]:1232; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1233; DEFAULT-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]1234; DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i8>, ptr [[TMP10]], align 11235; DEFAULT-NEXT: [[TMP11:%.*]] = uitofp <vscale x 4 x i8> [[WIDE_LOAD]] to <vscale x 4 x float>1236; DEFAULT-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]1237; DEFAULT-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 4 x i8>, ptr [[TMP12]], align 11238; DEFAULT-NEXT: [[TMP13:%.*]] = icmp eq <vscale x 4 x i8> [[WIDE_LOAD5]], zeroinitializer1239; DEFAULT-NEXT: [[TMP14:%.*]] = xor <vscale x 4 x i8> [[WIDE_LOAD]], splat (i8 1)1240; DEFAULT-NEXT: [[TMP15:%.*]] = select <vscale x 4 x i1> [[TMP13]], <vscale x 4 x i8> splat (i8 1), <vscale x 4 x i8> [[BROADCAST_SPLAT]]1241; DEFAULT-NEXT: [[TMP16:%.*]] = udiv <vscale x 4 x i8> [[TMP14]], [[TMP15]]1242; DEFAULT-NEXT: [[TMP17:%.*]] = icmp ugt <vscale x 4 x i8> [[TMP16]], splat (i8 1)1243; DEFAULT-NEXT: [[TMP18:%.*]] = select <vscale x 4 x i1> [[TMP17]], <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> splat (i32 255)1244; DEFAULT-NEXT: [[PREDPHI:%.*]] = select <vscale x 4 x i1> [[TMP13]], <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> [[TMP18]]1245; DEFAULT-NEXT: [[TMP19:%.*]] = zext <vscale x 4 x i8> [[WIDE_LOAD]] to <vscale x 4 x i32>1246; DEFAULT-NEXT: [[TMP20:%.*]] = sub <vscale x 4 x i32> [[PREDPHI]], [[TMP19]]1247; DEFAULT-NEXT: [[TMP21:%.*]] = sitofp <vscale x 4 x i32> [[TMP20]] to <vscale x 4 x float>1248; DEFAULT-NEXT: [[TMP22:%.*]] = call <vscale x 4 x float> @llvm.fmuladd.nxv4f32(<vscale x 4 x float> [[TMP21]], <vscale x 4 x float> splat (float 3.000000e+00), <vscale x 4 x float> [[TMP11]])1249; DEFAULT-NEXT: [[TMP23:%.*]] = fptoui <vscale x 4 x float> [[TMP22]] to <vscale x 4 x i8>1250; DEFAULT-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[C]], i64 [[INDEX]]1251; DEFAULT-NEXT: store <vscale x 4 x i8> [[TMP23]], ptr [[TMP24]], align 11252; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP9]]1253; DEFAULT-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]1254; DEFAULT-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP29:![0-9]+]]1255; DEFAULT: [[MIDDLE_BLOCK]]:1256; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]1257; DEFAULT-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]1258; DEFAULT: [[SCALAR_PH]]:1259;1260; PRED-LABEL: define void @pred_udiv_select_cost(1261; PRED-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]], i8 [[Y:%.*]]) #[[ATTR2]] {1262; PRED-NEXT: [[ENTRY:.*:]]1263; PRED-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i641264; PRED-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i641265; PRED-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i641266; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 11267; PRED-NEXT: br label %[[VECTOR_MEMCHECK:.*]]1268; PRED: [[VECTOR_MEMCHECK]]:1269; PRED-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()1270; PRED-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 161271; PRED-NEXT: [[TMP3:%.*]] = sub i64 [[C1]], [[A2]]1272; PRED-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP3]], [[TMP2]]1273; PRED-NEXT: [[TMP4:%.*]] = sub i64 [[C1]], [[B3]]1274; PRED-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP4]], [[TMP2]]1275; PRED-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]1276; PRED-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]1277; PRED: [[VECTOR_PH]]:1278; PRED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()1279; PRED-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 161280; PRED-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()1281; PRED-NEXT: [[TMP8:%.*]] = shl nuw i64 [[TMP7]], 41282; PRED-NEXT: [[TMP9:%.*]] = sub i64 [[TMP0]], [[TMP8]]1283; PRED-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP0]], [[TMP8]]1284; PRED-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP9]], i64 01285; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 [[TMP0]])1286; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[Y]], i64 01287; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[BROADCAST_SPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer1288; PRED-NEXT: br label %[[VECTOR_BODY:.*]]1289; PRED: [[VECTOR_BODY]]:1290; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1291; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 16 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]1292; PRED-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]1293; PRED-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr align 1 [[TMP12]], <vscale x 16 x i1> [[ACTIVE_LANE_MASK]], <vscale x 16 x i8> poison)1294; PRED-NEXT: [[TMP13:%.*]] = uitofp <vscale x 16 x i8> [[WIDE_MASKED_LOAD]] to <vscale x 16 x float>1295; PRED-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]1296; PRED-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr align 1 [[TMP14]], <vscale x 16 x i1> [[ACTIVE_LANE_MASK]], <vscale x 16 x i8> poison)1297; PRED-NEXT: [[TMP15:%.*]] = icmp ne <vscale x 16 x i8> [[WIDE_MASKED_LOAD5]], zeroinitializer1298; PRED-NEXT: [[TMP16:%.*]] = select <vscale x 16 x i1> [[ACTIVE_LANE_MASK]], <vscale x 16 x i1> [[TMP15]], <vscale x 16 x i1> zeroinitializer1299; PRED-NEXT: [[TMP17:%.*]] = xor <vscale x 16 x i8> [[WIDE_MASKED_LOAD]], splat (i8 1)1300; PRED-NEXT: [[TMP18:%.*]] = select <vscale x 16 x i1> [[TMP16]], <vscale x 16 x i8> [[BROADCAST_SPLAT]], <vscale x 16 x i8> splat (i8 1)1301; PRED-NEXT: [[TMP19:%.*]] = udiv <vscale x 16 x i8> [[TMP17]], [[TMP18]]1302; PRED-NEXT: [[TMP20:%.*]] = icmp ugt <vscale x 16 x i8> [[TMP19]], splat (i8 1)1303; PRED-NEXT: [[TMP21:%.*]] = select <vscale x 16 x i1> [[TMP20]], <vscale x 16 x i32> zeroinitializer, <vscale x 16 x i32> splat (i32 255)1304; PRED-NEXT: [[PREDPHI:%.*]] = select <vscale x 16 x i1> [[TMP15]], <vscale x 16 x i32> [[TMP21]], <vscale x 16 x i32> zeroinitializer1305; PRED-NEXT: [[TMP22:%.*]] = zext <vscale x 16 x i8> [[WIDE_MASKED_LOAD]] to <vscale x 16 x i32>1306; PRED-NEXT: [[TMP23:%.*]] = sub <vscale x 16 x i32> [[PREDPHI]], [[TMP22]]1307; PRED-NEXT: [[TMP24:%.*]] = sitofp <vscale x 16 x i32> [[TMP23]] to <vscale x 16 x float>1308; PRED-NEXT: [[TMP25:%.*]] = call <vscale x 16 x float> @llvm.fmuladd.nxv16f32(<vscale x 16 x float> [[TMP24]], <vscale x 16 x float> splat (float 3.000000e+00), <vscale x 16 x float> [[TMP13]])1309; PRED-NEXT: [[TMP26:%.*]] = fptoui <vscale x 16 x float> [[TMP25]] to <vscale x 16 x i8>1310; PRED-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[C]], i64 [[INDEX]]1311; PRED-NEXT: call void @llvm.masked.store.nxv16i8.p0(<vscale x 16 x i8> [[TMP26]], ptr align 1 [[TMP27]], <vscale x 16 x i1> [[ACTIVE_LANE_MASK]])1312; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP6]]1313; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[INDEX]], i64 [[TMP11]])1314; PRED-NEXT: [[TMP28:%.*]] = extractelement <vscale x 16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 01315; PRED-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], true1316; PRED-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]1317; PRED: [[MIDDLE_BLOCK]]:1318; PRED-NEXT: br [[EXIT:label %.*]]1319; PRED: [[SCALAR_PH]]:1320;1321entry:1322 br label %loop.header1323 1324loop.header: ; preds = %loop.latch, %entry1325 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]1326 %gep.A = getelementptr i8, ptr %A, i64 %iv1327 %l.1 = load i8, ptr %gep.A, align 11328 %l.1.to.float = uitofp i8 %l.1 to float1329 %gep.B = getelementptr i8, ptr %B, i64 %iv1330 %l.2 = load i8, ptr %gep.B, align 11331 %c = icmp eq i8 %l.2, 01332 br i1 %c, label %loop.latch, label %else1333 1334else:1335 %x = xor i8 %l.1, 11336 %ud = udiv i8 %x, %y1337 %c.sel = icmp ugt i8 %ud, 11338 %sel = select i1 %c.sel, i32 0, i32 2551339 br label %loop.latch1340 1341loop.latch:1342 %p = phi i32 [ %sel, %else ], [ 0, %loop.header ]1343 %l.1.ext = zext i8 %l.1 to i321344 %sub = sub i32 %p, %l.1.ext1345 %sub.to.float = sitofp i32 %sub to float1346 %muladd = tail call float @llvm.fmuladd.f32(float %sub.to.float, float 3.000000e+00, float %l.1.to.float)1347 %muladd.conv = fptoui float %muladd to i81348 %gep.C = getelementptr i8, ptr %C, i64 %iv1349 store i8 %muladd.conv, ptr %gep.C, align 11350 %iv.next = add i64 %iv, 11351 %ec = icmp eq i64 %iv, %n1352 br i1 %ec, label %exit, label %loop.header1353 1354exit:1355 ret void1356}1357 1358declare float @llvm.fmuladd.f32(float, float, float) #11359declare double @llvm.pow.f64(double, double)1360 1361attributes #1 = { "target-cpu"="neoverse-512tvb" }1362attributes #2 = { vscale_range(2,2) "target-cpu"="neoverse-512tvb" }1363 1364!0 = distinct !{!0, !1, !2, !3}1365!1 = !{!"llvm.loop.vectorize.width", i32 8}1366!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 false}1367!3 = !{!"llvm.loop.vectorize.enable", i1 true}1368