335 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -mtriple aarch64 -mcpu=neoverse-v1 -S %s | FileCheck %s3 4; Test case for https://github.com/llvm/llvm-project/issues/94328.5define void @sdiv_feeding_gep(ptr %dst, i32 %x, i64 %M, i64 %conv6, i64 %N) {6; CHECK-LABEL: define void @sdiv_feeding_gep(7; CHECK-SAME: ptr [[DST:%.*]], i32 [[X:%.*]], i64 [[M:%.*]], i64 [[CONV6:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {8; CHECK-NEXT: [[ENTRY:.*]]:9; CHECK-NEXT: [[CONV61:%.*]] = zext i32 [[X]] to i6410; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()11; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP10]], 212; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP1]], i64 8)13; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP2]]14; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]15; CHECK: [[VECTOR_SCEVCHECK]]:16; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[N]], -117; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i3218; CHECK-NEXT: [[TMP5:%.*]] = icmp slt i32 [[TMP4]], 019; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[TMP3]], 429496729520; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]21; CHECK-NEXT: br i1 [[TMP7]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]22; CHECK: [[VECTOR_PH]]:23; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()24; CHECK-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 425; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP9]]26; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]27; CHECK-NEXT: [[TMP18:%.*]] = sdiv i64 [[M]], [[CONV6]]28; CHECK-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP18]] to i3229; CHECK-NEXT: [[TMP22:%.*]] = mul i64 [[TMP18]], [[CONV61]]30; CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[X]], [[TMP20]]31; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]32; CHECK: [[VECTOR_BODY]]:33; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]34; CHECK-NEXT: [[TMP24:%.*]] = sub i64 [[INDEX]], [[TMP22]]35; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP24]] to i3236; CHECK-NEXT: [[TMP30:%.*]] = add i32 [[TMP28]], [[TMP26]]37; CHECK-NEXT: [[TMP32:%.*]] = sext i32 [[TMP30]] to i6438; CHECK-NEXT: [[TMP34:%.*]] = getelementptr double, ptr [[DST]], i64 [[TMP32]]39; CHECK-NEXT: [[TMP37:%.*]] = call i64 @llvm.vscale.i64()40; CHECK-NEXT: [[TMP38:%.*]] = shl nuw i64 [[TMP37]], 141; CHECK-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[TMP34]], i64 [[TMP38]]42; CHECK-NEXT: store <vscale x 2 x double> zeroinitializer, ptr [[TMP34]], align 843; CHECK-NEXT: store <vscale x 2 x double> zeroinitializer, ptr [[TMP39]], align 844; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP9]]45; CHECK-NEXT: [[TMP40:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]46; CHECK-NEXT: br i1 [[TMP40]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]47; CHECK: [[MIDDLE_BLOCK]]:48; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]49; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]50; CHECK: [[SCALAR_PH]]:51; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]52; CHECK-NEXT: br label %[[LOOP:.*]]53; CHECK: [[LOOP]]:54; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]55; CHECK-NEXT: [[DIV18:%.*]] = sdiv i64 [[M]], [[CONV6]]56; CHECK-NEXT: [[CONV20:%.*]] = trunc i64 [[DIV18]] to i3257; CHECK-NEXT: [[MUL30:%.*]] = mul i64 [[DIV18]], [[CONV61]]58; CHECK-NEXT: [[SUB31:%.*]] = sub i64 [[IV]], [[MUL30]]59; CHECK-NEXT: [[CONV34:%.*]] = trunc i64 [[SUB31]] to i3260; CHECK-NEXT: [[MUL35:%.*]] = mul i32 [[X]], [[CONV20]]61; CHECK-NEXT: [[ADD36:%.*]] = add i32 [[MUL35]], [[CONV34]]62; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[ADD36]] to i6463; CHECK-NEXT: [[GEP:%.*]] = getelementptr double, ptr [[DST]], i64 [[IDXPROM]]64; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP]], align 865; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 166; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]67; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]68; CHECK: [[EXIT]]:69; CHECK-NEXT: ret void70;71entry:72 %conv61 = zext i32 %x to i6473 br label %loop74 75loop:76 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]77 %div18 = sdiv i64 %M, %conv678 %conv20 = trunc i64 %div18 to i3279 %mul30 = mul i64 %div18, %conv6180 %sub31 = sub i64 %iv, %mul3081 %conv34 = trunc i64 %sub31 to i3282 %mul35 = mul i32 %x, %conv2083 %add36 = add i32 %mul35, %conv3484 %idxprom = sext i32 %add36 to i6485 %gep = getelementptr double, ptr %dst, i64 %idxprom86 store double 0.000000e+00, ptr %gep, align 887 %iv.next = add i64 %iv, 188 %ec = icmp eq i64 %iv.next, %N89 br i1 %ec, label %exit, label %loop90 91exit:92 ret void93}94 95define void @sdiv_feeding_gep_predicated(ptr %dst, i32 %x, i64 %M, i64 %conv6, i64 %N) {96; CHECK-LABEL: define void @sdiv_feeding_gep_predicated(97; CHECK-SAME: ptr [[DST:%.*]], i32 [[X:%.*]], i64 [[M:%.*]], i64 [[CONV6:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {98; CHECK-NEXT: [[ENTRY:.*:]]99; CHECK-NEXT: [[CONV61:%.*]] = zext i32 [[X]] to i64100; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]101; CHECK: [[VECTOR_SCEVCHECK]]:102; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1103; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32104; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0105; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i64 [[TMP0]], 4294967295106; CHECK-NEXT: [[TMP4:%.*]] = or i1 [[TMP2]], [[TMP3]]107; CHECK-NEXT: br i1 [[TMP4]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]108; CHECK: [[VECTOR_PH]]:109; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()110; CHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 2111; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()112; CHECK-NEXT: [[TMP11:%.*]] = shl nuw i64 [[TMP10]], 1113; CHECK-NEXT: [[TMP12:%.*]] = sub i64 [[N]], [[TMP11]]114; CHECK-NEXT: [[TMP13:%.*]] = icmp ugt i64 [[N]], [[TMP11]]115; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i64 [[TMP12]], i64 0116; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 0, i64 [[N]])117; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[M]], i64 0118; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer119; CHECK-NEXT: [[TMP15:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()120; CHECK-NEXT: [[TMP17:%.*]] = mul <vscale x 2 x i64> [[TMP15]], splat (i64 1)121; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i64> zeroinitializer, [[TMP17]]122; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP6]], i64 0123; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer124; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]125; CHECK: [[VECTOR_BODY]]:126; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]127; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 2 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]128; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]129; CHECK-NEXT: [[TMP22:%.*]] = icmp ule <vscale x 2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]130; CHECK-NEXT: [[TMP23:%.*]] = select <vscale x 2 x i1> [[ACTIVE_LANE_MASK]], <vscale x 2 x i1> [[TMP22]], <vscale x 2 x i1> zeroinitializer131; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 2 x i1> [[TMP23]], i32 0132; CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i64 [[CONV6]], i64 1133; CHECK-NEXT: [[TMP26:%.*]] = sdiv i64 [[M]], [[TMP25]]134; CHECK-NEXT: [[TMP27:%.*]] = trunc i64 [[TMP26]] to i32135; CHECK-NEXT: [[TMP28:%.*]] = mul i64 [[TMP26]], [[CONV61]]136; CHECK-NEXT: [[TMP29:%.*]] = sub i64 [[INDEX]], [[TMP28]]137; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[TMP29]] to i32138; CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[X]], [[TMP27]]139; CHECK-NEXT: [[TMP32:%.*]] = add i32 [[TMP31]], [[TMP30]]140; CHECK-NEXT: [[TMP33:%.*]] = sext i32 [[TMP32]] to i64141; CHECK-NEXT: [[TMP34:%.*]] = getelementptr double, ptr [[DST]], i64 [[TMP33]]142; CHECK-NEXT: call void @llvm.masked.store.nxv2f64.p0(<vscale x 2 x double> zeroinitializer, ptr align 8 [[TMP34]], <vscale x 2 x i1> [[TMP23]])143; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP6]]144; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[INDEX]], i64 [[TMP14]])145; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 2 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 0146; CHECK-NEXT: [[TMP36:%.*]] = xor i1 [[TMP35]], true147; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i64> [[VEC_IND]], [[DOTSPLAT]]148; CHECK-NEXT: br i1 [[TMP36]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]149; CHECK: [[MIDDLE_BLOCK]]:150; CHECK-NEXT: br label %[[EXIT:.*]]151; CHECK: [[SCALAR_PH]]:152; CHECK-NEXT: br label %[[LOOP:.*]]153; CHECK: [[LOOP]]:154; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]155; CHECK-NEXT: [[C:%.*]] = icmp ule i64 [[IV]], [[M]]156; CHECK-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]]157; CHECK: [[THEN]]:158; CHECK-NEXT: [[DIV18:%.*]] = sdiv i64 [[M]], [[CONV6]]159; CHECK-NEXT: [[CONV20:%.*]] = trunc i64 [[DIV18]] to i32160; CHECK-NEXT: [[MUL30:%.*]] = mul i64 [[DIV18]], [[CONV61]]161; CHECK-NEXT: [[SUB31:%.*]] = sub i64 [[IV]], [[MUL30]]162; CHECK-NEXT: [[CONV34:%.*]] = trunc i64 [[SUB31]] to i32163; CHECK-NEXT: [[MUL35:%.*]] = mul i32 [[X]], [[CONV20]]164; CHECK-NEXT: [[ADD36:%.*]] = add i32 [[MUL35]], [[CONV34]]165; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[ADD36]] to i64166; CHECK-NEXT: [[GEP:%.*]] = getelementptr double, ptr [[DST]], i64 [[IDXPROM]]167; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP]], align 8168; CHECK-NEXT: br label %[[LOOP_LATCH]]169; CHECK: [[LOOP_LATCH]]:170; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1171; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]172; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]173; CHECK: [[EXIT]]:174; CHECK-NEXT: ret void175;176entry:177 %conv61 = zext i32 %x to i64178 br label %loop179 180loop:181 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]182 %c = icmp ule i64 %iv, %M183 br i1 %c, label %then, label %loop.latch184 185then:186 %div18 = sdiv i64 %M, %conv6187 %conv20 = trunc i64 %div18 to i32188 %mul30 = mul i64 %div18, %conv61189 %sub31 = sub i64 %iv, %mul30190 %conv34 = trunc i64 %sub31 to i32191 %mul35 = mul i32 %x, %conv20192 %add36 = add i32 %mul35, %conv34193 %idxprom = sext i32 %add36 to i64194 %gep = getelementptr double, ptr %dst, i64 %idxprom195 store double 0.000000e+00, ptr %gep, align 8196 br label %loop.latch197 198loop.latch:199 %iv.next = add i64 %iv, 1200 %ec = icmp eq i64 %iv.next, %N201 br i1 %ec, label %exit, label %loop202 203exit:204 ret void205}206 207; Test case for https://github.com/llvm/llvm-project/issues/80416.208define void @udiv_urem_feeding_gep(i64 %x, ptr %dst, i64 %N) {209; CHECK-LABEL: define void @udiv_urem_feeding_gep(210; CHECK-SAME: i64 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {211; CHECK-NEXT: [[ENTRY:.*:]]212; CHECK-NEXT: [[MUL_1_I:%.*]] = mul i64 [[X]], [[X]]213; CHECK-NEXT: [[MUL_2_I:%.*]] = mul i64 [[MUL_1_I]], [[X]]214; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1215; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]216; CHECK: [[VECTOR_SCEVCHECK]]:217; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[N]] to i32218; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0219; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i64 [[N]], 4294967295220; CHECK-NEXT: [[TMP4:%.*]] = or i1 [[TMP2]], [[TMP3]]221; CHECK-NEXT: br i1 [[TMP4]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]222; CHECK: [[VECTOR_PH]]:223; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()224; CHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 2225; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()226; CHECK-NEXT: [[TMP11:%.*]] = shl nuw i64 [[TMP10]], 1227; CHECK-NEXT: [[TMP12:%.*]] = sub i64 [[TMP0]], [[TMP11]]228; CHECK-NEXT: [[TMP13:%.*]] = icmp ugt i64 [[TMP0]], [[TMP11]]229; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i64 [[TMP12]], i64 0230; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 0, i64 [[TMP0]])231; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[MUL_2_I]], i64 0232; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer233; CHECK-NEXT: [[TMP15:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()234; CHECK-NEXT: [[TMP17:%.*]] = mul <vscale x 2 x i64> [[TMP15]], splat (i64 1)235; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i64> zeroinitializer, [[TMP17]]236; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP6]], i64 0237; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT3]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer238; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]239; CHECK: [[VECTOR_BODY]]:240; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]241; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 2 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]242; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]243; CHECK-NEXT: [[TMP23:%.*]] = udiv <vscale x 2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]244; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 2 x i64> [[TMP23]], i32 0245; CHECK-NEXT: [[TMP24:%.*]] = urem i64 [[INDEX]], [[MUL_2_I]]246; CHECK-NEXT: [[TMP25:%.*]] = udiv i64 [[TMP24]], [[MUL_1_I]]247; CHECK-NEXT: [[TMP26:%.*]] = urem i64 [[TMP24]], [[MUL_1_I]]248; CHECK-NEXT: [[TMP27:%.*]] = udiv i64 [[TMP26]], [[X]]249; CHECK-NEXT: [[TMP28:%.*]] = urem i64 [[TMP26]], [[X]]250; CHECK-NEXT: [[TMP30:%.*]] = mul i64 [[X]], [[TMP29]]251; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP30]], [[TMP25]]252; CHECK-NEXT: [[TMP32:%.*]] = mul i64 [[TMP31]], [[X]]253; CHECK-NEXT: [[TMP33:%.*]] = add i64 [[TMP32]], [[TMP27]]254; CHECK-NEXT: [[TMP34:%.*]] = mul i64 [[TMP33]], [[X]]255; CHECK-NEXT: [[TMP35:%.*]] = add i64 [[TMP34]], [[TMP28]]256; CHECK-NEXT: [[TMP36:%.*]] = shl i64 [[TMP35]], 32257; CHECK-NEXT: [[TMP37:%.*]] = ashr i64 [[TMP36]], 32258; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP37]]259; CHECK-NEXT: call void @llvm.masked.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP23]], ptr align 4 [[TMP38]], <vscale x 2 x i1> [[ACTIVE_LANE_MASK]])260; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP6]]261; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[INDEX]], i64 [[TMP14]])262; CHECK-NEXT: [[TMP39:%.*]] = extractelement <vscale x 2 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 0263; CHECK-NEXT: [[TMP40:%.*]] = xor i1 [[TMP39]], true264; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT4]]265; CHECK-NEXT: br i1 [[TMP40]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]266; CHECK: [[MIDDLE_BLOCK]]:267; CHECK-NEXT: br label %[[EXIT:.*]]268; CHECK: [[SCALAR_PH]]:269; CHECK-NEXT: br label %[[LOOP:.*]]270; CHECK: [[LOOP]]:271; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]272; CHECK-NEXT: [[DIV_I:%.*]] = udiv i64 [[IV]], [[MUL_2_I]]273; CHECK-NEXT: [[REM_I:%.*]] = urem i64 [[IV]], [[MUL_2_I]]274; CHECK-NEXT: [[DIV_1_I:%.*]] = udiv i64 [[REM_I]], [[MUL_1_I]]275; CHECK-NEXT: [[REM_1_I:%.*]] = urem i64 [[REM_I]], [[MUL_1_I]]276; CHECK-NEXT: [[DIV_2_I:%.*]] = udiv i64 [[REM_1_I]], [[X]]277; CHECK-NEXT: [[REM_2_I:%.*]] = urem i64 [[REM_1_I]], [[X]]278; CHECK-NEXT: [[MUL_I:%.*]] = mul i64 [[X]], [[DIV_I]]279; CHECK-NEXT: [[ADD_I:%.*]] = add i64 [[MUL_I]], [[DIV_1_I]]280; CHECK-NEXT: [[MUL_1_I9:%.*]] = mul i64 [[ADD_I]], [[X]]281; CHECK-NEXT: [[ADD_1_I:%.*]] = add i64 [[MUL_1_I9]], [[DIV_2_I]]282; CHECK-NEXT: [[MUL_2_I11:%.*]] = mul i64 [[ADD_1_I]], [[X]]283; CHECK-NEXT: [[ADD_2_I:%.*]] = add i64 [[MUL_2_I11]], [[REM_2_I]]284; CHECK-NEXT: [[SEXT_I:%.*]] = shl i64 [[ADD_2_I]], 32285; CHECK-NEXT: [[CONV6_I:%.*]] = ashr i64 [[SEXT_I]], 32286; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[DST]], i64 [[CONV6_I]]287; CHECK-NEXT: store i64 [[DIV_I]], ptr [[GEP]], align 4288; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1289; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], [[N]]290; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]291; CHECK: [[EXIT]]:292; CHECK-NEXT: ret void293;294entry:295 %mul.1.i = mul i64 %x, %x296 %mul.2.i = mul i64 %mul.1.i, %x297 br label %loop298 299loop:300 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]301 %div.i = udiv i64 %iv, %mul.2.i302 %rem.i = urem i64 %iv, %mul.2.i303 %div.1.i = udiv i64 %rem.i, %mul.1.i304 %rem.1.i = urem i64 %rem.i, %mul.1.i305 %div.2.i = udiv i64 %rem.1.i, %x306 %rem.2.i = urem i64 %rem.1.i, %x307 %mul.i = mul i64 %x, %div.i308 %add.i = add i64 %mul.i, %div.1.i309 %mul.1.i9 = mul i64 %add.i, %x310 %add.1.i = add i64 %mul.1.i9, %div.2.i311 %mul.2.i11 = mul i64 %add.1.i, %x312 %add.2.i = add i64 %mul.2.i11, %rem.2.i313 %sext.i = shl i64 %add.2.i, 32314 %conv6.i = ashr i64 %sext.i, 32315 %gep = getelementptr i64, ptr %dst, i64 %conv6.i316 store i64 %div.i, ptr %gep, align 4317 %iv.next = add i64 %iv, 1318 %exitcond.not = icmp eq i64 %iv, %N319 br i1 %exitcond.not, label %exit, label %loop320 321exit:322 ret void323}324 325;.326; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}327; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}328; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}329; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}330; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}331; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}332; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}333; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]}334;.335