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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -p loop-vectorize -mcpu=neoverse-v2 -force-vector-width=4 -S %s | FileCheck %s3 4target triple = "aarch64-unknown-linux"5 6; Test case where we visit a VPWidenIntrinsic (for @llvm.fabs) with nnan flags.7; For https://github.com/llvm/llvm-project/issues/125301.8define void @check_widen_intrinsic_with_nnan(ptr noalias %dst.0, ptr noalias %dst.1, ptr noalias %src.1, ptr %src.2) {9; CHECK-LABEL: define void @check_widen_intrinsic_with_nnan(10; CHECK-SAME: ptr noalias [[DST_0:%.*]], ptr noalias [[DST_1:%.*]], ptr noalias [[SRC_1:%.*]], ptr [[SRC_2:%.*]]) #[[ATTR0:[0-9]+]] {11; CHECK-NEXT: [[ENTRY:.*:]]12; CHECK-NEXT: br label %[[VECTOR_PH:.*]]13; CHECK: [[VECTOR_PH]]:14; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]15; CHECK: [[VECTOR_BODY]]:16; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6:.*]] ]17; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, ptr [[SRC_1]], i64 [[INDEX]]18; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x double>, ptr [[TMP1]], align 819; CHECK-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[WIDE_LOAD]])20; CHECK-NEXT: [[TMP4:%.*]] = fcmp olt <4 x double> [[TMP3]], splat (double 1.000000e+00)21; CHECK-NEXT: [[TMP5:%.*]] = xor <4 x i1> [[TMP4]], splat (i1 true)22; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], -123; CHECK-NEXT: [[TMP7:%.*]] = getelementptr double, ptr [[DST_0]], i64 [[TMP6]]24; CHECK-NEXT: call void @llvm.masked.store.v4f64.p0(<4 x double> zeroinitializer, ptr align 8 [[TMP7]], <4 x i1> [[TMP5]])25; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP4]], i32 026; CHECK-NEXT: br i1 [[TMP9]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]27; CHECK: [[PRED_LOAD_IF]]:28; CHECK-NEXT: [[TMP10:%.*]] = load double, ptr [[SRC_2]], align 829; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x double> poison, double [[TMP10]], i32 030; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE]]31; CHECK: [[PRED_LOAD_CONTINUE]]:32; CHECK-NEXT: [[TMP12:%.*]] = phi <4 x double> [ poison, %[[VECTOR_BODY]] ], [ [[TMP11]], %[[PRED_LOAD_IF]] ]33; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i1> [[TMP4]], i32 134; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_LOAD_IF1:.*]], label %[[PRED_LOAD_CONTINUE2:.*]]35; CHECK: [[PRED_LOAD_IF1]]:36; CHECK-NEXT: [[TMP14:%.*]] = load double, ptr [[SRC_2]], align 837; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x double> [[TMP12]], double [[TMP14]], i32 138; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE2]]39; CHECK: [[PRED_LOAD_CONTINUE2]]:40; CHECK-NEXT: [[TMP16:%.*]] = phi <4 x double> [ [[TMP12]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP15]], %[[PRED_LOAD_IF1]] ]41; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i1> [[TMP4]], i32 242; CHECK-NEXT: br i1 [[TMP17]], label %[[PRED_LOAD_IF3:.*]], label %[[PRED_LOAD_CONTINUE4:.*]]43; CHECK: [[PRED_LOAD_IF3]]:44; CHECK-NEXT: [[TMP18:%.*]] = load double, ptr [[SRC_2]], align 845; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x double> [[TMP16]], double [[TMP18]], i32 246; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE4]]47; CHECK: [[PRED_LOAD_CONTINUE4]]:48; CHECK-NEXT: [[TMP20:%.*]] = phi <4 x double> [ [[TMP16]], %[[PRED_LOAD_CONTINUE2]] ], [ [[TMP19]], %[[PRED_LOAD_IF3]] ]49; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i1> [[TMP4]], i32 350; CHECK-NEXT: br i1 [[TMP21]], label %[[PRED_LOAD_IF5:.*]], label %[[PRED_LOAD_CONTINUE6]]51; CHECK: [[PRED_LOAD_IF5]]:52; CHECK-NEXT: [[TMP22:%.*]] = load double, ptr [[SRC_2]], align 853; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x double> [[TMP20]], double [[TMP22]], i32 354; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE6]]55; CHECK: [[PRED_LOAD_CONTINUE6]]:56; CHECK-NEXT: [[TMP24:%.*]] = phi <4 x double> [ [[TMP20]], %[[PRED_LOAD_CONTINUE4]] ], [ [[TMP23]], %[[PRED_LOAD_IF5]] ]57; CHECK-NEXT: call void @llvm.masked.store.v4f64.p0(<4 x double> zeroinitializer, ptr align 8 [[TMP7]], <4 x i1> [[TMP4]])58; CHECK-NEXT: [[TMP28:%.*]] = fcmp oeq <4 x double> [[TMP24]], zeroinitializer59; CHECK-NEXT: [[TMP29:%.*]] = select <4 x i1> [[TMP4]], <4 x i1> [[TMP28]], <4 x i1> zeroinitializer60; CHECK-NEXT: [[TMP30:%.*]] = or <4 x i1> [[TMP5]], [[TMP29]]61; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr [[DST_1]], i64 [[TMP6]]62; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> splat (i32 10), ptr align 4 [[TMP32]], <4 x i1> [[TMP30]])63; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 464; CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100065; CHECK-NEXT: br i1 [[TMP34]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]66; CHECK: [[MIDDLE_BLOCK]]:67; CHECK-NEXT: br label %[[EXIT:.*]]68; CHECK: [[EXIT]]:69; CHECK-NEXT: ret void70;71entry:72 br label %loop.header73 74loop.header:75 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]76 %gep.src.1 = getelementptr inbounds double, ptr %src.1, i64 %iv77 %l.1 = load double, ptr %gep.src.1, align 878 %abs = tail call nnan double @llvm.fabs.f64(double %l.1)79 %c.0 = fcmp olt double %abs, 1.000000e+0080 br i1 %c.0, label %then, label %else81 82then:83 %l.2 = load double, ptr %src.2, align 884 %iv.sub.1 = add nsw i64 %iv, -185 %gep.iv.sub.1 = getelementptr double, ptr %dst.0, i64 %iv.sub.186 store double 0.000000e+00, ptr %gep.iv.sub.1, align 887 %c.1 = fcmp oeq double %l.2, 0.000000e+0088 br i1 %c.1, label %merge, label %loop.latch89 90else:91 %iv.sub.2 = add nsw i64 %iv, -192 %gep.iv.sub.2 = getelementptr double, ptr %dst.0, i64 %iv.sub.293 store double 0.000000e+00, ptr %gep.iv.sub.2, align 894 br label %merge95 96merge:97 %merge.iv = phi i64 [ %iv.sub.2, %else ], [ %iv.sub.1, %then ]98 %gep.dst.1 = getelementptr inbounds i32, ptr %dst.1, i64 %merge.iv99 store i32 10, ptr %gep.dst.1, align 4100 br label %loop.latch101 102loop.latch:103 %iv.next = add nuw nsw i64 %iv, 1104 %exitcond.not = icmp eq i64 %iv.next, 1000105 br i1 %exitcond.not, label %exit, label %loop.header106 107exit:108ret void109}110 111declare double @llvm.fabs.f64(double)112