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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -p loop-vectorize -S %s | FileCheck --check-prefixes=DEFAULT %s3; RUN: opt -p loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -S %s | FileCheck --check-prefixes=PRED %s4 5target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"6target triple = "arm64-apple-macosx14.0.0"7 8define void @iv_casts(ptr %dst, ptr %src, i32 %x, i64 %N) #0 {9; DEFAULT-LABEL: define void @iv_casts(10; DEFAULT-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]], i32 [[X:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {11; DEFAULT-NEXT: [[ITER_CHECK:.*]]:12; DEFAULT-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i6413; DEFAULT-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST]] to i6414; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 115; DEFAULT-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()16; DEFAULT-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 217; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]]18; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]19; DEFAULT: [[VECTOR_MEMCHECK]]:20; DEFAULT-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()21; DEFAULT-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 822; DEFAULT-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 223; DEFAULT-NEXT: [[TMP6:%.*]] = sub i64 [[DST1]], [[SRC2]]24; DEFAULT-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]25; DEFAULT-NEXT: br i1 [[DIFF_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]26; DEFAULT: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:27; DEFAULT-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()28; DEFAULT-NEXT: [[TMP8:%.*]] = shl nuw i64 [[TMP7]], 429; DEFAULT-NEXT: [[MIN_ITERS_CHECK3:%.*]] = icmp ult i64 [[TMP0]], [[TMP8]]30; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK3]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]31; DEFAULT: [[VECTOR_PH]]:32; DEFAULT-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()33; DEFAULT-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 1634; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], [[TMP10]]35; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]36; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x i32> poison, i32 [[X]], i64 037; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer38; DEFAULT-NEXT: [[TMP11:%.*]] = trunc <vscale x 8 x i32> [[BROADCAST_SPLAT]] to <vscale x 8 x i16>39; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]40; DEFAULT: [[VECTOR_BODY]]:41; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]42; DEFAULT-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[INDEX]]43; DEFAULT-NEXT: [[TMP13:%.*]] = call i64 @llvm.vscale.i64()44; DEFAULT-NEXT: [[TMP14:%.*]] = shl nuw i64 [[TMP13]], 345; DEFAULT-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP14]]46; DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x i8>, ptr [[TMP12]], align 147; DEFAULT-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 8 x i8>, ptr [[TMP15]], align 148; DEFAULT-NEXT: [[TMP16:%.*]] = zext <vscale x 8 x i8> [[WIDE_LOAD]] to <vscale x 8 x i16>49; DEFAULT-NEXT: [[TMP17:%.*]] = zext <vscale x 8 x i8> [[WIDE_LOAD4]] to <vscale x 8 x i16>50; DEFAULT-NEXT: [[TMP18:%.*]] = mul <vscale x 8 x i16> [[TMP16]], [[TMP11]]51; DEFAULT-NEXT: [[TMP19:%.*]] = mul <vscale x 8 x i16> [[TMP17]], [[TMP11]]52; DEFAULT-NEXT: [[TMP20:%.*]] = or <vscale x 8 x i16> [[TMP18]], [[TMP16]]53; DEFAULT-NEXT: [[TMP21:%.*]] = or <vscale x 8 x i16> [[TMP19]], [[TMP17]]54; DEFAULT-NEXT: [[TMP22:%.*]] = lshr <vscale x 8 x i16> [[TMP20]], splat (i16 1)55; DEFAULT-NEXT: [[TMP23:%.*]] = lshr <vscale x 8 x i16> [[TMP21]], splat (i16 1)56; DEFAULT-NEXT: [[TMP24:%.*]] = trunc <vscale x 8 x i16> [[TMP22]] to <vscale x 8 x i8>57; DEFAULT-NEXT: [[TMP25:%.*]] = trunc <vscale x 8 x i16> [[TMP23]] to <vscale x 8 x i8>58; DEFAULT-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX]]59; DEFAULT-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()60; DEFAULT-NEXT: [[TMP28:%.*]] = shl nuw i64 [[TMP27]], 361; DEFAULT-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP26]], i64 [[TMP28]]62; DEFAULT-NEXT: store <vscale x 8 x i8> [[TMP24]], ptr [[TMP26]], align 163; DEFAULT-NEXT: store <vscale x 8 x i8> [[TMP25]], ptr [[TMP29]], align 164; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP10]]65; DEFAULT-NEXT: [[TMP30:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]66; DEFAULT-NEXT: br i1 [[TMP30]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]67; DEFAULT: [[MIDDLE_BLOCK]]:68; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]69; DEFAULT-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]70; DEFAULT: [[VEC_EPILOG_ITER_CHECK]]:71; DEFAULT-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], [[TMP2]]72; DEFAULT-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]73; DEFAULT: [[VEC_EPILOG_PH]]:74; DEFAULT-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]75; DEFAULT-NEXT: [[TMP33:%.*]] = call i64 @llvm.vscale.i64()76; DEFAULT-NEXT: [[TMP34:%.*]] = mul nuw i64 [[TMP33]], 477; DEFAULT-NEXT: [[N_MOD_VF5:%.*]] = urem i64 [[TMP0]], [[TMP34]]78; DEFAULT-NEXT: [[N_VEC6:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF5]]79; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT7:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[X]], i64 080; DEFAULT-NEXT: [[BROADCAST_SPLAT8:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT7]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer81; DEFAULT-NEXT: [[TMP35:%.*]] = trunc <vscale x 4 x i32> [[BROADCAST_SPLAT8]] to <vscale x 4 x i16>82; DEFAULT-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]]83; DEFAULT: [[VEC_EPILOG_VECTOR_BODY]]:84; DEFAULT-NEXT: [[INDEX9:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT11:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]85; DEFAULT-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[INDEX9]]86; DEFAULT-NEXT: [[WIDE_LOAD10:%.*]] = load <vscale x 4 x i8>, ptr [[TMP36]], align 187; DEFAULT-NEXT: [[TMP37:%.*]] = zext <vscale x 4 x i8> [[WIDE_LOAD10]] to <vscale x 4 x i16>88; DEFAULT-NEXT: [[TMP38:%.*]] = mul <vscale x 4 x i16> [[TMP37]], [[TMP35]]89; DEFAULT-NEXT: [[TMP39:%.*]] = or <vscale x 4 x i16> [[TMP38]], [[TMP37]]90; DEFAULT-NEXT: [[TMP40:%.*]] = lshr <vscale x 4 x i16> [[TMP39]], splat (i16 1)91; DEFAULT-NEXT: [[TMP41:%.*]] = trunc <vscale x 4 x i16> [[TMP40]] to <vscale x 4 x i8>92; DEFAULT-NEXT: [[TMP42:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX9]]93; DEFAULT-NEXT: store <vscale x 4 x i8> [[TMP41]], ptr [[TMP42]], align 194; DEFAULT-NEXT: [[INDEX_NEXT11]] = add nuw i64 [[INDEX9]], [[TMP34]]95; DEFAULT-NEXT: [[TMP43:%.*]] = icmp eq i64 [[INDEX_NEXT11]], [[N_VEC6]]96; DEFAULT-NEXT: br i1 [[TMP43]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]97; DEFAULT: [[VEC_EPILOG_MIDDLE_BLOCK]]:98; DEFAULT-NEXT: [[CMP_N12:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC6]]99; DEFAULT-NEXT: br i1 [[CMP_N12]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]]100; DEFAULT: [[VEC_EPILOG_SCALAR_PH]]:101; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC6]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MEMCHECK]] ], [ 0, %[[ITER_CHECK]] ]102; DEFAULT-NEXT: br label %[[LOOP:.*]]103; DEFAULT: [[LOOP]]:104; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]105; DEFAULT-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV]]106; DEFAULT-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1107; DEFAULT-NEXT: [[L_EXT:%.*]] = zext i8 [[L]] to i32108; DEFAULT-NEXT: [[MUL:%.*]] = mul i32 [[L_EXT]], [[X]]109; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1110; DEFAULT-NEXT: [[L_EXT_2:%.*]] = zext i8 [[L]] to i32111; DEFAULT-NEXT: [[OR:%.*]] = or i32 [[MUL]], [[L_EXT_2]]112; DEFAULT-NEXT: [[LSHR:%.*]] = lshr i32 [[OR]], 1113; DEFAULT-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR]] to i8114; DEFAULT-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]]115; DEFAULT-NEXT: store i8 [[TRUNC]], ptr [[GEP_DST]], align 1116; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]117; DEFAULT-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]118; DEFAULT: [[EXIT]]:119; DEFAULT-NEXT: ret void120;121; PRED-LABEL: define void @iv_casts(122; PRED-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]], i32 [[X:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {123; PRED-NEXT: [[ENTRY:.*:]]124; PRED-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64125; PRED-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST]] to i64126; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1127; PRED-NEXT: br label %[[VECTOR_MEMCHECK:.*]]128; PRED: [[VECTOR_MEMCHECK]]:129; PRED-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()130; PRED-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 16131; PRED-NEXT: [[TMP3:%.*]] = sub i64 [[DST1]], [[SRC2]]132; PRED-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP3]], [[TMP2]]133; PRED-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]134; PRED: [[VECTOR_PH]]:135; PRED-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()136; PRED-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 16137; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 16 x i32> poison, i32 [[X]], i64 0138; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 16 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer139; PRED-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()140; PRED-NEXT: [[TMP7:%.*]] = shl nuw i64 [[TMP6]], 4141; PRED-NEXT: [[TMP8:%.*]] = sub i64 [[TMP0]], [[TMP7]]142; PRED-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP0]], [[TMP7]]143; PRED-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i64 [[TMP8]], i64 0144; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 [[TMP0]])145; PRED-NEXT: [[TMP11:%.*]] = trunc <vscale x 16 x i32> [[BROADCAST_SPLAT]] to <vscale x 16 x i16>146; PRED-NEXT: br label %[[VECTOR_BODY:.*]]147; PRED: [[VECTOR_BODY]]:148; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]149; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 16 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]150; PRED-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[INDEX]]151; PRED-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr align 1 [[TMP12]], <vscale x 16 x i1> [[ACTIVE_LANE_MASK]], <vscale x 16 x i8> poison)152; PRED-NEXT: [[TMP13:%.*]] = zext <vscale x 16 x i8> [[WIDE_MASKED_LOAD]] to <vscale x 16 x i16>153; PRED-NEXT: [[TMP14:%.*]] = mul <vscale x 16 x i16> [[TMP13]], [[TMP11]]154; PRED-NEXT: [[TMP15:%.*]] = or <vscale x 16 x i16> [[TMP14]], [[TMP13]]155; PRED-NEXT: [[TMP16:%.*]] = lshr <vscale x 16 x i16> [[TMP15]], splat (i16 1)156; PRED-NEXT: [[TMP17:%.*]] = trunc <vscale x 16 x i16> [[TMP16]] to <vscale x 16 x i8>157; PRED-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX]]158; PRED-NEXT: call void @llvm.masked.store.nxv16i8.p0(<vscale x 16 x i8> [[TMP17]], ptr align 1 [[TMP18]], <vscale x 16 x i1> [[ACTIVE_LANE_MASK]])159; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP5]]160; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[INDEX]], i64 [[TMP10]])161; PRED-NEXT: [[TMP19:%.*]] = extractelement <vscale x 16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 0162; PRED-NEXT: [[TMP20:%.*]] = xor i1 [[TMP19]], true163; PRED-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]164; PRED: [[MIDDLE_BLOCK]]:165; PRED-NEXT: br label %[[EXIT:.*]]166; PRED: [[SCALAR_PH]]:167; PRED-NEXT: br label %[[LOOP:.*]]168; PRED: [[LOOP]]:169; PRED-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]170; PRED-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV]]171; PRED-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1172; PRED-NEXT: [[L_EXT:%.*]] = zext i8 [[L]] to i32173; PRED-NEXT: [[MUL:%.*]] = mul i32 [[L_EXT]], [[X]]174; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1175; PRED-NEXT: [[L_EXT_2:%.*]] = zext i8 [[L]] to i32176; PRED-NEXT: [[OR:%.*]] = or i32 [[MUL]], [[L_EXT_2]]177; PRED-NEXT: [[LSHR:%.*]] = lshr i32 [[OR]], 1178; PRED-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR]] to i8179; PRED-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]]180; PRED-NEXT: store i8 [[TRUNC]], ptr [[GEP_DST]], align 1181; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]182; PRED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]183; PRED: [[EXIT]]:184; PRED-NEXT: ret void185;186entry:187 br label %loop188 189loop:190 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]191 %gep.src = getelementptr i8, ptr %src, i64 %iv192 %l = load i8, ptr %gep.src, align 1193 %l.ext = zext i8 %l to i32194 %mul = mul i32 %l.ext, %x195 %iv.next = add i64 %iv, 1196 %l.ext.2 = zext i8 %l to i32197 %or = or i32 %mul, %l.ext.2198 %lshr = lshr i32 %or, 1199 %trunc = trunc i32 %lshr to i8200 %gep.dst = getelementptr i8, ptr %dst, i64 %iv201 store i8 %trunc, ptr %gep.dst, align 1202 %ec = icmp eq i64 %iv, %N203 br i1 %ec, label %exit, label %loop204 205exit:206 ret void207}208 209define void @iv_trunc(i32 %x, ptr %dst, i64 %N) #0 {210; DEFAULT-LABEL: define void @iv_trunc(211; DEFAULT-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {212; DEFAULT-NEXT: [[ENTRY:.*]]:213; DEFAULT-NEXT: [[MUL_X:%.*]] = add i32 [[X]], 1214; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1215; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2216; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]217; DEFAULT: [[VECTOR_SCEVCHECK]]:218; DEFAULT-NEXT: [[TMP1:%.*]] = sub i32 -1, [[X]]219; DEFAULT-NEXT: [[TMP2:%.*]] = icmp slt i32 [[MUL_X]], 0220; DEFAULT-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 [[MUL_X]]221; DEFAULT-NEXT: [[TMP4:%.*]] = trunc i64 [[N]] to i32222; DEFAULT-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP3]], i32 [[TMP4]])223; DEFAULT-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0224; DEFAULT-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1225; DEFAULT-NEXT: [[TMP5:%.*]] = sub i32 0, [[MUL_RESULT]]226; DEFAULT-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP5]], 0227; DEFAULT-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 false228; DEFAULT-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]]229; DEFAULT-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[N]], 4294967295230; DEFAULT-NEXT: [[TMP10:%.*]] = icmp ne i32 [[MUL_X]], 0231; DEFAULT-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]]232; DEFAULT-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]]233; DEFAULT-NEXT: br i1 [[TMP12]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]234; DEFAULT: [[VECTOR_PH]]:235; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2236; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]237; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]238; DEFAULT: [[VECTOR_BODY]]:239; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]240; DEFAULT-NEXT: [[TMP13:%.*]] = trunc i64 [[INDEX]] to i32241; DEFAULT-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], 1242; DEFAULT-NEXT: [[TMP15:%.*]] = mul i32 [[MUL_X]], [[TMP13]]243; DEFAULT-NEXT: [[TMP16:%.*]] = mul i32 [[MUL_X]], [[TMP14]]244; DEFAULT-NEXT: [[TMP17:%.*]] = zext i32 [[TMP15]] to i64245; DEFAULT-NEXT: [[TMP18:%.*]] = zext i32 [[TMP16]] to i64246; DEFAULT-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP17]]247; DEFAULT-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP18]]248; DEFAULT-NEXT: store i32 1, ptr [[TMP19]], align 4249; DEFAULT-NEXT: store i32 1, ptr [[TMP20]], align 4250; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2251; DEFAULT-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]252; DEFAULT-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]253; DEFAULT: [[MIDDLE_BLOCK]]:254; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]255; DEFAULT-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]256; DEFAULT: [[SCALAR_PH]]:257; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]258; DEFAULT-NEXT: br label %[[FOR_BODY:.*]]259; DEFAULT: [[FOR_BODY]]:260; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]261; DEFAULT-NEXT: [[TRUNC_IV:%.*]] = trunc i64 [[IV]] to i32262; DEFAULT-NEXT: [[ADD_I:%.*]] = mul i32 [[MUL_X]], [[TRUNC_IV]]263; DEFAULT-NEXT: [[IV_MUL:%.*]] = zext i32 [[ADD_I]] to i64264; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_MUL]]265; DEFAULT-NEXT: store i32 1, ptr [[GEP]], align 4266; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1267; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]268; DEFAULT-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]269; DEFAULT: [[EXIT]]:270; DEFAULT-NEXT: ret void271;272; PRED-LABEL: define void @iv_trunc(273; PRED-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {274; PRED-NEXT: [[ENTRY:.*]]:275; PRED-NEXT: [[MUL_X:%.*]] = add i32 [[X]], 1276; PRED-NEXT: br label %[[FOR_BODY:.*]]277; PRED: [[FOR_BODY]]:278; PRED-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]279; PRED-NEXT: [[TRUNC_IV:%.*]] = trunc i64 [[IV]] to i32280; PRED-NEXT: [[ADD_I:%.*]] = mul i32 [[MUL_X]], [[TRUNC_IV]]281; PRED-NEXT: [[IV_MUL:%.*]] = zext i32 [[ADD_I]] to i64282; PRED-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_MUL]]283; PRED-NEXT: store i32 1, ptr [[GEP]], align 4284; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1285; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]286; PRED-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[FOR_BODY]]287; PRED: [[EXIT]]:288; PRED-NEXT: ret void289;290entry:291 %mul.x = add i32 %x, 1292 br label %for.body293 294for.body: ; preds = %for.body, %entry295 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]296 %trunc.iv = trunc i64 %iv to i32297 %add.i = mul i32 %mul.x, %trunc.iv298 %iv.mul = zext i32 %add.i to i64299 %gep = getelementptr i32, ptr %dst, i64 %iv.mul300 store i32 1, ptr %gep, align 4301 %iv.next = add i64 %iv, 1302 %ec = icmp eq i64 %iv, %N303 br i1 %ec, label %exit, label %for.body304 305exit:306 ret void307}308 309define void @trunc_ivs_and_store(i32 %x, ptr %dst, i64 %N) #0 {310;311; DEFAULT-LABEL: define void @trunc_ivs_and_store(312; DEFAULT-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {313; DEFAULT-NEXT: [[ENTRY:.*]]:314; DEFAULT-NEXT: [[MUL:%.*]] = mul i32 [[X]], [[X]]315; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1316; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2317; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]318; DEFAULT: [[VECTOR_SCEVCHECK]]:319; DEFAULT-NEXT: [[TMP1:%.*]] = mul i32 [[X]], [[X]]320; DEFAULT-NEXT: [[TMP2:%.*]] = sub i32 0, [[TMP1]]321; DEFAULT-NEXT: [[TMP3:%.*]] = icmp slt i32 [[MUL]], 0322; DEFAULT-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 [[MUL]]323; DEFAULT-NEXT: [[TMP5:%.*]] = trunc i64 [[N]] to i32324; DEFAULT-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP4]], i32 [[TMP5]])325; DEFAULT-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0326; DEFAULT-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1327; DEFAULT-NEXT: [[TMP6:%.*]] = sub i32 0, [[MUL_RESULT]]328; DEFAULT-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], 0329; DEFAULT-NEXT: [[TMP8:%.*]] = select i1 [[TMP3]], i1 [[TMP7]], i1 false330; DEFAULT-NEXT: [[TMP9:%.*]] = or i1 [[TMP8]], [[MUL_OVERFLOW]]331; DEFAULT-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[N]], 4294967295332; DEFAULT-NEXT: [[TMP11:%.*]] = icmp ne i32 [[MUL]], 0333; DEFAULT-NEXT: [[TMP12:%.*]] = and i1 [[TMP10]], [[TMP11]]334; DEFAULT-NEXT: [[TMP13:%.*]] = or i1 [[TMP9]], [[TMP12]]335; DEFAULT-NEXT: br i1 [[TMP13]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]336; DEFAULT: [[VECTOR_PH]]:337; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2338; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]339; DEFAULT-NEXT: [[TMP14:%.*]] = trunc i64 [[N_VEC]] to i32340; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]341; DEFAULT: [[VECTOR_BODY]]:342; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]343; DEFAULT-NEXT: [[OFFSET_IDX:%.*]] = trunc i64 [[INDEX]] to i32344; DEFAULT-NEXT: [[TMP15:%.*]] = add i32 [[OFFSET_IDX]], 1345; DEFAULT-NEXT: [[TMP16:%.*]] = trunc i64 [[INDEX]] to i32346; DEFAULT-NEXT: [[TMP17:%.*]] = add i32 [[TMP16]], 1347; DEFAULT-NEXT: [[TMP18:%.*]] = mul i32 [[MUL]], [[TMP16]]348; DEFAULT-NEXT: [[TMP19:%.*]] = mul i32 [[MUL]], [[TMP17]]349; DEFAULT-NEXT: [[TMP20:%.*]] = zext i32 [[TMP18]] to i64350; DEFAULT-NEXT: [[TMP21:%.*]] = zext i32 [[TMP19]] to i64351; DEFAULT-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP20]]352; DEFAULT-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP21]]353; DEFAULT-NEXT: store i32 [[OFFSET_IDX]], ptr [[TMP22]], align 4354; DEFAULT-NEXT: store i32 [[TMP15]], ptr [[TMP23]], align 4355; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2356; DEFAULT-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]357; DEFAULT-NEXT: br i1 [[TMP24]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]358; DEFAULT: [[MIDDLE_BLOCK]]:359; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]360; DEFAULT-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]361; DEFAULT: [[SCALAR_PH]]:362; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]363; DEFAULT-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i32 [ [[TMP14]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]364; DEFAULT-NEXT: br label %[[LOOP:.*]]365; DEFAULT: [[LOOP]]:366; DEFAULT-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP]] ]367; DEFAULT-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL2]], %[[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP]] ]368; DEFAULT-NEXT: [[IV_1_TRUNC:%.*]] = trunc i64 [[IV_1]] to i32369; DEFAULT-NEXT: [[IV_1_MUL:%.*]] = mul i32 [[MUL]], [[IV_1_TRUNC]]370; DEFAULT-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1371; DEFAULT-NEXT: [[MUL_EXT:%.*]] = zext i32 [[IV_1_MUL]] to i64372; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[MUL_EXT]]373; DEFAULT-NEXT: store i32 [[IV_2]], ptr [[GEP]], align 4374; DEFAULT-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], 1375; DEFAULT-NEXT: [[EXITCOND_3_NOT:%.*]] = icmp eq i64 [[IV_1]], [[N]]376; DEFAULT-NEXT: br i1 [[EXITCOND_3_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]377; DEFAULT: [[EXIT]]:378; DEFAULT-NEXT: ret void379;380; PRED-LABEL: define void @trunc_ivs_and_store(381; PRED-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {382; PRED-NEXT: [[ENTRY:.*]]:383; PRED-NEXT: [[TMP1:%.*]] = mul i32 [[X]], [[X]]384; PRED-NEXT: br label %[[LOOP:.*]]385; PRED: [[LOOP]]:386; PRED-NEXT: [[IV_1:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP]] ]387; PRED-NEXT: [[IV_2:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP]] ]388; PRED-NEXT: [[IV_1_TRUNC:%.*]] = trunc i64 [[IV_1]] to i32389; PRED-NEXT: [[IV_1_MUL:%.*]] = mul i32 [[TMP1]], [[IV_1_TRUNC]]390; PRED-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1391; PRED-NEXT: [[MUL_EXT:%.*]] = zext i32 [[IV_1_MUL]] to i64392; PRED-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[MUL_EXT]]393; PRED-NEXT: store i32 [[IV_2]], ptr [[GEP]], align 4394; PRED-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], 1395; PRED-NEXT: [[EXITCOND_3_NOT:%.*]] = icmp eq i64 [[IV_1]], [[N]]396; PRED-NEXT: br i1 [[EXITCOND_3_NOT]], label %[[EXIT:.*]], label %[[LOOP]]397; PRED: [[EXIT]]:398; PRED-NEXT: ret void399;400entry:401 %mul = mul i32 %x, %x402 br label %loop403 404loop:405 %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ]406 %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ]407 %iv.1.trunc = trunc i64 %iv.1 to i32408 %iv.1.mul = mul i32 %mul, %iv.1.trunc409 %iv.2.next = add i32 %iv.2, 1410 %mul.ext = zext i32 %iv.1.mul to i64411 %gep = getelementptr i32, ptr %dst, i64 %mul.ext412 store i32 %iv.2, ptr %gep, align 4413 %iv.1.next = add i64 %iv.1, 1414 %exitcond.3.not = icmp eq i64 %iv.1, %N415 br i1 %exitcond.3.not, label %exit, label %loop416 417exit:418 ret void419}420 421define void @ivs_trunc_and_ext(i32 %x, ptr %dst, i64 %N) #0 {422; DEFAULT-LABEL: define void @ivs_trunc_and_ext(423; DEFAULT-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {424; DEFAULT-NEXT: [[ENTRY:.*]]:425; DEFAULT-NEXT: [[ADD:%.*]] = add i32 [[X]], 1426; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1427; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2428; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]429; DEFAULT: [[VECTOR_SCEVCHECK]]:430; DEFAULT-NEXT: [[TMP1:%.*]] = sub i32 -1, [[X]]431; DEFAULT-NEXT: [[TMP2:%.*]] = icmp slt i32 [[ADD]], 0432; DEFAULT-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 [[ADD]]433; DEFAULT-NEXT: [[TMP4:%.*]] = trunc i64 [[N]] to i32434; DEFAULT-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP3]], i32 [[TMP4]])435; DEFAULT-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0436; DEFAULT-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1437; DEFAULT-NEXT: [[TMP5:%.*]] = sub i32 0, [[MUL_RESULT]]438; DEFAULT-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP5]], 0439; DEFAULT-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 false440; DEFAULT-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]]441; DEFAULT-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[N]], 4294967295442; DEFAULT-NEXT: [[TMP10:%.*]] = icmp ne i32 [[ADD]], 0443; DEFAULT-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]]444; DEFAULT-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]]445; DEFAULT-NEXT: br i1 [[TMP12]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]446; DEFAULT: [[VECTOR_PH]]:447; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2448; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]449; DEFAULT-NEXT: [[TMP13:%.*]] = trunc i64 [[N_VEC]] to i32450; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]451; DEFAULT: [[VECTOR_BODY]]:452; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]453; DEFAULT-NEXT: [[OFFSET_IDX:%.*]] = trunc i64 [[INDEX]] to i32454; DEFAULT-NEXT: [[TMP14:%.*]] = add i32 [[OFFSET_IDX]], 1455; DEFAULT-NEXT: [[TMP15:%.*]] = trunc i64 [[INDEX]] to i32456; DEFAULT-NEXT: [[TMP16:%.*]] = add i32 [[TMP15]], 1457; DEFAULT-NEXT: [[TMP17:%.*]] = mul i32 [[ADD]], [[TMP15]]458; DEFAULT-NEXT: [[TMP18:%.*]] = mul i32 [[ADD]], [[TMP16]]459; DEFAULT-NEXT: [[TMP19:%.*]] = zext i32 [[TMP17]] to i64460; DEFAULT-NEXT: [[TMP20:%.*]] = zext i32 [[TMP18]] to i64461; DEFAULT-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP19]]462; DEFAULT-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP20]]463; DEFAULT-NEXT: store i32 [[OFFSET_IDX]], ptr [[TMP21]], align 4464; DEFAULT-NEXT: store i32 [[TMP14]], ptr [[TMP22]], align 4465; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2466; DEFAULT-NEXT: [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]467; DEFAULT-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]468; DEFAULT: [[MIDDLE_BLOCK]]:469; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]470; DEFAULT-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]471; DEFAULT: [[SCALAR_PH]]:472; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]473; DEFAULT-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ [[TMP13]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]474; DEFAULT-NEXT: br label %[[LOOP:.*]]475; DEFAULT: [[LOOP]]:476; DEFAULT-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP]] ]477; DEFAULT-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP]] ]478; DEFAULT-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV_1]] to i32479; DEFAULT-NEXT: [[IV_MUL:%.*]] = mul i32 [[ADD]], [[IV_TRUNC]]480; DEFAULT-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1481; DEFAULT-NEXT: [[EXT:%.*]] = zext i32 [[IV_MUL]] to i64482; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[EXT]]483; DEFAULT-NEXT: store i32 [[IV_2]], ptr [[GEP]], align 4484; DEFAULT-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], 1485; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_1]], [[N]]486; DEFAULT-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]487; DEFAULT: [[EXIT]]:488; DEFAULT-NEXT: ret void489;490; PRED-LABEL: define void @ivs_trunc_and_ext(491; PRED-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {492; PRED-NEXT: [[ENTRY:.*]]:493; PRED-NEXT: [[ADD:%.*]] = add i32 [[X]], 1494; PRED-NEXT: br label %[[LOOP:.*]]495; PRED: [[LOOP]]:496; PRED-NEXT: [[IV_1:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP]] ]497; PRED-NEXT: [[IV_2:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP]] ]498; PRED-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV_1]] to i32499; PRED-NEXT: [[IV_MUL:%.*]] = mul i32 [[ADD]], [[IV_TRUNC]]500; PRED-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1501; PRED-NEXT: [[EXT:%.*]] = zext i32 [[IV_MUL]] to i64502; PRED-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[EXT]]503; PRED-NEXT: store i32 [[IV_2]], ptr [[GEP]], align 4504; PRED-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], 1505; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_1]], [[N]]506; PRED-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]507; PRED: [[EXIT]]:508; PRED-NEXT: ret void509;510 511entry:512 %add = add i32 %x, 1513 br label %loop514 515loop:516 %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ]517 %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ]518 %iv.trunc = trunc i64 %iv.1 to i32519 %iv.mul = mul i32 %add, %iv.trunc520 %iv.2.next = add i32 %iv.2, 1521 %ext = zext i32 %iv.mul to i64522 %gep = getelementptr i32, ptr %dst, i64 %ext523 store i32 %iv.2, ptr %gep, align 4524 %iv.1.next = add i64 %iv.1, 1525 %ec = icmp eq i64 %iv.1, %N526 br i1 %ec, label %exit, label %loop527 528exit:529 ret void530}531 532define void @exit_cond_zext_iv(ptr %dst, i64 %N) {533; DEFAULT-LABEL: define void @exit_cond_zext_iv(534; DEFAULT-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) {535; DEFAULT-NEXT: [[ENTRY:.*]]:536; DEFAULT-NEXT: [[UMAX1:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)537; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX1]], 2538; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]539; DEFAULT: [[VECTOR_SCEVCHECK]]:540; DEFAULT-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)541; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], -1542; DEFAULT-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32543; DEFAULT-NEXT: [[TMP2:%.*]] = add i32 1, [[TMP1]]544; DEFAULT-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 1545; DEFAULT-NEXT: [[TMP4:%.*]] = icmp ugt i64 [[TMP0]], 4294967295546; DEFAULT-NEXT: [[TMP5:%.*]] = or i1 [[TMP3]], [[TMP4]]547; DEFAULT-NEXT: br i1 [[TMP5]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]548; DEFAULT: [[VECTOR_PH]]:549; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX1]], 2550; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX1]], [[N_MOD_VF]]551; DEFAULT-NEXT: [[TMP6:%.*]] = trunc i64 [[N_VEC]] to i32552; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]553; DEFAULT: [[VECTOR_BODY]]:554; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]555; DEFAULT-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 1556; DEFAULT-NEXT: [[TMP8:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[INDEX]], i32 2557; DEFAULT-NEXT: [[TMP9:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[TMP7]], i32 2558; DEFAULT-NEXT: store i32 0, ptr [[TMP8]], align 8559; DEFAULT-NEXT: store i32 0, ptr [[TMP9]], align 8560; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2561; DEFAULT-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]562; DEFAULT-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]563; DEFAULT: [[MIDDLE_BLOCK]]:564; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX1]], [[N_VEC]]565; DEFAULT-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]566; DEFAULT: [[SCALAR_PH]]:567; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]568; DEFAULT-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]569; DEFAULT-NEXT: br label %[[LOOP:.*]]570; DEFAULT: [[LOOP]]:571; DEFAULT-NEXT: [[IV_1:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP]] ]572; DEFAULT-NEXT: [[IV_CONV:%.*]] = phi i64 [ [[BC_RESUME_VAL2]], %[[SCALAR_PH]] ], [ [[IV_EXT:%.*]], %[[LOOP]] ]573; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[IV_CONV]], i32 2574; DEFAULT-NEXT: store i32 0, ptr [[GEP]], align 8575; DEFAULT-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1576; DEFAULT-NEXT: [[IV_EXT]] = zext i32 [[IV_1_NEXT]] to i64577; DEFAULT-NEXT: [[C:%.*]] = icmp ult i64 [[IV_EXT]], [[N]]578; DEFAULT-NEXT: br i1 [[C]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP13:![0-9]+]]579; DEFAULT: [[EXIT]]:580; DEFAULT-NEXT: ret void581;582; PRED-LABEL: define void @exit_cond_zext_iv(583; PRED-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) {584; PRED-NEXT: [[ENTRY:.*:]]585; PRED-NEXT: [[UMAX1:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)586; PRED-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]587; PRED: [[VECTOR_SCEVCHECK]]:588; PRED-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)589; PRED-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], -1590; PRED-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32591; PRED-NEXT: [[TMP2:%.*]] = add i32 1, [[TMP1]]592; PRED-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 1593; PRED-NEXT: [[TMP4:%.*]] = icmp ugt i64 [[TMP0]], 4294967295594; PRED-NEXT: [[TMP5:%.*]] = or i1 [[TMP3]], [[TMP4]]595; PRED-NEXT: br i1 [[TMP5]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]596; PRED: [[VECTOR_PH]]:597; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 [[UMAX1]], 1598; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 2599; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]600; PRED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = sub i64 [[UMAX1]], 1601; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0602; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer603; PRED-NEXT: br label %[[VECTOR_BODY:.*]]604; PRED: [[VECTOR_BODY]]:605; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE5:.*]] ]606; PRED-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <2 x i64> poison, i64 [[INDEX]], i64 0607; PRED-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT2]], <2 x i64> poison, <2 x i32> zeroinitializer608; PRED-NEXT: [[VEC_IV:%.*]] = add <2 x i64> [[BROADCAST_SPLAT3]], <i64 0, i64 1>609; PRED-NEXT: [[TMP6:%.*]] = icmp ule <2 x i64> [[VEC_IV]], [[BROADCAST_SPLAT]]610; PRED-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP6]], i32 0611; PRED-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]612; PRED: [[PRED_STORE_IF]]:613; PRED-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 0614; PRED-NEXT: [[TMP9:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[TMP8]], i32 2615; PRED-NEXT: store i32 0, ptr [[TMP9]], align 8616; PRED-NEXT: br label %[[PRED_STORE_CONTINUE]]617; PRED: [[PRED_STORE_CONTINUE]]:618; PRED-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP6]], i32 1619; PRED-NEXT: br i1 [[TMP10]], label %[[PRED_STORE_IF4:.*]], label %[[PRED_STORE_CONTINUE5]]620; PRED: [[PRED_STORE_IF4]]:621; PRED-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 1622; PRED-NEXT: [[TMP12:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[TMP11]], i32 2623; PRED-NEXT: store i32 0, ptr [[TMP12]], align 8624; PRED-NEXT: br label %[[PRED_STORE_CONTINUE5]]625; PRED: [[PRED_STORE_CONTINUE5]]:626; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 2627; PRED-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]628; PRED-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]629; PRED: [[MIDDLE_BLOCK]]:630; PRED-NEXT: br label %[[EXIT:.*]]631; PRED: [[SCALAR_PH]]:632; PRED-NEXT: br label %[[LOOP:.*]]633; PRED: [[LOOP]]:634; PRED-NEXT: [[IV_1:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP]] ]635; PRED-NEXT: [[IV_CONV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_EXT:%.*]], %[[LOOP]] ]636; PRED-NEXT: [[GEP:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[IV_CONV]], i32 2637; PRED-NEXT: store i32 0, ptr [[GEP]], align 8638; PRED-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1639; PRED-NEXT: [[IV_EXT]] = zext i32 [[IV_1_NEXT]] to i64640; PRED-NEXT: [[C:%.*]] = icmp ult i64 [[IV_EXT]], [[N]]641; PRED-NEXT: br i1 [[C]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP5:![0-9]+]]642; PRED: [[EXIT]]:643; PRED-NEXT: ret void644;645entry:646 br label %loop647 648loop:649 %iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop ]650 %iv.conv = phi i64 [ 0, %entry ], [ %iv.ext, %loop ]651 %gep = getelementptr {[100 x i32], i32, i32}, ptr %dst, i64 %iv.conv, i32 2652 store i32 0, ptr %gep, align 8653 %iv.1.next = add i32 %iv.1, 1654 %iv.ext = zext i32 %iv.1.next to i64655 %c = icmp ult i64 %iv.ext, %N656 br i1 %c, label %loop, label %exit657 658exit:659 ret void660}661 662attributes #0 = { "target-features"="+sve" }663 664