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1; REQUIRES: asserts2; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -debug-only=loop-vectorize -disable-output -force-vector-interleave=1 -enable-epilogue-vectorization=false -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-REGS-VP3; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -debug-only=loop-vectorize -disable-output -force-target-num-vector-regs=1 -force-vector-interleave=1 -enable-epilogue-vectorization=false -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NOREGS-VP4 5target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"6target triple = "aarch64-none-unknown-elf"7 8define i32 @dotp(ptr %a, ptr %b) #0 {9; CHECK-REGS-VP: LV: Selecting VF: vscale x 16.10;11; CHECK-NOREGS-VP: LV(REG): Not considering vector loop of width vscale x 8 because it uses too many registers12; CHECK-NOREGS-VP: LV(REG): Not considering vector loop of width vscale x 16 because it uses too many registers13; CHECK-NOREGS-VP: LV: Selecting VF: vscale x 4.14entry:15 br label %for.body16 17for.body: ; preds = %for.body, %entry18 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]19 %accum = phi i32 [ 0, %entry ], [ %add, %for.body ]20 %gep.a = getelementptr i8, ptr %a, i64 %iv21 %load.a = load i8, ptr %gep.a, align 122 %ext.a = zext i8 %load.a to i3223 %gep.b = getelementptr i8, ptr %b, i64 %iv24 %load.b = load i8, ptr %gep.b, align 125 %ext.b = zext i8 %load.b to i3226 %mul = mul i32 %ext.b, %ext.a27 %sub = sub i32 0, %mul28 %add = add i32 %accum, %sub29 %iv.next = add i64 %iv, 130 %exitcond.not = icmp eq i64 %iv.next, 102431 br i1 %exitcond.not, label %for.exit, label %for.body32 33for.exit: ; preds = %for.body34 ret i32 %add35}36 37attributes #0 = { vscale_range(1,16) "target-features"="+sve" }38