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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 62; RUN: opt --mattr=+neon,+dotprod -passes=loop-vectorize -force-vector-interleave=1 -enable-epilogue-vectorization=false -S %s | FileCheck %s3 4target triple = "arm64-apple-macosx"5 6define i32 @red_extended_add_incomplete_chain(ptr %start, ptr %end, i32 %offset) {7; CHECK-LABEL: define i32 @red_extended_add_incomplete_chain(8; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: [[ENTRY:.*]]:10; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i6411; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i6412; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 113; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]14; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 1615; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]16; CHECK: [[VECTOR_PH]]:17; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 1618; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]]19; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[START]], i64 [[N_VEC]]20; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[OFFSET]], i64 021; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i32> [[BROADCAST_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer22; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]23; CHECK: [[VECTOR_BODY]]:24; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]25; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <16 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]26; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[INDEX]]27; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[NEXT_GEP]], align 128; CHECK-NEXT: [[TMP3:%.*]] = zext <16 x i8> [[WIDE_LOAD]] to <16 x i32>29; CHECK-NEXT: [[TMP4:%.*]] = add <16 x i32> [[VEC_PHI]], [[TMP3]]30; CHECK-NEXT: [[TMP5]] = add <16 x i32> [[TMP4]], [[BROADCAST_SPLAT]]31; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1632; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]33; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]34; CHECK: [[MIDDLE_BLOCK]]:35; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP5]])36; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]]37; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]38; CHECK: [[SCALAR_PH]]:39; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]40; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]41; CHECK-NEXT: br label %[[LOOP:.*]]42; CHECK: [[LOOP]]:43; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[GEP_IV_NEXT:%.*]], %[[LOOP]] ]44; CHECK-NEXT: [[RED:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[RED_NEXT:%.*]], %[[LOOP]] ]45; CHECK-NEXT: [[L:%.*]] = load i8, ptr [[PTR_IV]], align 146; CHECK-NEXT: [[L_EXT:%.*]] = zext i8 [[L]] to i3247; CHECK-NEXT: [[ADD:%.*]] = add i32 [[RED]], [[L_EXT]]48; CHECK-NEXT: [[RED_NEXT]] = add i32 [[ADD]], [[OFFSET]]49; CHECK-NEXT: [[GEP_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 150; CHECK-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV]], [[END]]51; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]52; CHECK: [[EXIT]]:53; CHECK-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i32 [ [[RED_NEXT]], %[[LOOP]] ], [ [[TMP7]], %[[MIDDLE_BLOCK]] ]54; CHECK-NEXT: ret i32 [[RED_NEXT_LCSSA]]55;56entry:57 br label %loop58 59loop:60 %ptr.iv = phi ptr [ %start, %entry ], [ %gep.iv.next, %loop ]61 %red = phi i32 [ 0, %entry ], [ %red.next, %loop ]62 %l = load i8, ptr %ptr.iv, align 163 %l.ext = zext i8 %l to i3264 %add = add i32 %red, %l.ext65 %red.next = add i32 %add, %offset66 %gep.iv.next = getelementptr i8, ptr %ptr.iv, i64 167 %ec = icmp eq ptr %ptr.iv, %end68 br i1 %ec, label %exit, label %loop69 70exit:71 ret i32 %red.next72}73 74define i16 @test_incomplete_chain_without_mul(ptr noalias %dst, ptr %A, ptr %B) #0 {75; CHECK-LABEL: define i16 @test_incomplete_chain_without_mul(76; CHECK-SAME: ptr noalias [[DST:%.*]], ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR1:[0-9]+]] {77; CHECK-NEXT: [[ENTRY:.*:]]78; CHECK-NEXT: br label %[[VECTOR_PH:.*]]79; CHECK: [[VECTOR_PH]]:80; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]81; CHECK: [[VECTOR_BODY]]:82; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]83; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <16 x i16> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]84; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 185; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i8> poison, i8 [[TMP0]], i64 086; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i8> [[BROADCAST_SPLATINSERT]], <16 x i8> poison, <16 x i32> zeroinitializer87; CHECK-NEXT: [[TMP1:%.*]] = zext <16 x i8> [[BROADCAST_SPLAT]] to <16 x i16>88; CHECK-NEXT: [[TMP2:%.*]] = extractelement <16 x i16> [[TMP1]], i32 1589; CHECK-NEXT: store i16 [[TMP2]], ptr [[DST]], align 290; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[B]], align 191; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <16 x i8> poison, i8 [[TMP3]], i64 092; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <16 x i8> [[BROADCAST_SPLATINSERT1]], <16 x i8> poison, <16 x i32> zeroinitializer93; CHECK-NEXT: [[TMP4:%.*]] = zext <16 x i8> [[BROADCAST_SPLAT2]] to <16 x i16>94; CHECK-NEXT: [[TMP5:%.*]] = add <16 x i16> [[VEC_PHI]], [[TMP4]]95; CHECK-NEXT: [[TMP6:%.*]] = add <16 x i16> [[TMP5]], [[TMP1]]96; CHECK-NEXT: [[TMP7]] = add <16 x i16> [[TMP6]], [[TMP4]]97; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1698; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 102499; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]100; CHECK: [[MIDDLE_BLOCK]]:101; CHECK-NEXT: [[TMP9:%.*]] = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> [[TMP7]])102; CHECK-NEXT: br label %[[EXIT:.*]]103; CHECK: [[EXIT]]:104; CHECK-NEXT: ret i16 [[TMP9]]105;106entry:107 br label %loop108 109loop:110 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]111 %red = phi i16 [ 0, %entry ], [ %red.next, %loop ]112 %l.a = load i8, ptr %A, align 1113 %a.ext = zext i8 %l.a to i16114 store i16 %a.ext, ptr %dst, align 2115 %l.b = load i8, ptr %B, align 1116 %b.ext = zext i8 %l.b to i16117 %add = add i16 %red, %b.ext118 %add.1 = add i16 %add, %a.ext119 %red.next = add i16 %add.1, %b.ext120 %iv.next = add i64 %iv, 1121 %ec = icmp ult i64 %iv.next, 1024122 br i1 %ec, label %loop, label %exit123 124exit:125 ret i16 %red.next126}127 128define void @chained_sext_adds(ptr noalias %src, ptr noalias %dst) #0 {129; CHECK-NEON-LABEL: define void @chained_sext_adds(130; CHECK-NEON-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR1]] {131; CHECK-NEON-NEXT: [[ENTRY:.*:]]132; CHECK-NEON-NEXT: br label %[[VECTOR_PH:.*]]133; CHECK-NEON: [[VECTOR_PH]]:134; CHECK-NEON-NEXT: br label %[[VECTOR_BODY:.*]]135; CHECK-NEON: [[VECTOR_BODY]]:136; CHECK-NEON-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]137; CHECK-NEON-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE1:%.*]], %[[VECTOR_BODY]] ]138; CHECK-NEON-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[INDEX]]139; CHECK-NEON-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[TMP0]], align 1140; CHECK-NEON-NEXT: [[TMP1:%.*]] = sext <16 x i8> [[WIDE_LOAD]] to <16 x i32>141; CHECK-NEON-NEXT: [[PARTIAL_REDUCE:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[VEC_PHI]], <16 x i32> [[TMP1]])142; CHECK-NEON-NEXT: [[PARTIAL_REDUCE1]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[PARTIAL_REDUCE]], <16 x i32> [[TMP1]])143; CHECK-NEON-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16144; CHECK-NEON-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 992145; CHECK-NEON-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]146; CHECK-NEON: [[MIDDLE_BLOCK]]:147; CHECK-NEON-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[PARTIAL_REDUCE1]])148; CHECK-NEON-NEXT: store i32 [[TMP3]], ptr [[DST]], align 4149; CHECK-NEON-NEXT: br label %[[SCALAR_PH:.*]]150; CHECK-NEON: [[SCALAR_PH]]:151; CHECK-NEON-NEXT: br label %[[LOOP:.*]]152; CHECK-NEON: [[EXIT:.*]]:153; CHECK-NEON-NEXT: ret void154; CHECK-NEON: [[LOOP]]:155; CHECK-NEON-NEXT: [[IV:%.*]] = phi i64 [ 992, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]156; CHECK-NEON-NEXT: [[RED:%.*]] = phi i32 [ [[TMP3]], %[[SCALAR_PH]] ], [ [[ADD_1:%.*]], %[[LOOP]] ]157; CHECK-NEON-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV]]158; CHECK-NEON-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1159; CHECK-NEON-NEXT: [[CONV8:%.*]] = sext i8 [[L]] to i32160; CHECK-NEON-NEXT: [[ADD:%.*]] = add i32 [[RED]], [[CONV8]]161; CHECK-NEON-NEXT: [[CONV8_1:%.*]] = sext i8 [[L]] to i32162; CHECK-NEON-NEXT: [[ADD_1]] = add i32 [[ADD]], [[CONV8_1]]163; CHECK-NEON-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]]164; CHECK-NEON-NEXT: store i32 [[ADD_1]], ptr [[DST]], align 4165; CHECK-NEON-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1166; CHECK-NEON-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], 1000167; CHECK-NEON-NEXT: br i1 [[EXITCOND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]168;169; CHECK-LABEL: define void @chained_sext_adds(170; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR1]] {171; CHECK-NEXT: [[ENTRY:.*]]:172; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()173; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2174; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1000, [[TMP1]]175; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]176; CHECK: [[VECTOR_PH]]:177; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()178; CHECK-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4179; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 1000, [[TMP3]]180; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 1000, [[N_MOD_VF]]181; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]182; CHECK: [[VECTOR_BODY]]:183; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]184; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]185; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[INDEX]]186; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i8>, ptr [[TMP4]], align 1187; CHECK-NEXT: [[TMP5:%.*]] = sext <vscale x 4 x i8> [[WIDE_LOAD]] to <vscale x 4 x i32>188; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 4 x i32> [[VEC_PHI]], [[TMP5]]189; CHECK-NEXT: [[TMP7]] = add <vscale x 4 x i32> [[TMP6]], [[TMP5]]190; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]191; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]192; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]193; CHECK: [[MIDDLE_BLOCK]]:194; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[TMP7]])195; CHECK-NEXT: store i32 [[TMP9]], ptr [[DST]], align 4196; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1000, [[N_VEC]]197; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]198; CHECK: [[SCALAR_PH]]:199; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]200; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]201; CHECK-NEXT: br label %[[LOOP:.*]]202; CHECK: [[EXIT]]:203; CHECK-NEXT: ret void204; CHECK: [[LOOP]]:205; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]206; CHECK-NEXT: [[RED:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD_1:%.*]], %[[LOOP]] ]207; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV]]208; CHECK-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1209; CHECK-NEXT: [[CONV8:%.*]] = sext i8 [[L]] to i32210; CHECK-NEXT: [[ADD:%.*]] = add i32 [[RED]], [[CONV8]]211; CHECK-NEXT: [[CONV8_1:%.*]] = sext i8 [[L]] to i32212; CHECK-NEXT: [[ADD_1]] = add i32 [[ADD]], [[CONV8_1]]213; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]]214; CHECK-NEXT: store i32 [[ADD_1]], ptr [[DST]], align 4215; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1216; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], 1000217; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]218;219entry:220 br label %loop221 222exit: ; preds = %loop223 ret void224 225loop: ; preds = %loop, %entry226 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]227 %red = phi i32 [ 0, %entry ], [ %add.1, %loop ]228 %gep.src = getelementptr i8, ptr %src, i64 %iv229 %l = load i8, ptr %gep.src, align 1230 %conv8 = sext i8 %l to i32231 %add = add i32 %red, %conv8232 %conv8.1 = sext i8 %l to i32233 %add.1 = add i32 %add, %conv8.1234 %gep.dst = getelementptr i8, ptr %dst, i64 %iv235 store i32 %add.1, ptr %dst, align 4236 %iv.next = add i64 %iv, 1237 %exitcond = icmp eq i64 %iv.next, 1000238 br i1 %exitcond, label %exit, label %loop239}240 241attributes #0 = { "target-cpu"="grace" }242