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1; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 \2; RUN: -prefer-predicate-over-epilogue=scalar-epilogue -S -o - < %s | FileCheck %s3; RUN: opt -mattr=+sve -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 \4; RUN: -prefer-predicate-over-epilogue=scalar-epilogue -S -o - < %s | FileCheck %s5 6target triple = "aarch64-unknown-linux-gnu"7 8; This test is defending against a bug that appeared when we have a target9; configuration where masked loads/stores are legal -- e.g. AArch64 with SVE.10; Predication would not be applied during interleaving, enabling the11; possibility of superfluous loads/stores which could result in miscompiles.12; This test checks that, when we disable vectorisation and force interleaving,13; stores are predicated properly.14;15; This is _not_ an SVE-specific test. The same bug could manifest on any16; architecture with masked loads/stores, but we use SVE for testing purposes17; here.18 19define void @foo(ptr %data1, ptr %data2) {20; CHECK-LABEL: @foo(21; CHECK: vector.body:22; CHECK: br i1 {{%.*}}, label %pred.store.if, label %pred.store.continue23; CHECK: pred.store.if:24; CHECK-NEXT: store i32 {{%.*}}, ptr {{%.*}}25; CHECK-NEXT: br label %pred.store.continue26; CHECK: pred.store.continue:27; CHECK-NEXT: br i1 {{%.*}}, label %pred.store.if1, label %pred.store.continue228; CHECK: pred.store.if1:29; CHECK-NEXT: store i32 {{%.*}}, ptr {{%.*}}30; CHECK-NEXT: br label %pred.store.continue231; CHECK: pred.store.continue2:32 33entry:34 br label %while.body35 36while.body:37 %i = phi i64 [ 1023, %entry ], [ %i.next, %if.end ]38 %arrayidx = getelementptr inbounds i32, ptr %data1, i64 %i39 %ld = load i32, ptr %arrayidx, align 440 %cmp = icmp sgt i32 %ld, %ld41 br i1 %cmp, label %if.then, label %if.end42 43if.then:44 store i32 %ld, ptr %arrayidx, align 445 br label %if.end46 47if.end:48 %i.next = add nsw i64 %i, -149 %tobool.not = icmp eq i64 %i, 050 br i1 %tobool.not, label %while.end, label %while.body51 52while.end:53 ret void54}55