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1; RUN: opt -passes=loop-vectorize,dce,instcombine -mtriple aarch64-linux-gnu -mattr=+sve \2; RUN: -prefer-predicate-over-epilogue=scalar-epilogue < %s -S | FileCheck %s3 4 5target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"6target triple = "aarch64-unknown-linux-gnu"7 8define void @cmpsel_i32(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, i64 %n) {9; CHECK-LABEL: @cmpsel_i32(10; CHECK-NEXT: entry:11; CHECK: vector.body:12; CHECK: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr {{.*}}, align 413; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <vscale x 4 x i32> [[WIDE_LOAD]], zeroinitializer14; CHECK-NEXT: [[TMP2:%.*]] = select <vscale x 4 x i1> [[TMP1]], <vscale x 4 x i32> splat (i32 2), <vscale x 4 x i32> splat (i32 10)15; CHECK: store <vscale x 4 x i32> [[TMP2]], ptr {{.*}}, align 416;17entry:18 br label %for.body19 20for.body: ; preds = %entry, %for.body21 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]22 %arrayidx = getelementptr inbounds i32, ptr %b, i64 %indvars.iv23 %0 = load i32, ptr %arrayidx, align 424 %tobool.not = icmp eq i32 %0, 025 %cond = select i1 %tobool.not, i32 2, i32 1026 %arrayidx2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv27 store i32 %cond, ptr %arrayidx2, align 428 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 129 %exitcond.not = icmp eq i64 %indvars.iv.next, %n30 br i1 %exitcond.not, label %for.end.loopexit, label %for.body, !llvm.loop !031 32for.end.loopexit: ; preds = %for.body33 br label %for.end34 35for.end: ; preds = %for.end.loopexit, %entry36 ret void37}38 39define void @cmpsel_f32(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, i64 %n) {40; CHECK-LABEL: @cmpsel_f32(41; CHECK-NEXT: entry:42; CHECK: vector.body:43; CHECK: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr {{.*}}, align 444; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt <vscale x 4 x float> [[WIDE_LOAD]], splat (float 3.000000e+00)45; CHECK-NEXT: [[TMP2:%.*]] = select <vscale x 4 x i1> [[TMP1]], <vscale x 4 x float> splat (float 1.000000e+01), <vscale x 4 x float> splat (float 2.000000e+00)46; CHECK: store <vscale x 4 x float> [[TMP2]], ptr {{.*}}, align 447 48entry:49 br label %for.body50 51for.body: ; preds = %entry, %for.body52 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]53 %arrayidx = getelementptr inbounds float, ptr %b, i64 %indvars.iv54 %0 = load float, ptr %arrayidx, align 455 %cmp1 = fcmp ogt float %0, 3.000000e+0056 %conv = select i1 %cmp1, float 1.000000e+01, float 2.000000e+0057 %arrayidx3 = getelementptr inbounds float, ptr %a, i64 %indvars.iv58 store float %conv, ptr %arrayidx3, align 459 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 160 %exitcond.not = icmp eq i64 %indvars.iv.next, %n61 br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !062 63for.end: ; preds = %for.body, %entry64 ret void65}66 67define void @fneg_f32(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, i64 %n) {68; CHECK-LABEL: @fneg_f32(69; CHECK-NEXT: entry:70; CHECK: vector.body:71; CHECK: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr {{.*}}, align 472; CHECK-NEXT: [[TMP1:%.*]] = fneg <vscale x 4 x float> [[WIDE_LOAD]]73; CHECK: store <vscale x 4 x float> [[TMP1]], ptr {{.*}}, align 474 75entry:76 br label %for.body77 78for.body: ; preds = %entry, %for.body79 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]80 %arrayidx = getelementptr inbounds float, ptr %b, i64 %indvars.iv81 %0 = load float, ptr %arrayidx, align 482 %fneg = fneg float %083 %arrayidx3 = getelementptr inbounds float, ptr %a, i64 %indvars.iv84 store float %fneg, ptr %arrayidx3, align 485 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 186 %exitcond.not = icmp eq i64 %indvars.iv.next, %n87 br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !088 89for.end: ; preds = %for.body, %entry90 ret void91}92 93!0 = distinct !{!0, !1, !2, !3, !4, !5}94!1 = !{!"llvm.loop.mustprogress"}95!2 = !{!"llvm.loop.vectorize.width", i32 4}96!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}97!4 = !{!"llvm.loop.interleave.count", i32 1}98!5 = !{!"llvm.loop.vectorize.enable", i1 true}99