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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter-out-after "^scalar.ph:"2; RUN: opt -passes=loop-vectorize,dce -prefer-predicate-over-epilogue=scalar-epilogue \3; RUN: -enable-epilogue-vectorization=false < %s -S | FileCheck %s4 5target triple = "aarch64-unknown-linux-gnu"6 7; This should be vscale x 8 vectorized, maybe with some interleaving.8 9define void @fneg(ptr nocapture noundef writeonly %d, ptr nocapture noundef readonly %s, i32 noundef %n) #0 {10; CHECK-LABEL: @fneg(11; CHECK-NEXT: entry:12; CHECK-NEXT: [[S2:%.*]] = ptrtoint ptr [[S:%.*]] to i6413; CHECK-NEXT: [[D1:%.*]] = ptrtoint ptr [[D:%.*]] to i6414; CHECK-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 015; CHECK-NEXT: br i1 [[CMP6]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]]16; CHECK: for.body.preheader:17; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i6418; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()19; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 420; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], [[TMP1]]21; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]]22; CHECK: vector.memcheck:23; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()24; CHECK-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 825; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 426; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[D1]], [[S2]]27; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP5]], [[TMP4]]28; CHECK-NEXT: br i1 [[DIFF_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]29; CHECK: vector.ph:30; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()31; CHECK-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 1632; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[WIDE_TRIP_COUNT]], [[TMP7]]33; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]]34; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]35; CHECK: vector.body:36; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]37; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds half, ptr [[S]], i64 [[INDEX]]38; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.vscale.i64()39; CHECK-NEXT: [[TMP14:%.*]] = shl nuw i64 [[TMP13]], 340; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds half, ptr [[TMP11]], i64 [[TMP14]]41; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP11]], align 242; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 8 x half>, ptr [[TMP15]], align 243; CHECK-NEXT: [[TMP16:%.*]] = fneg <vscale x 8 x half> [[WIDE_LOAD]]44; CHECK-NEXT: [[TMP17:%.*]] = fneg <vscale x 8 x half> [[WIDE_LOAD3]]45; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds half, ptr [[D]], i64 [[INDEX]]46; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64()47; CHECK-NEXT: [[TMP21:%.*]] = shl nuw i64 [[TMP20]], 348; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds half, ptr [[TMP18]], i64 [[TMP21]]49; CHECK-NEXT: store <vscale x 8 x half> [[TMP16]], ptr [[TMP18]], align 250; CHECK-NEXT: store <vscale x 8 x half> [[TMP17]], ptr [[TMP22]], align 251; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP7]]52; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]53; CHECK-NEXT: br i1 [[TMP23]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]54; CHECK: middle.block:55; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]]56; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]], label [[SCALAR_PH]]57; CHECK: scalar.ph:58;59entry:60 %cmp6 = icmp sgt i32 %n, 061 br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup62 63for.body.preheader: ; preds = %entry64 %wide.trip.count = zext i32 %n to i6465 br label %for.body66 67for.cond.cleanup: ; preds = %for.body, %entry68 ret void69 70for.body: ; preds = %for.body.preheader, %for.body71 %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]72 %arrayidx = getelementptr inbounds half, ptr %s, i64 %indvars.iv73 %0 = load half, ptr %arrayidx, align 274 %fneg = fneg half %075 %arrayidx2 = getelementptr inbounds half, ptr %d, i64 %indvars.iv76 store half %fneg, ptr %arrayidx2, align 277 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 178 %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count79 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body80}81 82attributes #0 = { "target-features"="+sve" vscale_range(1,16) }83