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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -mtriple=aarch64-none-linux-gnu -S %s | FileCheck %s3 4target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"5 6; Test cases for modeling interleave access costs.7 8; Function Attrs: vscale_range(2,2)9define void @test_masked_interleave(ptr noalias %A, ptr noalias %B, ptr noalias %C) #0 {10; CHECK-LABEL: define void @test_masked_interleave(11; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0:[0-9]+]] {12; CHECK-NEXT: [[ENTRY:.*]]:13; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]14; CHECK: [[LOOP_HEADER]]:15; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 0, %[[ENTRY]] ]16; CHECK-NEXT: [[IV_1:%.*]] = or disjoint i64 [[IV]], 117; CHECK-NEXT: [[GEP_A_1:%.*]] = getelementptr i8, ptr [[A]], i64 [[IV_1]]18; CHECK-NEXT: [[L_1:%.*]] = load i8, ptr [[GEP_A_1]], align 119; CHECK-NEXT: [[C_1:%.*]] = icmp eq i8 [[L_1]], 020; CHECK-NEXT: br i1 [[C_1]], label %[[THEN:.*]], label %[[LOOP_LATCH]]21; CHECK: [[THEN]]:22; CHECK-NEXT: [[IV_2:%.*]] = or disjoint i64 [[IV]], 223; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr i8, ptr [[A]], i64 [[IV_2]]24; CHECK-NEXT: [[L_2:%.*]] = load i8, ptr [[ARRAYIDX7]], align 125; CHECK-NEXT: [[CONV8:%.*]] = zext i8 [[L_2]] to i3226; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV8]], 227; CHECK-NEXT: [[ADD9:%.*]] = or disjoint i64 [[IV]], 128; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr i8, ptr [[A]], i64 [[ADD9]]29; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX10]], align 130; CHECK-NEXT: [[CONV11:%.*]] = zext i8 [[TMP0]] to i3231; CHECK-NEXT: [[SHL12:%.*]] = shl i32 [[CONV11]], 232; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL12]], [[SHL]]33; CHECK-NEXT: [[B2:%.*]] = getelementptr i8, ptr [[A]], i64 [[IV]]34; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[B2]], align 135; CHECK-NEXT: [[CONV15:%.*]] = zext i8 [[TMP1]] to i3236; CHECK-NEXT: [[OR16:%.*]] = or i32 [[OR]], [[CONV15]]37; CHECK-NEXT: [[SHL17:%.*]] = shl i32 [[OR16]], 238; CHECK-NEXT: [[CONV19:%.*]] = trunc i64 [[IV]] to i3239; CHECK-NEXT: [[ADD20:%.*]] = or i32 3, [[CONV19]]40; CHECK-NEXT: [[DEST_0:%.*]] = or i32 [[SHL17]], [[ADD20]]41; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[DEST_0]], 242; CHECK-NEXT: [[SHR26:%.*]] = lshr i32 [[CONV8]], 243; CHECK-NEXT: [[CONV27:%.*]] = trunc i32 [[SHR26]] to i844; CHECK-NEXT: store i8 [[CONV27]], ptr [[ARRAYIDX7]], align 145; CHECK-NEXT: [[SHR30:%.*]] = lshr i32 [[CONV8]], 546; CHECK-NEXT: [[CONV31:%.*]] = trunc i32 [[SHR30]] to i847; CHECK-NEXT: store i8 [[CONV31]], ptr [[C]], align 148; CHECK-NEXT: [[CONV34:%.*]] = trunc i32 [[SHR]] to i849; CHECK-NEXT: store i8 [[CONV34]], ptr [[B]], align 150; CHECK-NEXT: br label %[[LOOP_LATCH]]51; CHECK: [[LOOP_LATCH]]:52; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 453; CHECK-NEXT: [[EC:%.*]] = icmp ugt i64 [[IV]], 100054; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]55; CHECK: [[EXIT]]:56; CHECK-NEXT: ret void57;58entry:59 br label %loop.header60 61loop.header:62 %iv = phi i64 [ %iv.next, %loop.latch ], [ 0, %entry ]63 %iv.1 = or disjoint i64 %iv, 164 %gep.A.1 = getelementptr i8, ptr %A, i64 %iv.165 %l.1 = load i8, ptr %gep.A.1, align 166 %c.1 = icmp eq i8 %l.1, 067 br i1 %c.1, label %then, label %loop.latch68 69then:70 %iv.2 = or disjoint i64 %iv, 271 %arrayidx7 = getelementptr i8, ptr %A, i64 %iv.272 %l.2 = load i8, ptr %arrayidx7, align 173 %conv8 = zext i8 %l.2 to i3274 %shl = shl i32 %conv8, 275 %add9 = or disjoint i64 %iv, 176 %arrayidx10 = getelementptr i8, ptr %A, i64 %add977 %2 = load i8, ptr %arrayidx10, align 178 %conv11 = zext i8 %2 to i3279 %shl12 = shl i32 %conv11, 280 %or = or i32 %shl12, %shl81 %B2 = getelementptr i8, ptr %A, i64 %iv82 %3 = load i8, ptr %B2, align 183 %conv15 = zext i8 %3 to i3284 %or16 = or i32 %or, %conv1585 %shl17 = shl i32 %or16, 286 %conv19 = trunc i64 %iv to i3287 %add20 = or i32 3, %conv1988 %dest.0 = or i32 %shl17, %add2089 %shr = lshr i32 %dest.0, 290 %shr26 = lshr i32 %conv8, 291 %conv27 = trunc i32 %shr26 to i892 store i8 %conv27, ptr %arrayidx7, align 193 %shr30 = lshr i32 %conv8, 594 %conv31 = trunc i32 %shr30 to i895 store i8 %conv31, ptr %C, align 196 %conv34 = trunc i32 %shr to i897 store i8 %conv34, ptr %B, align 198 br label %loop.latch99 100loop.latch:101 %iv.next = add i64 %iv, 4102 %ec = icmp ugt i64 %iv, 1000103 br i1 %ec, label %exit, label %loop.header104 105exit:106 ret void107}108 109attributes #0 = { vscale_range(2,2) "target-cpu"="neoverse-512tvb" }110