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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "scalar.ph\:" --version 52; RUN: opt -passes=loop-vectorize -S < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6define void @trip7_i64(ptr noalias nocapture noundef %dst, ptr noalias nocapture noundef readonly %src) #0 {7; CHECK-LABEL: define void @trip7_i64(8; CHECK-SAME: ptr noalias noundef captures(none) [[DST:%.*]], ptr noalias noundef readonly captures(none) [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: [[ENTRY:.*:]]10; CHECK-NEXT: br label %[[VECTOR_PH:.*]]11; CHECK: [[VECTOR_PH]]:12; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()13; CHECK-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 214; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 0, i64 7)15; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]16; CHECK: [[VECTOR_BODY]]:17; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]18; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 2 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]19; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[INDEX]]20; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr align 8 [[TMP5]], <vscale x 2 x i1> [[ACTIVE_LANE_MASK]], <vscale x 2 x i64> poison)21; CHECK-NEXT: [[TMP6:%.*]] = shl nsw <vscale x 2 x i64> [[WIDE_MASKED_LOAD]], splat (i64 1)22; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[INDEX]]23; CHECK-NEXT: [[WIDE_MASKED_LOAD1:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr align 8 [[TMP7]], <vscale x 2 x i1> [[ACTIVE_LANE_MASK]], <vscale x 2 x i64> poison)24; CHECK-NEXT: [[TMP8:%.*]] = add nsw <vscale x 2 x i64> [[WIDE_MASKED_LOAD1]], [[TMP6]]25; CHECK-NEXT: call void @llvm.masked.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP8]], ptr align 8 [[TMP7]], <vscale x 2 x i1> [[ACTIVE_LANE_MASK]])26; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP4]]27; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[INDEX_NEXT]], i64 7)28; CHECK-NEXT: [[EXTRACT_FIRST_LANE_MASK:%.*]] = extractelement <vscale x 2 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 029; CHECK-NEXT: [[COND:%.*]] = xor i1 [[EXTRACT_FIRST_LANE_MASK]], true30; CHECK-NEXT: br i1 [[COND]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]31; CHECK: [[MIDDLE_BLOCK]]:32; CHECK-NEXT: br label %[[EXIT:.*]]33; CHECK: [[EXIT]]:34; CHECK-NEXT: ret void35;36entry:37 br label %loop38 39loop:40 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]41 %gep.src = getelementptr inbounds i64, ptr %src, i64 %iv42 %0 = load i64, ptr %gep.src, align 843 %mul = shl nsw i64 %0, 144 %gep.dst = getelementptr inbounds i64, ptr %dst, i64 %iv45 %1 = load i64, ptr %gep.dst, align 846 %add = add nsw i64 %1, %mul47 store i64 %add, ptr %gep.dst, align 848 %iv.next = add nuw nsw i64 %iv, 149 %ec = icmp eq i64 %iv.next, 750 br i1 %ec, label %exit, label %loop51 52exit:53 ret void54}55 56define void @trip5_i8(ptr noalias nocapture noundef %dst, ptr noalias nocapture noundef readonly %src) #0 {57; CHECK-LABEL: define void @trip5_i8(58; CHECK-SAME: ptr noalias noundef captures(none) [[DST:%.*]], ptr noalias noundef readonly captures(none) [[SRC:%.*]]) #[[ATTR0]] {59; CHECK-NEXT: [[ENTRY:.*]]:60; CHECK-NEXT: br label %[[LOOP:.*]]61; CHECK: [[LOOP]]:62; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]63; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[IV]]64; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[GEP_SRC]], align 165; CHECK-NEXT: [[MUL:%.*]] = shl i8 [[TMP0]], 166; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[IV]]67; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[GEP_DST]], align 168; CHECK-NEXT: [[ADD:%.*]] = add i8 [[MUL]], [[TMP1]]69; CHECK-NEXT: store i8 [[ADD]], ptr [[GEP_DST]], align 170; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 171; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 572; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]73; CHECK: [[EXIT]]:74; CHECK-NEXT: ret void75;76entry:77 br label %loop78 79loop:80 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]81 %gep.src = getelementptr inbounds i8, ptr %src, i64 %iv82 %0 = load i8, ptr %gep.src, align 183 %mul = shl i8 %0, 184 %gep.dst = getelementptr inbounds i8, ptr %dst, i64 %iv85 %1 = load i8, ptr %gep.dst, align 186 %add = add i8 %mul, %187 store i8 %add, ptr %gep.dst, align 188 %iv.next = add nuw nsw i64 %iv, 189 %ec = icmp eq i64 %iv.next, 590 br i1 %ec, label %exit, label %loop91 92exit:93 ret void94}95 96attributes #0 = { vscale_range(1,16) "target-features"="+sve" }97