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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter-out-after "^scalar.ph:"2; RUN: opt -passes=loop-vectorize -mattr=+sve -prefer-predicate-over-epilogue=scalar-epilogue -S %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6; Test case where the minimum profitable trip count due to runtime checks7; exceeds VF.getKnownMinValue() * UF.8define void @min_trip_count_due_to_runtime_checks_1(ptr %dst.1, ptr %dst.2, ptr %src.1, ptr %src.2, i64 %n) {9; CHECK-LABEL: @min_trip_count_due_to_runtime_checks_1(10; CHECK-NEXT: entry:11; CHECK-NEXT: [[SRC_25:%.*]] = ptrtoint ptr [[SRC_2:%.*]] to i6412; CHECK-NEXT: [[SRC_13:%.*]] = ptrtoint ptr [[SRC_1:%.*]] to i6413; CHECK-NEXT: [[DST_12:%.*]] = ptrtoint ptr [[DST_1:%.*]] to i6414; CHECK-NEXT: [[DST_21:%.*]] = ptrtoint ptr [[DST_2:%.*]] to i6415; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N:%.*]], i64 1)16; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()17; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 218; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP1]], i64 20)19; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], [[TMP2]]20; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]]21; CHECK: vector.memcheck:22; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()23; CHECK-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 224; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 1625; CHECK-NEXT: [[TMP6:%.*]] = sub i64 [[DST_21]], [[DST_12]]26; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]27; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 1628; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[DST_12]], [[SRC_13]]29; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP8]], [[TMP7]]30; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]31; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[TMP4]], 1632; CHECK-NEXT: [[TMP10:%.*]] = sub i64 [[DST_12]], [[SRC_25]]33; CHECK-NEXT: [[DIFF_CHECK6:%.*]] = icmp ult i64 [[TMP10]], [[TMP9]]34; CHECK-NEXT: [[CONFLICT_RDX7:%.*]] = or i1 [[CONFLICT_RDX]], [[DIFF_CHECK6]]35; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[TMP4]], 1636; CHECK-NEXT: [[TMP12:%.*]] = sub i64 [[DST_21]], [[SRC_13]]37; CHECK-NEXT: [[DIFF_CHECK8:%.*]] = icmp ult i64 [[TMP12]], [[TMP11]]38; CHECK-NEXT: [[CONFLICT_RDX9:%.*]] = or i1 [[CONFLICT_RDX7]], [[DIFF_CHECK8]]39; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[TMP4]], 1640; CHECK-NEXT: [[TMP14:%.*]] = sub i64 [[DST_21]], [[SRC_25]]41; CHECK-NEXT: [[DIFF_CHECK10:%.*]] = icmp ult i64 [[TMP14]], [[TMP13]]42; CHECK-NEXT: [[CONFLICT_RDX11:%.*]] = or i1 [[CONFLICT_RDX9]], [[DIFF_CHECK10]]43; CHECK-NEXT: br i1 [[CONFLICT_RDX11]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]44; CHECK: vector.ph:45; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()46; CHECK-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP15]], 447; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], [[TMP16]]48; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]]49; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]50; CHECK: vector.body:51; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]52; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i64, ptr [[SRC_1]], i64 [[INDEX]]53; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[INDEX]]54; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.vscale.i64()55; CHECK-NEXT: [[TMP29:%.*]] = shl nuw i64 [[TMP28]], 156; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i64, ptr [[TMP27]], i64 [[TMP29]]57; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[TMP27]], align 858; CHECK-NEXT: [[WIDE_LOAD12:%.*]] = load <vscale x 2 x i64>, ptr [[TMP30]], align 859; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.vscale.i64()60; CHECK-NEXT: [[TMP33:%.*]] = shl nuw i64 [[TMP32]], 161; CHECK-NEXT: [[TMP34:%.*]] = getelementptr i64, ptr [[TMP31]], i64 [[TMP33]]62; CHECK-NEXT: [[WIDE_LOAD13:%.*]] = load <vscale x 2 x i64>, ptr [[TMP31]], align 863; CHECK-NEXT: [[WIDE_LOAD14:%.*]] = load <vscale x 2 x i64>, ptr [[TMP34]], align 864; CHECK-NEXT: [[TMP35:%.*]] = add <vscale x 2 x i64> [[WIDE_LOAD]], [[WIDE_LOAD13]]65; CHECK-NEXT: [[TMP36:%.*]] = add <vscale x 2 x i64> [[WIDE_LOAD12]], [[WIDE_LOAD14]]66; CHECK-NEXT: [[TMP41:%.*]] = getelementptr i64, ptr [[DST_1]], i64 [[INDEX]]67; CHECK-NEXT: [[TMP45:%.*]] = getelementptr i64, ptr [[DST_2]], i64 [[INDEX]]68; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.vscale.i64()69; CHECK-NEXT: [[TMP43:%.*]] = shl nuw i64 [[TMP42]], 170; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i64, ptr [[TMP41]], i64 [[TMP43]]71; CHECK-NEXT: store <vscale x 2 x i64> [[TMP35]], ptr [[TMP41]], align 872; CHECK-NEXT: store <vscale x 2 x i64> [[TMP36]], ptr [[TMP44]], align 873; CHECK-NEXT: [[TMP46:%.*]] = call i64 @llvm.vscale.i64()74; CHECK-NEXT: [[TMP47:%.*]] = shl nuw i64 [[TMP46]], 175; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i64, ptr [[TMP45]], i64 [[TMP47]]76; CHECK-NEXT: store <vscale x 2 x i64> [[TMP35]], ptr [[TMP45]], align 877; CHECK-NEXT: store <vscale x 2 x i64> [[TMP36]], ptr [[TMP48]], align 878; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP16]]79; CHECK-NEXT: [[TMP51:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]80; CHECK-NEXT: br i1 [[TMP51]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]81; CHECK: middle.block:82; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]]83; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]84; CHECK: scalar.ph:85;86entry:87 br label %loop88 89loop:90 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]91 %gep.src.1 = getelementptr i64, ptr %src.1, i64 %iv92 %gep.src.2 = getelementptr i64, ptr %src.2, i64 %iv93 %l.1 = load i64, ptr %gep.src.194 %l.2 = load i64, ptr %gep.src.295 %add = add i64 %l.1, %l.296 %gep.dst.1 = getelementptr i64, ptr %dst.1, i64 %iv97 %gep.dst.2 = getelementptr i64, ptr %dst.2, i64 %iv98 store i64 %add, ptr %gep.dst.199 store i64 %add, ptr %gep.dst.2100 %iv.next = add nsw i64 %iv, 1101 %cmp10 = icmp ult i64 %iv.next, %n102 br i1 %cmp10, label %loop, label %exit103 104exit:105 ret void106}107