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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter-out-after "^scalar.ph:"2; REQUIRES: asserts3; RUN: opt -S -passes=loop-vectorize -debug-only=loop-vectorize < %s 2>%t | FileCheck %s4; RUN: cat %t | FileCheck %s --check-prefix=VPLANS5 6; These tests ensure that tail-folding is enabled when the predicate.enable7; loop attribute is set to true.8 9target triple = "aarch64-unknown-linux-gnu"10 11; VPLANS-LABEL: Checking a loop in 'simple_memset'12; VPLANS: VPlan 'Initial VPlan for VF={vscale x 1,vscale x 2,vscale x 4},UF>=1' {13; VPLANS-NEXT: Live-in vp<[[VF:%.+]]> = VF14; VPLANS-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF15; VPLANS: vp<[[TC:%[0-9]+]]> = original trip-count16; VPLANS-EMPTY:17; VPLANS-NEXT: ir-bb<entry>:18; VPLANS-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (1 umax %n)19; VPLANS-NEXT: Successor(s): scalar.ph, vector.ph20; VPLANS-EMPTY:21; VPLANS-NEXT: vector.ph:22; VPLANS-NEXT: EMIT vp<[[NEWTC:%[0-9]+]]> = TC > VF ? TC - VF : 0 vp<[[TC]]>23; VPLANS-NEXT: EMIT vp<[[VF_PER_PART:%.+]]> = VF * Part + ir<0>24; VPLANS-NEXT: EMIT vp<[[LANEMASK_ENTRY:%.+]]> = active lane mask vp<[[VF_PER_PART]]>, vp<[[TC]]>25; VPLANS-NEXT: Successor(s): vector loop26; VPLANS-EMPTY:27; VPLANS-NEXT: <x1> vector loop: {28; VPLANS-NEXT: vector.body:29; VPLANS-NEXT: EMIT vp<[[INDV:%[0-9]+]]> = CANONICAL-INDUCTION30; VPLANS-NEXT: ACTIVE-LANE-MASK-PHI vp<[[LANEMASK_PHI:%[0-9]+]]> = phi vp<[[LANEMASK_ENTRY]]>, vp<[[LANEMASK_LOOP:%.+]]>31; VPLANS-NEXT: vp<[[STEP:%[0-9]+]]> = SCALAR-STEPS vp<[[INDV]]>, ir<1>, vp<[[VF]]>32; VPLANS-NEXT: CLONE ir<%gep> = getelementptr ir<%ptr>, vp<[[STEP]]>33; VPLANS-NEXT: vp<[[VEC_PTR:%[0-9]+]]> = vector-pointer ir<%gep>34; VPLANS-NEXT: WIDEN store vp<[[VEC_PTR]]>, ir<%val>, vp<[[LANEMASK_PHI]]>35; VPLANS-NEXT: EMIT vp<[[INDV_UPDATE:%.+]]> = add vp<[[INDV]]>, vp<[[VFxUF]]>36; VPLANS-NEXT: EMIT vp<[[INC:%[0-9]+]]> = VF * Part + vp<[[INDV]]>37; VPLANS-NEXT: EMIT vp<[[LANEMASK_LOOP]]> = active lane mask vp<[[INC]]>, vp<[[NEWTC]]>38; VPLANS-NEXT: EMIT vp<[[NOT:%[0-9]+]]> = not vp<[[LANEMASK_LOOP]]>39; VPLANS-NEXT: EMIT branch-on-cond vp<[[NOT]]>40; VPLANS-NEXT: No successors41; VPLANS-NEXT: }42 43define void @simple_memset(i32 %val, ptr %ptr, i64 %n) #0 {44; CHECK-LABEL: @simple_memset(45; CHECK-NEXT: entry:46; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N:%.*]], i64 1)47; CHECK-NEXT: br label [[VECTOR_PH:%.*]]48; CHECK: vector.ph:49; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.vscale.i64()50; CHECK-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 451; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()52; CHECK-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 253; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[UMAX]], [[TMP6]]54; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i64 [[UMAX]], [[TMP6]]55; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i64 [[TMP7]], i64 056; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 [[UMAX]])57; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[VAL:%.*]], i64 058; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer59; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]60; CHECK: vector.body:61; CHECK-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT2:%.*]], [[VECTOR_BODY]] ]62; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ]63; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[PTR:%.*]], i64 [[INDEX1]]64; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[BROADCAST_SPLAT]], ptr align 4 [[TMP11]], <vscale x 4 x i1> [[ACTIVE_LANE_MASK]])65; CHECK-NEXT: [[INDEX_NEXT2]] = add i64 [[INDEX1]], [[TMP14]]66; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX1]], i64 [[TMP9]])67; CHECK-NEXT: [[TMP15:%.*]] = extractelement <vscale x 4 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 068; CHECK-NEXT: [[TMP12:%.*]] = xor i1 [[TMP15]], true69; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]70; CHECK: middle.block:71; CHECK-NEXT: br label [[WHILE_END_LOOPEXIT:%.*]]72; CHECK: while.end.loopexit:73; CHECK-NEXT: ret void74;75entry:76 br label %while.body77 78while.body: ; preds = %while.body, %entry79 %index = phi i64 [ %index.next, %while.body ], [ 0, %entry ]80 %gep = getelementptr i32, ptr %ptr, i64 %index81 store i32 %val, ptr %gep82 %index.next = add nsw i64 %index, 183 %cmp10 = icmp ult i64 %index.next, %n84 br i1 %cmp10, label %while.body, label %while.end.loopexit, !llvm.loop !085 86while.end.loopexit: ; preds = %while.body87 ret void88}89 90 91attributes #0 = { "target-features"="+sve" }92 93!0 = distinct !{!0, !1}94!1 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}95