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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter-out-after "^scalar.ph:"2; RUN: opt -passes=loop-vectorize -S < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6define void @trip1025_i64(ptr noalias nocapture noundef %dst, ptr noalias nocapture noundef readonly %src) #0 {7; CHECK-LABEL: @trip1025_i64(8; CHECK-NEXT: entry:9; CHECK-NEXT: br label [[VECTOR_PH:%.*]]10; CHECK: vector.ph:11; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()12; CHECK-NEXT: [[TMP1:%.*]] = mul nuw i64 [[TMP0]], 213; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 0, i64 1025)14; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]15; CHECK: vector.body:16; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]17; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 2 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ]18; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[SRC:%.*]], i64 [[INDEX]]19; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr align 8 [[TMP8]], <vscale x 2 x i1> [[ACTIVE_LANE_MASK]], <vscale x 2 x i64> poison)20; CHECK-NEXT: [[TMP10:%.*]] = shl nsw <vscale x 2 x i64> [[WIDE_MASKED_LOAD]], splat (i64 1)21; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[DST:%.*]], i64 [[INDEX]]22; CHECK-NEXT: [[WIDE_MASKED_LOAD1:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr align 8 [[TMP11]], <vscale x 2 x i1> [[ACTIVE_LANE_MASK]], <vscale x 2 x i64> poison)23; CHECK-NEXT: [[TMP13:%.*]] = add nsw <vscale x 2 x i64> [[WIDE_MASKED_LOAD1]], [[TMP10]]24; CHECK-NEXT: call void @llvm.masked.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP13]], ptr align 8 [[TMP11]], <vscale x 2 x i1> [[ACTIVE_LANE_MASK]])25; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP1]]26; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[INDEX_NEXT]], i64 1025)27; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 2 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 028; CHECK-NEXT: [[TMP12:%.*]] = xor i1 [[TMP9]], true29; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]30; CHECK: middle.block:31; CHECK-NEXT: br label [[FOR_END:%.*]]32; CHECK: for.end:33; CHECK-NEXT: ret void34;35entry:36 br label %for.body37 38for.body: ; preds = %entry, %for.body39 %i.06 = phi i64 [ 0, %entry ], [ %inc, %for.body ]40 %arrayidx = getelementptr inbounds i64, ptr %src, i64 %i.0641 %0 = load i64, ptr %arrayidx, align 842 %mul = shl nsw i64 %0, 143 %arrayidx1 = getelementptr inbounds i64, ptr %dst, i64 %i.0644 %1 = load i64, ptr %arrayidx1, align 845 %add = add nsw i64 %1, %mul46 store i64 %add, ptr %arrayidx1, align 847 %inc = add nuw nsw i64 %i.06, 148 %exitcond.not = icmp eq i64 %inc, 102549 br i1 %exitcond.not, label %for.end, label %for.body50 51for.end: ; preds = %for.body52 ret void53}54 55attributes #0 = { vscale_range(1,16) "target-features"="+sve" optsize }56