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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter-out-after "^scalar.ph:"2; RUN: opt -S -passes=loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -force-vector-interleave=4 -force-vector-width=4 < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6 7define void @simple_memset(i32 %val, ptr %ptr, i64 %n) #0 {8; CHECK-LABEL: @simple_memset(9; CHECK-NEXT: entry:10; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N:%.*]], i64 1)11; CHECK-NEXT: br label [[VECTOR_PH:%.*]]12; CHECK: vector.ph:13; CHECK-NEXT: [[TMP61:%.*]] = call i64 @llvm.vscale.i64()14; CHECK-NEXT: [[TMP62:%.*]] = mul nuw i64 [[TMP61]], 1615; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()16; CHECK-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 417; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[UMAX]], [[TMP6]]18; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i64 [[UMAX]], [[TMP6]]19; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i64 [[TMP7]], i64 020; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.vscale.i64()21; CHECK-NEXT: [[TMP26:%.*]] = shl nuw i64 [[TMP25]], 222; CHECK-NEXT: [[INDEX_PART_NEXT:%.*]] = add i64 0, [[TMP26]]23; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()24; CHECK-NEXT: [[TMP28:%.*]] = shl nuw i64 [[TMP27]], 325; CHECK-NEXT: [[INDEX_PART_NEXT1:%.*]] = add i64 0, [[TMP28]]26; CHECK-NEXT: [[TMP29:%.*]] = call i64 @llvm.vscale.i64()27; CHECK-NEXT: [[TMP30:%.*]] = mul nuw i64 [[TMP29]], 1228; CHECK-NEXT: [[INDEX_PART_NEXT2:%.*]] = add i64 0, [[TMP30]]29; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 [[UMAX]])30; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY3:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX_PART_NEXT]], i64 [[UMAX]])31; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY4:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX_PART_NEXT1]], i64 [[UMAX]])32; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY5:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX_PART_NEXT2]], i64 [[UMAX]])33; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[VAL:%.*]], i64 034; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer35; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]36; CHECK: vector.body:37; CHECK-NEXT: [[INDEX6:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT10:%.*]], [[VECTOR_BODY]] ]38; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ]39; CHECK-NEXT: [[ACTIVE_LANE_MASK7:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY3]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT11:%.*]], [[VECTOR_BODY]] ]40; CHECK-NEXT: [[ACTIVE_LANE_MASK8:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY4]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT12:%.*]], [[VECTOR_BODY]] ]41; CHECK-NEXT: [[ACTIVE_LANE_MASK9:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY5]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT13:%.*]], [[VECTOR_BODY]] ]42; CHECK-NEXT: [[TMP47:%.*]] = getelementptr i32, ptr [[PTR:%.*]], i64 [[INDEX6]]43; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.vscale.i64()44; CHECK-NEXT: [[TMP53:%.*]] = shl nuw i64 [[TMP52]], 245; CHECK-NEXT: [[TMP54:%.*]] = getelementptr i32, ptr [[TMP47]], i64 [[TMP53]]46; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.vscale.i64()47; CHECK-NEXT: [[TMP56:%.*]] = shl nuw i64 [[TMP55]], 348; CHECK-NEXT: [[TMP57:%.*]] = getelementptr i32, ptr [[TMP47]], i64 [[TMP56]]49; CHECK-NEXT: [[TMP58:%.*]] = call i64 @llvm.vscale.i64()50; CHECK-NEXT: [[TMP59:%.*]] = mul nuw i64 [[TMP58]], 1251; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i32, ptr [[TMP47]], i64 [[TMP59]]52; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[BROADCAST_SPLAT]], ptr align 4 [[TMP47]], <vscale x 4 x i1> [[ACTIVE_LANE_MASK]])53; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[BROADCAST_SPLAT]], ptr align 4 [[TMP54]], <vscale x 4 x i1> [[ACTIVE_LANE_MASK7]])54; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[BROADCAST_SPLAT]], ptr align 4 [[TMP57]], <vscale x 4 x i1> [[ACTIVE_LANE_MASK8]])55; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[BROADCAST_SPLAT]], ptr align 4 [[TMP60]], <vscale x 4 x i1> [[ACTIVE_LANE_MASK9]])56; CHECK-NEXT: [[INDEX_NEXT10]] = add i64 [[INDEX6]], [[TMP62]]57; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()58; CHECK-NEXT: [[TMP64:%.*]] = shl nuw i64 [[TMP63]], 259; CHECK-NEXT: [[TMP65:%.*]] = add i64 [[INDEX6]], [[TMP64]]60; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.vscale.i64()61; CHECK-NEXT: [[TMP67:%.*]] = shl nuw i64 [[TMP66]], 362; CHECK-NEXT: [[TMP68:%.*]] = add i64 [[INDEX6]], [[TMP67]]63; CHECK-NEXT: [[TMP69:%.*]] = call i64 @llvm.vscale.i64()64; CHECK-NEXT: [[TMP70:%.*]] = mul nuw i64 [[TMP69]], 1265; CHECK-NEXT: [[TMP71:%.*]] = add i64 [[INDEX6]], [[TMP70]]66; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX6]], i64 [[TMP9]])67; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT11]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[TMP65]], i64 [[TMP9]])68; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT12]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[TMP68]], i64 [[TMP9]])69; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT13]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[TMP71]], i64 [[TMP9]])70; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 4 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 071; CHECK-NEXT: [[TMP36:%.*]] = xor i1 [[TMP35]], true72; CHECK-NEXT: br i1 [[TMP36]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]73; CHECK: middle.block:74; CHECK-NEXT: br label [[WHILE_END_LOOPEXIT:%.*]]75; CHECK: while.end.loopexit:76; CHECK-NEXT: ret void77;78entry:79 br label %while.body80 81while.body: ; preds = %while.body, %entry82 %index = phi i64 [ %index.next, %while.body ], [ 0, %entry ]83 %gep = getelementptr i32, ptr %ptr, i64 %index84 store i32 %val, ptr %gep85 %index.next = add nsw i64 %index, 186 %cmp10 = icmp ult i64 %index.next, %n87 br i1 %cmp10, label %while.body, label %while.end.loopexit, !llvm.loop !088 89while.end.loopexit: ; preds = %while.body90 ret void91}92 93define void @cond_memset(i32 %val, ptr noalias readonly %cond_ptr, ptr noalias %ptr, i64 %n) #0 {94; CHECK-LABEL: @cond_memset(95; CHECK-NEXT: entry:96; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N:%.*]], i64 1)97; CHECK-NEXT: br label [[VECTOR_PH:%.*]]98; CHECK: vector.ph:99; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()100; CHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 16101; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()102; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 4103; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[UMAX]], [[TMP3]]104; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i64 [[UMAX]], [[TMP3]]105; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i64 [[TMP7]], i64 0106; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.vscale.i64()107; CHECK-NEXT: [[TMP26:%.*]] = shl nuw i64 [[TMP25]], 2108; CHECK-NEXT: [[INDEX_PART_NEXT:%.*]] = add i64 0, [[TMP26]]109; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()110; CHECK-NEXT: [[TMP28:%.*]] = shl nuw i64 [[TMP27]], 3111; CHECK-NEXT: [[INDEX_PART_NEXT1:%.*]] = add i64 0, [[TMP28]]112; CHECK-NEXT: [[TMP29:%.*]] = call i64 @llvm.vscale.i64()113; CHECK-NEXT: [[TMP30:%.*]] = mul nuw i64 [[TMP29]], 12114; CHECK-NEXT: [[INDEX_PART_NEXT2:%.*]] = add i64 0, [[TMP30]]115; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 [[UMAX]])116; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY3:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX_PART_NEXT]], i64 [[UMAX]])117; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY4:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX_PART_NEXT1]], i64 [[UMAX]])118; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY5:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX_PART_NEXT2]], i64 [[UMAX]])119; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[VAL:%.*]], i64 0120; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer121; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]122; CHECK: vector.body:123; CHECK-NEXT: [[INDEX6:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT13:%.*]], [[VECTOR_BODY]] ]124; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ]125; CHECK-NEXT: [[ACTIVE_LANE_MASK7:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY3]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT14:%.*]], [[VECTOR_BODY]] ]126; CHECK-NEXT: [[ACTIVE_LANE_MASK8:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY4]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT15:%.*]], [[VECTOR_BODY]] ]127; CHECK-NEXT: [[ACTIVE_LANE_MASK9:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY5]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT16:%.*]], [[VECTOR_BODY]] ]128; CHECK-NEXT: [[TMP47:%.*]] = getelementptr i32, ptr [[COND_PTR:%.*]], i64 [[INDEX6]]129; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.vscale.i64()130; CHECK-NEXT: [[TMP53:%.*]] = shl nuw i64 [[TMP52]], 2131; CHECK-NEXT: [[TMP54:%.*]] = getelementptr i32, ptr [[TMP47]], i64 [[TMP53]]132; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.vscale.i64()133; CHECK-NEXT: [[TMP56:%.*]] = shl nuw i64 [[TMP55]], 3134; CHECK-NEXT: [[TMP57:%.*]] = getelementptr i32, ptr [[TMP47]], i64 [[TMP56]]135; CHECK-NEXT: [[TMP58:%.*]] = call i64 @llvm.vscale.i64()136; CHECK-NEXT: [[TMP59:%.*]] = mul nuw i64 [[TMP58]], 12137; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i32, ptr [[TMP47]], i64 [[TMP59]]138; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr align 4 [[TMP47]], <vscale x 4 x i1> [[ACTIVE_LANE_MASK]], <vscale x 4 x i32> poison)139; CHECK-NEXT: [[WIDE_MASKED_LOAD10:%.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr align 4 [[TMP54]], <vscale x 4 x i1> [[ACTIVE_LANE_MASK7]], <vscale x 4 x i32> poison)140; CHECK-NEXT: [[WIDE_MASKED_LOAD11:%.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr align 4 [[TMP57]], <vscale x 4 x i1> [[ACTIVE_LANE_MASK8]], <vscale x 4 x i32> poison)141; CHECK-NEXT: [[WIDE_MASKED_LOAD12:%.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr align 4 [[TMP60]], <vscale x 4 x i1> [[ACTIVE_LANE_MASK9]], <vscale x 4 x i32> poison)142; CHECK-NEXT: [[TMP61:%.*]] = icmp ne <vscale x 4 x i32> [[WIDE_MASKED_LOAD]], zeroinitializer143; CHECK-NEXT: [[TMP62:%.*]] = icmp ne <vscale x 4 x i32> [[WIDE_MASKED_LOAD10]], zeroinitializer144; CHECK-NEXT: [[TMP63:%.*]] = icmp ne <vscale x 4 x i32> [[WIDE_MASKED_LOAD11]], zeroinitializer145; CHECK-NEXT: [[TMP64:%.*]] = icmp ne <vscale x 4 x i32> [[WIDE_MASKED_LOAD12]], zeroinitializer146; CHECK-NEXT: [[TMP69:%.*]] = select <vscale x 4 x i1> [[ACTIVE_LANE_MASK]], <vscale x 4 x i1> [[TMP61]], <vscale x 4 x i1> zeroinitializer147; CHECK-NEXT: [[TMP70:%.*]] = select <vscale x 4 x i1> [[ACTIVE_LANE_MASK7]], <vscale x 4 x i1> [[TMP62]], <vscale x 4 x i1> zeroinitializer148; CHECK-NEXT: [[TMP71:%.*]] = select <vscale x 4 x i1> [[ACTIVE_LANE_MASK8]], <vscale x 4 x i1> [[TMP63]], <vscale x 4 x i1> zeroinitializer149; CHECK-NEXT: [[TMP72:%.*]] = select <vscale x 4 x i1> [[ACTIVE_LANE_MASK9]], <vscale x 4 x i1> [[TMP64]], <vscale x 4 x i1> zeroinitializer150; CHECK-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr [[PTR:%.*]], i64 [[INDEX6]]151; CHECK-NEXT: [[TMP74:%.*]] = call i64 @llvm.vscale.i64()152; CHECK-NEXT: [[TMP75:%.*]] = shl nuw i64 [[TMP74]], 2153; CHECK-NEXT: [[TMP76:%.*]] = getelementptr i32, ptr [[TMP65]], i64 [[TMP75]]154; CHECK-NEXT: [[TMP77:%.*]] = call i64 @llvm.vscale.i64()155; CHECK-NEXT: [[TMP78:%.*]] = shl nuw i64 [[TMP77]], 3156; CHECK-NEXT: [[TMP79:%.*]] = getelementptr i32, ptr [[TMP65]], i64 [[TMP78]]157; CHECK-NEXT: [[TMP80:%.*]] = call i64 @llvm.vscale.i64()158; CHECK-NEXT: [[TMP81:%.*]] = mul nuw i64 [[TMP80]], 12159; CHECK-NEXT: [[TMP82:%.*]] = getelementptr i32, ptr [[TMP65]], i64 [[TMP81]]160; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[BROADCAST_SPLAT]], ptr align 4 [[TMP65]], <vscale x 4 x i1> [[TMP69]])161; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[BROADCAST_SPLAT]], ptr align 4 [[TMP76]], <vscale x 4 x i1> [[TMP70]])162; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[BROADCAST_SPLAT]], ptr align 4 [[TMP79]], <vscale x 4 x i1> [[TMP71]])163; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[BROADCAST_SPLAT]], ptr align 4 [[TMP82]], <vscale x 4 x i1> [[TMP72]])164; CHECK-NEXT: [[INDEX_NEXT13]] = add i64 [[INDEX6]], [[TMP6]]165; CHECK-NEXT: [[TMP85:%.*]] = call i64 @llvm.vscale.i64()166; CHECK-NEXT: [[TMP86:%.*]] = shl nuw i64 [[TMP85]], 2167; CHECK-NEXT: [[TMP87:%.*]] = add i64 [[INDEX6]], [[TMP86]]168; CHECK-NEXT: [[TMP88:%.*]] = call i64 @llvm.vscale.i64()169; CHECK-NEXT: [[TMP89:%.*]] = shl nuw i64 [[TMP88]], 3170; CHECK-NEXT: [[TMP90:%.*]] = add i64 [[INDEX6]], [[TMP89]]171; CHECK-NEXT: [[TMP91:%.*]] = call i64 @llvm.vscale.i64()172; CHECK-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP91]], 12173; CHECK-NEXT: [[TMP93:%.*]] = add i64 [[INDEX6]], [[TMP92]]174; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX6]], i64 [[TMP9]])175; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT14]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[TMP87]], i64 [[TMP9]])176; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT15]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[TMP90]], i64 [[TMP9]])177; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT16]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[TMP93]], i64 [[TMP9]])178; CHECK-NEXT: [[TMP66:%.*]] = extractelement <vscale x 4 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 0179; CHECK-NEXT: [[TMP67:%.*]] = xor i1 [[TMP66]], true180; CHECK-NEXT: br i1 [[TMP67]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]181; CHECK: middle.block:182; CHECK-NEXT: br label [[WHILE_END_LOOPEXIT:%.*]]183; CHECK: while.end.loopexit:184; CHECK-NEXT: ret void185;186entry:187 br label %while.body188 189while.body: ; preds = %while.body, %entry190 %index = phi i64 [ %index.next, %while.end ], [ 0, %entry ]191 %cond_gep = getelementptr i32, ptr %cond_ptr, i64 %index192 %cond_i32 = load i32, ptr %cond_gep193 %cond_i1 = icmp ne i32 %cond_i32, 0194 br i1 %cond_i1, label %do.store, label %while.end195 196do.store:197 %gep = getelementptr i32, ptr %ptr, i64 %index198 store i32 %val, ptr %gep199 br label %while.end200 201while.end:202 %index.next = add nsw i64 %index, 1203 %cmp10 = icmp ult i64 %index.next, %n204 br i1 %cmp10, label %while.body, label %while.end.loopexit, !llvm.loop !0205 206while.end.loopexit: ; preds = %while.body207 ret void208}209 210!0 = distinct !{!0, !1}211!1 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}212 213attributes #0 = { "target-features"="+sve" }214