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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 62; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=VF2IC1 %s3; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=2 -S %s | FileCheck --check-prefixes=VF2IC2 %s4 5target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"6target triple = "arm64-apple-macosx"7 8define void @load_store_interleave_group_block_invar_cond(ptr noalias %data, ptr noalias %dst.0, ptr noalias %dst.1, i1 %c) {9; VF2IC1-LABEL: define void @load_store_interleave_group_block_invar_cond(10; VF2IC1-SAME: ptr noalias [[DATA:%.*]], ptr noalias [[DST_0:%.*]], ptr noalias [[DST_1:%.*]], i1 [[C:%.*]]) {11; VF2IC1-NEXT: [[ENTRY:.*:]]12; VF2IC1-NEXT: br label %[[VECTOR_PH:.*]]13; VF2IC1: [[VECTOR_PH]]:14; VF2IC1-NEXT: br label %[[VECTOR_BODY:.*]]15; VF2IC1: [[VECTOR_BODY]]:16; VF2IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE3:.*]] ]17; VF2IC1-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 118; VF2IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP0]]19; VF2IC1-NEXT: [[WIDE_VEC:%.*]] = load <4 x i64>, ptr [[TMP1]], align 820; VF2IC1-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>21; VF2IC1-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>22; VF2IC1-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC]], <2 x i64> [[STRIDED_VEC1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>23; VF2IC1-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>24; VF2IC1-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP1]], align 825; VF2IC1-NEXT: br i1 [[C]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]26; VF2IC1: [[PRED_STORE_IF]]:27; VF2IC1-NEXT: store i8 1, ptr [[DST_0]], align 128; VF2IC1-NEXT: br label %[[PRED_STORE_CONTINUE]]29; VF2IC1: [[PRED_STORE_CONTINUE]]:30; VF2IC1-NEXT: br i1 [[C]], label %[[PRED_STORE_IF2:.*]], label %[[PRED_STORE_CONTINUE3]]31; VF2IC1: [[PRED_STORE_IF2]]:32; VF2IC1-NEXT: store i8 1, ptr [[DST_0]], align 133; VF2IC1-NEXT: br label %[[PRED_STORE_CONTINUE3]]34; VF2IC1: [[PRED_STORE_CONTINUE3]]:35; VF2IC1-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[DST_1]], i64 [[INDEX]]36; VF2IC1-NEXT: store <2 x i8> zeroinitializer, ptr [[TMP2]], align 137; VF2IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 238; VF2IC1-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10039; VF2IC1-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]40; VF2IC1: [[MIDDLE_BLOCK]]:41; VF2IC1-NEXT: br label %[[EXIT:.*]]42; VF2IC1: [[EXIT]]:43; VF2IC1-NEXT: ret void44;45; VF2IC2-LABEL: define void @load_store_interleave_group_block_invar_cond(46; VF2IC2-SAME: ptr noalias [[DATA:%.*]], ptr noalias [[DST_0:%.*]], ptr noalias [[DST_1:%.*]], i1 [[C:%.*]]) {47; VF2IC2-NEXT: [[ENTRY:.*:]]48; VF2IC2-NEXT: br label %[[VECTOR_PH:.*]]49; VF2IC2: [[VECTOR_PH]]:50; VF2IC2-NEXT: br label %[[VECTOR_BODY:.*]]51; VF2IC2: [[VECTOR_BODY]]:52; VF2IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE11:.*]] ]53; VF2IC2-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 254; VF2IC2-NEXT: [[TMP1:%.*]] = shl nsw i64 [[INDEX]], 155; VF2IC2-NEXT: [[TMP2:%.*]] = shl nsw i64 [[TMP0]], 156; VF2IC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP1]]57; VF2IC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP2]]58; VF2IC2-NEXT: [[WIDE_VEC:%.*]] = load <4 x i64>, ptr [[TMP3]], align 859; VF2IC2-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>60; VF2IC2-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>61; VF2IC2-NEXT: [[WIDE_VEC2:%.*]] = load <4 x i64>, ptr [[TMP4]], align 862; VF2IC2-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <4 x i64> [[WIDE_VEC2]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>63; VF2IC2-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <4 x i64> [[WIDE_VEC2]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>64; VF2IC2-NEXT: [[TMP8:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC]], <2 x i64> [[STRIDED_VEC1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>65; VF2IC2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP8]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>66; VF2IC2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP3]], align 867; VF2IC2-NEXT: [[TMP9:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC3]], <2 x i64> [[STRIDED_VEC4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>68; VF2IC2-NEXT: [[INTERLEAVED_VEC5:%.*]] = shufflevector <4 x i64> [[TMP9]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>69; VF2IC2-NEXT: store <4 x i64> [[INTERLEAVED_VEC5]], ptr [[TMP4]], align 870; VF2IC2-NEXT: br i1 [[C]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]71; VF2IC2: [[PRED_STORE_IF]]:72; VF2IC2-NEXT: store i8 1, ptr [[DST_0]], align 173; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE]]74; VF2IC2: [[PRED_STORE_CONTINUE]]:75; VF2IC2-NEXT: br i1 [[C]], label %[[PRED_STORE_IF6:.*]], label %[[PRED_STORE_CONTINUE7:.*]]76; VF2IC2: [[PRED_STORE_IF6]]:77; VF2IC2-NEXT: store i8 1, ptr [[DST_0]], align 178; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE7]]79; VF2IC2: [[PRED_STORE_CONTINUE7]]:80; VF2IC2-NEXT: br i1 [[C]], label %[[PRED_STORE_IF8:.*]], label %[[PRED_STORE_CONTINUE9:.*]]81; VF2IC2: [[PRED_STORE_IF8]]:82; VF2IC2-NEXT: store i8 1, ptr [[DST_0]], align 183; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE9]]84; VF2IC2: [[PRED_STORE_CONTINUE9]]:85; VF2IC2-NEXT: br i1 [[C]], label %[[PRED_STORE_IF10:.*]], label %[[PRED_STORE_CONTINUE11]]86; VF2IC2: [[PRED_STORE_IF10]]:87; VF2IC2-NEXT: store i8 1, ptr [[DST_0]], align 188; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE11]]89; VF2IC2: [[PRED_STORE_CONTINUE11]]:90; VF2IC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[DST_1]], i64 [[INDEX]]91; VF2IC2-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[TMP5]], i64 292; VF2IC2-NEXT: store <2 x i8> zeroinitializer, ptr [[TMP5]], align 193; VF2IC2-NEXT: store <2 x i8> zeroinitializer, ptr [[TMP6]], align 194; VF2IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 495; VF2IC2-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10096; VF2IC2-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]97; VF2IC2: [[MIDDLE_BLOCK]]:98; VF2IC2-NEXT: br label %[[EXIT:.*]]99; VF2IC2: [[EXIT]]:100; VF2IC2-NEXT: ret void101;102entry:103 br label %loop.header104 105loop.header:106 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]107 %mul.2 = shl nsw i64 %iv, 1108 %data.0 = getelementptr inbounds i64, ptr %data, i64 %mul.2109 %l.0 = load i64, ptr %data.0, align 8110 store i64 %l.0, ptr %data.0, align 8111 %add.1 = or disjoint i64 %mul.2, 1112 %data.1 = getelementptr inbounds i64, ptr %data, i64 %add.1113 %l.1 = load i64, ptr %data.1, align 8114 store i64 %l.1, ptr %data.1, align 8115 br i1 %c, label %then, label %loop.latch116 117then:118 store i8 1, ptr %dst.0119 br label %loop.latch120 121loop.latch:122 %gep.dst.1 = getelementptr inbounds i8, ptr %dst.1, i64 %iv123 store i8 0, ptr %gep.dst.1124 %iv.next = add nuw nsw i64 %iv, 1125 %ec = icmp eq i64 %iv.next, 100126 br i1 %ec, label %exit, label %loop.header127 128exit:129 ret void130}131 132define void @load_store_interleave_group_block_var_cond(ptr noalias %data, ptr %masks, ptr noalias %dst) {133; VF2IC1-LABEL: define void @load_store_interleave_group_block_var_cond(134; VF2IC1-SAME: ptr noalias [[DATA:%.*]], ptr [[MASKS:%.*]], ptr noalias [[DST:%.*]]) {135; VF2IC1-NEXT: [[ENTRY:.*:]]136; VF2IC1-NEXT: br label %[[VECTOR_PH:.*]]137; VF2IC1: [[VECTOR_PH]]:138; VF2IC1-NEXT: br label %[[VECTOR_BODY:.*]]139; VF2IC1: [[VECTOR_BODY]]:140; VF2IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE3:.*]] ]141; VF2IC1-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1142; VF2IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP0]]143; VF2IC1-NEXT: [[WIDE_VEC:%.*]] = load <4 x i64>, ptr [[TMP1]], align 8144; VF2IC1-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>145; VF2IC1-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>146; VF2IC1-NEXT: [[TMP11:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC]], <2 x i64> [[STRIDED_VEC1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>147; VF2IC1-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP11]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>148; VF2IC1-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP1]], align 8149; VF2IC1-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[INDEX]]150; VF2IC1-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x i8>, ptr [[TMP2]], align 1151; VF2IC1-NEXT: [[TMP3:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD1]], zeroinitializer152; VF2IC1-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP3]], i32 0153; VF2IC1-NEXT: br i1 [[TMP4]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]154; VF2IC1: [[PRED_STORE_IF]]:155; VF2IC1-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 0156; VF2IC1-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[TMP5]]157; VF2IC1-NEXT: store i8 1, ptr [[TMP6]], align 1158; VF2IC1-NEXT: br label %[[PRED_STORE_CONTINUE]]159; VF2IC1: [[PRED_STORE_CONTINUE]]:160; VF2IC1-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP3]], i32 1161; VF2IC1-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF2:.*]], label %[[PRED_STORE_CONTINUE3]]162; VF2IC1: [[PRED_STORE_IF2]]:163; VF2IC1-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 1164; VF2IC1-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[TMP8]]165; VF2IC1-NEXT: store i8 1, ptr [[TMP9]], align 1166; VF2IC1-NEXT: br label %[[PRED_STORE_CONTINUE3]]167; VF2IC1: [[PRED_STORE_CONTINUE3]]:168; VF2IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2169; VF2IC1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100170; VF2IC1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]171; VF2IC1: [[MIDDLE_BLOCK]]:172; VF2IC1-NEXT: br label %[[EXIT:.*]]173; VF2IC1: [[EXIT]]:174; VF2IC1-NEXT: ret void175;176; VF2IC2-LABEL: define void @load_store_interleave_group_block_var_cond(177; VF2IC2-SAME: ptr noalias [[DATA:%.*]], ptr [[MASKS:%.*]], ptr noalias [[DST:%.*]]) {178; VF2IC2-NEXT: [[ENTRY:.*:]]179; VF2IC2-NEXT: br label %[[VECTOR_PH:.*]]180; VF2IC2: [[VECTOR_PH]]:181; VF2IC2-NEXT: br label %[[VECTOR_BODY:.*]]182; VF2IC2: [[VECTOR_BODY]]:183; VF2IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE12:.*]] ]184; VF2IC2-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 2185; VF2IC2-NEXT: [[TMP1:%.*]] = shl nsw i64 [[INDEX]], 1186; VF2IC2-NEXT: [[TMP2:%.*]] = shl nsw i64 [[TMP0]], 1187; VF2IC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP1]]188; VF2IC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP2]]189; VF2IC2-NEXT: [[WIDE_VEC:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8190; VF2IC2-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>191; VF2IC2-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>192; VF2IC2-NEXT: [[WIDE_VEC2:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8193; VF2IC2-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <4 x i64> [[WIDE_VEC2]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>194; VF2IC2-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <4 x i64> [[WIDE_VEC2]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>195; VF2IC2-NEXT: [[TMP5:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC]], <2 x i64> [[STRIDED_VEC1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>196; VF2IC2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP5]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>197; VF2IC2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP3]], align 8198; VF2IC2-NEXT: [[TMP6:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC3]], <2 x i64> [[STRIDED_VEC4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>199; VF2IC2-NEXT: [[INTERLEAVED_VEC5:%.*]] = shufflevector <4 x i64> [[TMP6]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>200; VF2IC2-NEXT: store <4 x i64> [[INTERLEAVED_VEC5]], ptr [[TMP4]], align 8201; VF2IC2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[INDEX]]202; VF2IC2-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[TMP7]], i64 2203; VF2IC2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP7]], align 1204; VF2IC2-NEXT: [[WIDE_LOAD6:%.*]] = load <2 x i8>, ptr [[TMP8]], align 1205; VF2IC2-NEXT: [[TMP9:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD]], zeroinitializer206; VF2IC2-NEXT: [[TMP10:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD6]], zeroinitializer207; VF2IC2-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP9]], i32 0208; VF2IC2-NEXT: br i1 [[TMP11]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]209; VF2IC2: [[PRED_STORE_IF]]:210; VF2IC2-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 0211; VF2IC2-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[TMP12]]212; VF2IC2-NEXT: store i8 1, ptr [[TMP13]], align 1213; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE]]214; VF2IC2: [[PRED_STORE_CONTINUE]]:215; VF2IC2-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP9]], i32 1216; VF2IC2-NEXT: br i1 [[TMP14]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]217; VF2IC2: [[PRED_STORE_IF7]]:218; VF2IC2-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 1219; VF2IC2-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[TMP15]]220; VF2IC2-NEXT: store i8 1, ptr [[TMP16]], align 1221; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE8]]222; VF2IC2: [[PRED_STORE_CONTINUE8]]:223; VF2IC2-NEXT: [[TMP17:%.*]] = extractelement <2 x i1> [[TMP10]], i32 0224; VF2IC2-NEXT: br i1 [[TMP17]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]225; VF2IC2: [[PRED_STORE_IF9]]:226; VF2IC2-NEXT: [[TMP18:%.*]] = add i64 [[INDEX]], 2227; VF2IC2-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[TMP18]]228; VF2IC2-NEXT: store i8 1, ptr [[TMP19]], align 1229; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE10]]230; VF2IC2: [[PRED_STORE_CONTINUE10]]:231; VF2IC2-NEXT: [[TMP20:%.*]] = extractelement <2 x i1> [[TMP10]], i32 1232; VF2IC2-NEXT: br i1 [[TMP20]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12]]233; VF2IC2: [[PRED_STORE_IF11]]:234; VF2IC2-NEXT: [[TMP21:%.*]] = add i64 [[INDEX]], 3235; VF2IC2-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[TMP21]]236; VF2IC2-NEXT: store i8 1, ptr [[TMP22]], align 1237; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE12]]238; VF2IC2: [[PRED_STORE_CONTINUE12]]:239; VF2IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4240; VF2IC2-NEXT: [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100241; VF2IC2-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]242; VF2IC2: [[MIDDLE_BLOCK]]:243; VF2IC2-NEXT: br label %[[EXIT:.*]]244; VF2IC2: [[EXIT]]:245; VF2IC2-NEXT: ret void246;247entry:248 br label %loop.header249 250loop.header:251 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]252 %mul.2 = shl nsw i64 %iv, 1253 %data.0 = getelementptr inbounds i64, ptr %data, i64 %mul.2254 %l.0 = load i64, ptr %data.0, align 8255 store i64 %l.0, ptr %data.0, align 8256 %add.1 = or disjoint i64 %mul.2, 1257 %data.1 = getelementptr inbounds i64, ptr %data, i64 %add.1258 %l.1 = load i64, ptr %data.1, align 8259 store i64 %l.1, ptr %data.1, align 8260 %gep.mask = getelementptr inbounds i8, ptr %masks, i64 %iv261 %l.mask = load i8, ptr %gep.mask262 %c = icmp eq i8 %l.mask, 0263 br i1 %c, label %then, label %loop.latch264 265then:266 store i8 1, ptr %gep.mask267 br label %loop.latch268 269loop.latch:270 %iv.next = add nuw nsw i64 %iv, 1271 %ec = icmp eq i64 %iv.next, 100272 br i1 %ec, label %exit, label %loop.header273 274exit:275 ret void276}277