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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=VF2 %s3; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=VF4 %s4 5target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"6target triple = "arm64-apple-macosx"7 8define void @load_store_interleave_group_tc_2(ptr noalias %data) {9; VF2-LABEL: define void @load_store_interleave_group_tc_2(10; VF2-SAME: ptr noalias [[DATA:%.*]]) {11; VF2-NEXT: [[ENTRY:.*:]]12; VF2-NEXT: br label %[[VECTOR_PH:.*]]13; VF2: [[VECTOR_PH]]:14; VF2-NEXT: br label %[[VECTOR_BODY:.*]]15; VF2: [[VECTOR_BODY]]:16; VF2-NEXT: [[WIDE_VEC:%.*]] = load <4 x i64>, ptr [[DATA]], align 817; VF2-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>18; VF2-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>19; VF2-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC]], <2 x i64> [[STRIDED_VEC1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>20; VF2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>21; VF2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[DATA]], align 822; VF2-NEXT: br label %[[MIDDLE_BLOCK:.*]]23; VF2: [[MIDDLE_BLOCK]]:24; VF2-NEXT: br label %[[EXIT:.*]]25; VF2: [[EXIT]]:26; VF2-NEXT: ret void27;28; VF4-LABEL: define void @load_store_interleave_group_tc_2(29; VF4-SAME: ptr noalias [[DATA:%.*]]) {30; VF4-NEXT: [[ENTRY:.*:]]31; VF4-NEXT: br label %[[VECTOR_PH:.*]]32; VF4: [[VECTOR_PH]]:33; VF4-NEXT: br label %[[VECTOR_BODY:.*]]34; VF4: [[VECTOR_BODY]]:35; VF4-NEXT: br i1 true, label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]36; VF4: [[PRED_STORE_IF]]:37; VF4-NEXT: [[TMP3:%.*]] = shl nsw i64 0, 138; VF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP3]]39; VF4-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 840; VF4-NEXT: store i64 [[TMP5]], ptr [[TMP4]], align 841; VF4-NEXT: [[TMP6:%.*]] = or disjoint i64 [[TMP3]], 142; VF4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP6]]43; VF4-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 844; VF4-NEXT: store i64 [[TMP8]], ptr [[TMP7]], align 845; VF4-NEXT: br label %[[PRED_STORE_CONTINUE]]46; VF4: [[PRED_STORE_CONTINUE]]:47; VF4-NEXT: br i1 true, label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]48; VF4: [[PRED_STORE_IF1]]:49; VF4-NEXT: [[TMP11:%.*]] = shl nsw i64 1, 150; VF4-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP11]]51; VF4-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 852; VF4-NEXT: store i64 [[TMP13]], ptr [[TMP12]], align 853; VF4-NEXT: [[TMP14:%.*]] = or disjoint i64 [[TMP11]], 154; VF4-NEXT: [[TMP15:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP14]]55; VF4-NEXT: [[TMP16:%.*]] = load i64, ptr [[TMP15]], align 856; VF4-NEXT: store i64 [[TMP16]], ptr [[TMP15]], align 857; VF4-NEXT: br label %[[PRED_STORE_CONTINUE2]]58; VF4: [[PRED_STORE_CONTINUE2]]:59; VF4-NEXT: br i1 false, label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]60; VF4: [[PRED_STORE_IF3]]:61; VF4-NEXT: [[TMP19:%.*]] = shl nsw i64 2, 162; VF4-NEXT: [[TMP20:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP19]]63; VF4-NEXT: [[TMP21:%.*]] = load i64, ptr [[TMP20]], align 864; VF4-NEXT: store i64 [[TMP21]], ptr [[TMP20]], align 865; VF4-NEXT: [[TMP22:%.*]] = or disjoint i64 [[TMP19]], 166; VF4-NEXT: [[TMP23:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP22]]67; VF4-NEXT: [[TMP24:%.*]] = load i64, ptr [[TMP23]], align 868; VF4-NEXT: store i64 [[TMP24]], ptr [[TMP23]], align 869; VF4-NEXT: br label %[[PRED_STORE_CONTINUE4]]70; VF4: [[PRED_STORE_CONTINUE4]]:71; VF4-NEXT: br i1 false, label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]72; VF4: [[PRED_STORE_IF5]]:73; VF4-NEXT: [[TMP27:%.*]] = shl nsw i64 3, 174; VF4-NEXT: [[DATA_0:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP27]]75; VF4-NEXT: [[L_0:%.*]] = load i64, ptr [[DATA_0]], align 876; VF4-NEXT: store i64 [[L_0]], ptr [[DATA_0]], align 877; VF4-NEXT: [[ADD_1:%.*]] = or disjoint i64 [[TMP27]], 178; VF4-NEXT: [[DATA_1:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[ADD_1]]79; VF4-NEXT: [[L_1:%.*]] = load i64, ptr [[DATA_1]], align 880; VF4-NEXT: store i64 [[L_1]], ptr [[DATA_1]], align 881; VF4-NEXT: br label %[[PRED_STORE_CONTINUE6]]82; VF4: [[PRED_STORE_CONTINUE6]]:83; VF4-NEXT: br label %[[MIDDLE_BLOCK:.*]]84; VF4: [[MIDDLE_BLOCK]]:85; VF4-NEXT: br label %[[EXIT:.*]]86; VF4: [[EXIT]]:87; VF4-NEXT: ret void88;89entry:90 br label %loop91 92loop:93 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]94 %mul.2 = shl nsw i64 %iv, 195 %data.0 = getelementptr inbounds i64, ptr %data, i64 %mul.296 %l.0 = load i64, ptr %data.0, align 897 store i64 %l.0, ptr %data.0, align 898 %add.1 = or disjoint i64 %mul.2, 199 %data.1 = getelementptr inbounds i64, ptr %data, i64 %add.1100 %l.1 = load i64, ptr %data.1, align 8101 store i64 %l.1, ptr %data.1, align 8102 %iv.next = add nuw nsw i64 %iv, 1103 %ec = icmp eq i64 %iv.next, 2104 br i1 %ec, label %exit, label %loop105 106exit:107 ret void108}109 110define void @test_complex_add_float_tc_4(ptr %res, ptr noalias %A, ptr noalias %B) {111; CHECK-LABEL: define void @test_complex_add_float(112; CHECK-SAME: ptr [[RES:%.*]], ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) {113; CHECK-NEXT: [[ENTRY:.*]]:114; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8115; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]116; CHECK: [[VECTOR_PH]]:117; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 8118; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]119; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]120; CHECK: [[VECTOR_BODY]]:121; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]122; CHECK-NEXT: [[IV:%.*]] = add i64 [[INDEX]], 0123; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 4124; CHECK-NEXT: [[GEP_A_0:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[A]], i64 [[IV]]125; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[A]], i64 [[TMP1]]126; CHECK-NEXT: [[GEP_B_0:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[B]], i64 [[IV]]127; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[B]], i64 [[TMP1]]128; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <8 x float>, ptr [[GEP_A_0]], align 4129; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x float> [[WIDE_VEC]], <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>130; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <8 x float> [[WIDE_VEC]], <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>131; CHECK-NEXT: [[WIDE_VEC2:%.*]] = load <8 x float>, ptr [[TMP3]], align 4132; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <8 x float> [[WIDE_VEC2]], <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>133; CHECK-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <8 x float> [[WIDE_VEC2]], <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>134; CHECK-NEXT: [[WIDE_VEC5:%.*]] = load <8 x float>, ptr [[GEP_B_0]], align 4135; CHECK-NEXT: [[STRIDED_VEC6:%.*]] = shufflevector <8 x float> [[WIDE_VEC5]], <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>136; CHECK-NEXT: [[STRIDED_VEC7:%.*]] = shufflevector <8 x float> [[WIDE_VEC5]], <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>137; CHECK-NEXT: [[WIDE_VEC8:%.*]] = load <8 x float>, ptr [[TMP5]], align 4138; CHECK-NEXT: [[STRIDED_VEC9:%.*]] = shufflevector <8 x float> [[WIDE_VEC8]], <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>139; CHECK-NEXT: [[STRIDED_VEC10:%.*]] = shufflevector <8 x float> [[WIDE_VEC8]], <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>140; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[STRIDED_VEC]], [[STRIDED_VEC6]]141; CHECK-NEXT: [[TMP7:%.*]] = fadd <4 x float> [[STRIDED_VEC3]], [[STRIDED_VEC9]]142; CHECK-NEXT: [[TMP8:%.*]] = fadd <4 x float> [[STRIDED_VEC1]], [[STRIDED_VEC7]]143; CHECK-NEXT: [[TMP9:%.*]] = fadd <4 x float> [[STRIDED_VEC4]], [[STRIDED_VEC10]]144; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[RES]], i64 [[IV]]145; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[RES]], i64 [[TMP1]]146; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x float> [[TMP6]], <4 x float> [[TMP8]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>147; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x float> [[TMP12]], <8 x float> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>148; CHECK-NEXT: store <8 x float> [[INTERLEAVED_VEC]], ptr [[TMP10]], align 4149; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x float> [[TMP7]], <4 x float> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>150; CHECK-NEXT: [[INTERLEAVED_VEC11:%.*]] = shufflevector <8 x float> [[TMP13]], <8 x float> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>151; CHECK-NEXT: store <8 x float> [[INTERLEAVED_VEC11]], ptr [[TMP11]], align 4152; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8153; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]154; CHECK-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]155; CHECK: [[MIDDLE_BLOCK]]:156; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]157; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]158; CHECK: [[SCALAR_PH]]:159; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]160; CHECK-NEXT: br label %[[LOOP:.*]]161; CHECK: [[LOOP]]:162; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]163; CHECK-NEXT: [[GEP_A_2:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[A]], i64 [[IV1]]164; CHECK-NEXT: [[GEP_B_2:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[B]], i64 [[IV1]]165; CHECK-NEXT: [[L_A_0:%.*]] = load float, ptr [[GEP_A_2]], align 4166; CHECK-NEXT: [[GEP_A_1:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP_A_2]], i64 4167; CHECK-NEXT: [[L_A_1:%.*]] = load float, ptr [[GEP_A_1]], align 4168; CHECK-NEXT: [[L_B_0:%.*]] = load float, ptr [[GEP_B_2]], align 4169; CHECK-NEXT: [[ADD_0:%.*]] = fadd float [[L_A_0]], [[L_B_0]]170; CHECK-NEXT: [[GEP_B_1:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP_B_2]], i64 4171; CHECK-NEXT: [[L_B_1:%.*]] = load float, ptr [[GEP_B_1]], align 4172; CHECK-NEXT: [[ADD_1:%.*]] = fadd float [[L_A_1]], [[L_B_1]]173; CHECK-NEXT: [[GEP_RES_0:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[RES]], i64 [[IV1]]174; CHECK-NEXT: store float [[ADD_0]], ptr [[GEP_RES_0]], align 4175; CHECK-NEXT: [[GEP_RES_1:%.*]] = getelementptr inbounds nuw i8, ptr [[GEP_RES_0]], i64 4176; CHECK-NEXT: store float [[ADD_1]], ptr [[GEP_RES_1]], align 4177; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1178; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]179; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]180; CHECK: [[EXIT]]:181; CHECK-NEXT: ret void182;183; VF2-LABEL: define void @test_complex_add_float_tc_4(184; VF2-SAME: ptr [[RES:%.*]], ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) {185; VF2-NEXT: [[ENTRY:.*:]]186; VF2-NEXT: br label %[[VECTOR_PH:.*]]187; VF2: [[VECTOR_PH]]:188; VF2-NEXT: br label %[[VECTOR_BODY:.*]]189; VF2: [[VECTOR_BODY]]:190; VF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]191; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[A]], i64 [[INDEX]]192; VF2-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[B]], i64 [[INDEX]]193; VF2-NEXT: [[WIDE_VEC:%.*]] = load <4 x float>, ptr [[TMP1]], align 4194; VF2-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x float> [[WIDE_VEC]], <4 x float> poison, <2 x i32> <i32 0, i32 2>195; VF2-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x float> [[WIDE_VEC]], <4 x float> poison, <2 x i32> <i32 1, i32 3>196; VF2-NEXT: [[WIDE_VEC2:%.*]] = load <4 x float>, ptr [[TMP2]], align 4197; VF2-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <4 x float> [[WIDE_VEC2]], <4 x float> poison, <2 x i32> <i32 0, i32 2>198; VF2-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <4 x float> [[WIDE_VEC2]], <4 x float> poison, <2 x i32> <i32 1, i32 3>199; VF2-NEXT: [[TMP3:%.*]] = fadd <2 x float> [[STRIDED_VEC]], [[STRIDED_VEC3]]200; VF2-NEXT: [[TMP4:%.*]] = fadd <2 x float> [[STRIDED_VEC1]], [[STRIDED_VEC4]]201; VF2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[RES]], i64 [[INDEX]]202; VF2-NEXT: [[TMP6:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>203; VF2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x float> [[TMP6]], <4 x float> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>204; VF2-NEXT: store <4 x float> [[INTERLEAVED_VEC]], ptr [[TMP5]], align 4205; VF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2206; VF2-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4207; VF2-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]208; VF2: [[MIDDLE_BLOCK]]:209; VF2-NEXT: br label %[[EXIT:.*]]210; VF2: [[EXIT]]:211; VF2-NEXT: ret void212;213; VF4-LABEL: define void @test_complex_add_float_tc_4(214; VF4-SAME: ptr [[RES:%.*]], ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) {215; VF4-NEXT: [[ENTRY:.*:]]216; VF4-NEXT: br label %[[VECTOR_PH:.*]]217; VF4: [[VECTOR_PH]]:218; VF4-NEXT: br label %[[VECTOR_BODY:.*]]219; VF4: [[VECTOR_BODY]]:220; VF4-NEXT: [[WIDE_VEC:%.*]] = load <8 x float>, ptr [[A]], align 4221; VF4-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x float> [[WIDE_VEC]], <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>222; VF4-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <8 x float> [[WIDE_VEC]], <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>223; VF4-NEXT: [[WIDE_VEC2:%.*]] = load <8 x float>, ptr [[B]], align 4224; VF4-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <8 x float> [[WIDE_VEC2]], <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>225; VF4-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <8 x float> [[WIDE_VEC2]], <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>226; VF4-NEXT: [[TMP2:%.*]] = fadd <4 x float> [[STRIDED_VEC]], [[STRIDED_VEC3]]227; VF4-NEXT: [[TMP3:%.*]] = fadd <4 x float> [[STRIDED_VEC1]], [[STRIDED_VEC4]]228; VF4-NEXT: [[TMP5:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>229; VF4-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x float> [[TMP5]], <8 x float> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>230; VF4-NEXT: store <8 x float> [[INTERLEAVED_VEC]], ptr [[RES]], align 4231; VF4-NEXT: br label %[[MIDDLE_BLOCK:.*]]232; VF4: [[MIDDLE_BLOCK]]:233; VF4-NEXT: br label %[[EXIT:.*]]234; VF4: [[EXIT]]:235; VF4-NEXT: ret void236;237entry:238 br label %loop239 240loop:241 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]242 %gep.A.0 = getelementptr inbounds nuw { float, float }, ptr %A, i64 %iv243 %gep.B.0 = getelementptr inbounds nuw { float, float }, ptr %B, i64 %iv244 %l.A.0 = load float, ptr %gep.A.0, align 4245 %gep.A.1 = getelementptr inbounds nuw i8, ptr %gep.A.0, i64 4246 %l.A.1 = load float, ptr %gep.A.1, align 4247 %l.B.0 = load float, ptr %gep.B.0, align 4248 %add.0 = fadd float %l.A.0, %l.B.0249 %gep.B.1 = getelementptr inbounds nuw i8, ptr %gep.B.0, i64 4250 %l.B.1 = load float, ptr %gep.B.1, align 4251 %add.1 = fadd float %l.A.1, %l.B.1252 %gep.res.0 = getelementptr inbounds nuw { float, float }, ptr %res, i64 %iv253 store float %add.0, ptr %gep.res.0, align 4254 %gep.res.1 = getelementptr inbounds nuw i8, ptr %gep.res.0, i64 4255 store float %add.1, ptr %gep.res.1, align 4256 %iv.next = add nuw nsw i64 %iv, 1257 %ec = icmp eq i64 %iv.next, 4258 br i1 %ec, label %exit, label %loop259 260exit:261 ret void262}263