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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=2 -S %s | FileCheck %s3 4target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"5target triple = "arm64-apple-macosx"6 7define void @load_store_interleave_group(ptr noalias %data) {8; CHECK-LABEL: define void @load_store_interleave_group(9; CHECK-SAME: ptr noalias [[DATA:%.*]]) {10; CHECK-NEXT: [[ENTRY:.*:]]11; CHECK-NEXT: br label %[[VECTOR_PH:.*]]12; CHECK: [[VECTOR_PH]]:13; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]14; CHECK: [[VECTOR_BODY]]:15; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]16; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 117; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i64 [[INDEX]], 118; CHECK-NEXT: [[TMP3:%.*]] = shl nsw i64 [[TMP1]], 119; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP2]]20; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP3]]21; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP4]], align 822; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x i64>, ptr [[TMP5]], align 823; CHECK-NEXT: store <2 x i64> [[WIDE_LOAD]], ptr [[TMP4]], align 824; CHECK-NEXT: store <2 x i64> [[WIDE_LOAD1]], ptr [[TMP5]], align 825; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 226; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10027; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]28; CHECK: [[MIDDLE_BLOCK]]:29; CHECK-NEXT: br label %[[EXIT:.*]]30; CHECK: [[EXIT]]:31; CHECK-NEXT: ret void32;33entry:34 br label %loop35 36loop:37 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]38 %mul.2 = shl nsw i64 %iv, 139 %data.0 = getelementptr inbounds i64, ptr %data, i64 %mul.240 %l.0 = load i64, ptr %data.0, align 841 store i64 %l.0, ptr %data.0, align 842 %add.1 = or disjoint i64 %mul.2, 143 %data.1 = getelementptr inbounds i64, ptr %data, i64 %add.144 %l.1 = load i64, ptr %data.1, align 845 store i64 %l.1, ptr %data.1, align 846 %iv.next = add nuw nsw i64 %iv, 147 %ec = icmp eq i64 %iv.next, 10048 br i1 %ec, label %exit, label %loop49 50exit:51 ret void52}53 54define void @test_2xi64_with_wide_load(ptr noalias %data, ptr noalias %factor) {55; CHECK-LABEL: define void @test_2xi64_with_wide_load(56; CHECK-SAME: ptr noalias [[DATA:%.*]], ptr noalias [[FACTOR:%.*]]) {57; CHECK-NEXT: [[ENTRY:.*:]]58; CHECK-NEXT: br label %[[VECTOR_PH:.*]]59; CHECK: [[VECTOR_PH]]:60; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]61; CHECK: [[VECTOR_BODY]]:62; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]63; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 264; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[FACTOR]], i64 [[INDEX]]65; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 266; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = load <2 x i64>, ptr [[TMP1]], align 867; CHECK-NEXT: [[BROADCAST_SPLAT3:%.*]] = load <2 x i64>, ptr [[TMP3]], align 868; CHECK-NEXT: [[TMP6:%.*]] = shl nsw i64 [[INDEX]], 169; CHECK-NEXT: [[TMP7:%.*]] = shl nsw i64 [[TMP0]], 170; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP6]]71; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP7]]72; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x i64>, ptr [[TMP8]], align 873; CHECK-NEXT: [[WIDE_LOAD:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>74; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>75; CHECK-NEXT: [[WIDE_VEC3:%.*]] = load <4 x i64>, ptr [[TMP9]], align 876; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = shufflevector <4 x i64> [[WIDE_VEC3]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>77; CHECK-NEXT: [[STRIDED_VEC5:%.*]] = shufflevector <4 x i64> [[WIDE_VEC3]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>78; CHECK-NEXT: [[TMP10:%.*]] = mul <2 x i64> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]79; CHECK-NEXT: [[TMP11:%.*]] = mul <2 x i64> [[BROADCAST_SPLAT3]], [[WIDE_LOAD1]]80; CHECK-NEXT: [[TMP15:%.*]] = mul <2 x i64> [[BROADCAST_SPLAT]], [[STRIDED_VEC2]]81; CHECK-NEXT: [[TMP16:%.*]] = mul <2 x i64> [[BROADCAST_SPLAT3]], [[STRIDED_VEC5]]82; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <2 x i64> [[TMP10]], <2 x i64> [[TMP15]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>83; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP17]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>84; CHECK-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP8]], align 885; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <2 x i64> [[TMP11]], <2 x i64> [[TMP16]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>86; CHECK-NEXT: [[INTERLEAVED_VEC6:%.*]] = shufflevector <4 x i64> [[TMP18]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>87; CHECK-NEXT: store <4 x i64> [[INTERLEAVED_VEC6]], ptr [[TMP9]], align 888; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 489; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10090; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]91; CHECK: [[MIDDLE_BLOCK]]:92; CHECK-NEXT: br label %[[EXIT:.*]]93; CHECK: [[EXIT]]:94; CHECK-NEXT: ret void95;96entry:97 br label %loop98 99loop:100 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]101 %arrayidx = getelementptr inbounds i64, ptr %factor, i64 %iv102 %l.factor = load i64, ptr %arrayidx, align 8103 %1 = shl nsw i64 %iv, 1104 %data.0 = getelementptr inbounds i64, ptr %data, i64 %1105 %l.0 = load i64, ptr %data.0, align 8106 %mul.0 = mul i64 %l.factor, %l.0107 store i64 %mul.0, ptr %data.0, align 8108 %3 = or disjoint i64 %1, 1109 %data.1 = getelementptr inbounds i64, ptr %data, i64 %3110 %l.1 = load i64, ptr %data.1, align 8111 %mul.1 = mul i64 %l.factor, %l.1112 store i64 %mul.1, ptr %data.1, align 8113 %iv.next = add nuw nsw i64 %iv, 1114 %ec = icmp eq i64 %iv.next, 100115 br i1 %ec, label %exit, label %loop116 117exit:118 ret void119}120