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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "^scalar.ph:" --version 52; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=VF2 %s3; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=VF4 %s4 5target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"6target triple = "arm64-apple-macosx"7 8define void @test_2xi64_matching_zext_interleave_group(ptr noalias %dst, ptr %src) {9; VF2-LABEL: define void @test_2xi64_matching_zext_interleave_group(10; VF2-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {11; VF2-NEXT: [[ENTRY:.*:]]12; VF2-NEXT: br label %[[VECTOR_PH:.*]]13; VF2: [[VECTOR_PH]]:14; VF2-NEXT: br label %[[VECTOR_BODY:.*]]15; VF2: [[VECTOR_BODY]]:16; VF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]17; VF2-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 118; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]19; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 820; VF2-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[WIDE_LOAD]] to <2 x i64>21; VF2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]22; VF2-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>23; VF2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>24; VF2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP3]], align 825; VF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 226; VF2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10027; VF2-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]28; VF2: [[MIDDLE_BLOCK]]:29; VF2-NEXT: br label %[[EXIT:.*]]30; VF2: [[EXIT]]:31; VF2-NEXT: ret void32;33; VF4-LABEL: define void @test_2xi64_matching_zext_interleave_group(34; VF4-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {35; VF4-NEXT: [[ENTRY:.*:]]36; VF4-NEXT: br label %[[VECTOR_PH:.*]]37; VF4: [[VECTOR_PH]]:38; VF4-NEXT: br label %[[VECTOR_BODY:.*]]39; VF4: [[VECTOR_BODY]]:40; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]41; VF4-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 142; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]43; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 844; VF4-NEXT: [[TMP2:%.*]] = zext <4 x i32> [[WIDE_LOAD]] to <4 x i64>45; VF4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]46; VF4-NEXT: [[TMP4:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>47; VF4-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x i64> [[TMP4]], <8 x i64> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>48; VF4-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP3]], align 849; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 450; VF4-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10051; VF4-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]52; VF4: [[MIDDLE_BLOCK]]:53; VF4-NEXT: br label %[[EXIT:.*]]54; VF4: [[EXIT]]:55; VF4-NEXT: ret void56;57entry:58 br label %loop59 60loop:61 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]62 %idx.0 = shl nsw i64 %iv, 163 %gep.src.0 = getelementptr inbounds i32, ptr %src, i64 %iv64 %l.0 = load i32 , ptr %gep.src.0, align 865 %ext.0 = zext i32 %l.0 to i6466 %dst.0 = getelementptr inbounds i64, ptr %dst, i64 %idx.067 store i64 %ext.0, ptr %dst.0, align 868 %idx.1 = add i64 %idx.0, 169 %dst.1 = getelementptr inbounds i64, ptr %dst, i64 %idx.170 %ext.1 = zext i32 %l.0 to i6471 store i64 %ext.1, ptr %dst.1, align 872 %iv.next = add nuw nsw i64 %iv, 173 %ec = icmp eq i64 %iv.next, 10074 br i1 %ec, label %exit, label %loop75 76exit:77 ret void78}79 80define void @test_2xi64_matching_sext_interleave_group(ptr noalias %dst, ptr %src) {81; VF2-LABEL: define void @test_2xi64_matching_sext_interleave_group(82; VF2-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {83; VF2-NEXT: [[ENTRY:.*:]]84; VF2-NEXT: br label %[[VECTOR_PH:.*]]85; VF2: [[VECTOR_PH]]:86; VF2-NEXT: br label %[[VECTOR_BODY:.*]]87; VF2: [[VECTOR_BODY]]:88; VF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]89; VF2-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 190; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]91; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 892; VF2-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[WIDE_LOAD]] to <2 x i64>93; VF2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]94; VF2-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>95; VF2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>96; VF2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP3]], align 897; VF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 298; VF2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10099; VF2-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]100; VF2: [[MIDDLE_BLOCK]]:101; VF2-NEXT: br label %[[EXIT:.*]]102; VF2: [[EXIT]]:103; VF2-NEXT: ret void104;105; VF4-LABEL: define void @test_2xi64_matching_sext_interleave_group(106; VF4-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {107; VF4-NEXT: [[ENTRY:.*:]]108; VF4-NEXT: br label %[[VECTOR_PH:.*]]109; VF4: [[VECTOR_PH]]:110; VF4-NEXT: br label %[[VECTOR_BODY:.*]]111; VF4: [[VECTOR_BODY]]:112; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]113; VF4-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1114; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]115; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 8116; VF4-NEXT: [[TMP2:%.*]] = sext <4 x i32> [[WIDE_LOAD]] to <4 x i64>117; VF4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]118; VF4-NEXT: [[TMP4:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>119; VF4-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x i64> [[TMP4]], <8 x i64> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>120; VF4-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP3]], align 8121; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4122; VF4-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100123; VF4-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]124; VF4: [[MIDDLE_BLOCK]]:125; VF4-NEXT: br label %[[EXIT:.*]]126; VF4: [[EXIT]]:127; VF4-NEXT: ret void128;129entry:130 br label %loop131 132loop:133 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]134 %idx.0 = shl nsw i64 %iv, 1135 %gep.src.0 = getelementptr inbounds i32, ptr %src, i64 %iv136 %l.0 = load i32 , ptr %gep.src.0, align 8137 %ext.0 = sext i32 %l.0 to i64138 %dst.0 = getelementptr inbounds i64, ptr %dst, i64 %idx.0139 store i64 %ext.0, ptr %dst.0, align 8140 %idx.1 = add i64 %idx.0, 1141 %dst.1 = getelementptr inbounds i64, ptr %dst, i64 %idx.1142 %ext.1 = sext i32 %l.0 to i64143 store i64 %ext.1, ptr %dst.1, align 8144 %iv.next = add nuw nsw i64 %iv, 1145 %ec = icmp eq i64 %iv.next, 100146 br i1 %ec, label %exit, label %loop147 148exit:149 ret void150}151 152define void @test_2xi64_mismatching_cast_interleave_group(ptr noalias %dst, ptr %src) {153; VF2-LABEL: define void @test_2xi64_mismatching_cast_interleave_group(154; VF2-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {155; VF2-NEXT: [[ENTRY:.*:]]156; VF2-NEXT: br label %[[VECTOR_PH:.*]]157; VF2: [[VECTOR_PH]]:158; VF2-NEXT: br label %[[VECTOR_BODY:.*]]159; VF2: [[VECTOR_BODY]]:160; VF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]161; VF2-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1162; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]163; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 8164; VF2-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[WIDE_LOAD]] to <2 x i64>165; VF2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]166; VF2-NEXT: [[TMP4:%.*]] = sext <2 x i32> [[WIDE_LOAD]] to <2 x i64>167; VF2-NEXT: [[TMP5:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>168; VF2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP5]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>169; VF2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP3]], align 8170; VF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2171; VF2-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100172; VF2-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]173; VF2: [[MIDDLE_BLOCK]]:174; VF2-NEXT: br label %[[EXIT:.*]]175; VF2: [[EXIT]]:176; VF2-NEXT: ret void177;178; VF4-LABEL: define void @test_2xi64_mismatching_cast_interleave_group(179; VF4-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {180; VF4-NEXT: [[ENTRY:.*:]]181; VF4-NEXT: br label %[[VECTOR_PH:.*]]182; VF4: [[VECTOR_PH]]:183; VF4-NEXT: br label %[[VECTOR_BODY:.*]]184; VF4: [[VECTOR_BODY]]:185; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]186; VF4-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1187; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]188; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 8189; VF4-NEXT: [[TMP2:%.*]] = zext <4 x i32> [[WIDE_LOAD]] to <4 x i64>190; VF4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]191; VF4-NEXT: [[TMP4:%.*]] = sext <4 x i32> [[WIDE_LOAD]] to <4 x i64>192; VF4-NEXT: [[TMP5:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> [[TMP4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>193; VF4-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x i64> [[TMP5]], <8 x i64> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>194; VF4-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP3]], align 8195; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4196; VF4-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100197; VF4-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]198; VF4: [[MIDDLE_BLOCK]]:199; VF4-NEXT: br label %[[EXIT:.*]]200; VF4: [[EXIT]]:201; VF4-NEXT: ret void202;203entry:204 br label %loop205 206loop:207 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]208 %idx.0 = shl nsw i64 %iv, 1209 %gep.src.0 = getelementptr inbounds i32, ptr %src, i64 %iv210 %l.0 = load i32 , ptr %gep.src.0, align 8211 %ext.0 = zext i32 %l.0 to i64212 %dst.0 = getelementptr inbounds i64, ptr %dst, i64 %idx.0213 store i64 %ext.0, ptr %dst.0, align 8214 %idx.1 = add i64 %idx.0, 1215 %dst.1 = getelementptr inbounds i64, ptr %dst, i64 %idx.1216 %ext.1 = sext i32 %l.0 to i64217 store i64 %ext.1, ptr %dst.1, align 8218 %iv.next = add nuw nsw i64 %iv, 1219 %ec = icmp eq i64 %iv.next, 100220 br i1 %ec, label %exit, label %loop221 222exit:223 ret void224}225 226define void @test_2xi64_matching_cast_add_interleave_group(ptr noalias %dst, ptr %src) {227; VF2-LABEL: define void @test_2xi64_matching_cast_add_interleave_group(228; VF2-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {229; VF2-NEXT: [[ENTRY:.*:]]230; VF2-NEXT: br label %[[VECTOR_PH:.*]]231; VF2: [[VECTOR_PH]]:232; VF2-NEXT: br label %[[VECTOR_BODY:.*]]233; VF2: [[VECTOR_BODY]]:234; VF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]235; VF2-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1236; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]237; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 8238; VF2-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[WIDE_LOAD]] to <2 x i64>239; VF2-NEXT: [[TMP3:%.*]] = add <2 x i64> [[TMP2]], splat (i64 2)240; VF2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]241; VF2-NEXT: [[TMP5:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>242; VF2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP5]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>243; VF2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8244; VF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2245; VF2-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100246; VF2-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]247; VF2: [[MIDDLE_BLOCK]]:248; VF2-NEXT: br label %[[EXIT:.*]]249; VF2: [[EXIT]]:250; VF2-NEXT: ret void251;252; VF4-LABEL: define void @test_2xi64_matching_cast_add_interleave_group(253; VF4-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {254; VF4-NEXT: [[ENTRY:.*:]]255; VF4-NEXT: br label %[[VECTOR_PH:.*]]256; VF4: [[VECTOR_PH]]:257; VF4-NEXT: br label %[[VECTOR_BODY:.*]]258; VF4: [[VECTOR_BODY]]:259; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]260; VF4-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1261; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]262; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 8263; VF4-NEXT: [[TMP2:%.*]] = zext <4 x i32> [[WIDE_LOAD]] to <4 x i64>264; VF4-NEXT: [[TMP3:%.*]] = add <4 x i64> [[TMP2]], splat (i64 2)265; VF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]266; VF4-NEXT: [[TMP5:%.*]] = shufflevector <4 x i64> [[TMP3]], <4 x i64> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>267; VF4-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x i64> [[TMP5]], <8 x i64> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>268; VF4-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8269; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4270; VF4-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100271; VF4-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]272; VF4: [[MIDDLE_BLOCK]]:273; VF4-NEXT: br label %[[EXIT:.*]]274; VF4: [[EXIT]]:275; VF4-NEXT: ret void276;277entry:278 br label %loop279 280loop:281 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]282 %idx.0 = shl nsw i64 %iv, 1283 %gep.src.0 = getelementptr inbounds i32, ptr %src, i64 %iv284 %l.0 = load i32 , ptr %gep.src.0, align 8285 %ext.0 = zext i32 %l.0 to i64286 %add.0 = add i64 %ext.0, 2287 %dst.0 = getelementptr inbounds i64, ptr %dst, i64 %idx.0288 store i64 %add.0, ptr %dst.0, align 8289 %idx.1 = add i64 %idx.0, 1290 %dst.1 = getelementptr inbounds i64, ptr %dst, i64 %idx.1291 %ext.1 = zext i32 %l.0 to i64292 %add.1 = add i64 %ext.1, 2293 store i64 %add.1, ptr %dst.1, align 8294 %iv.next = add nuw nsw i64 %iv, 1295 %ec = icmp eq i64 %iv.next, 100296 br i1 %ec, label %exit, label %loop297 298exit:299 ret void300}301 302define void @test_2xi64_mismatching_cast_add_interleave_group(ptr noalias %dst, ptr %src) {303; VF2-LABEL: define void @test_2xi64_mismatching_cast_add_interleave_group(304; VF2-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {305; VF2-NEXT: [[ENTRY:.*:]]306; VF2-NEXT: br label %[[VECTOR_PH:.*]]307; VF2: [[VECTOR_PH]]:308; VF2-NEXT: br label %[[VECTOR_BODY:.*]]309; VF2: [[VECTOR_BODY]]:310; VF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]311; VF2-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1312; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]313; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 8314; VF2-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[WIDE_LOAD]] to <2 x i64>315; VF2-NEXT: [[TMP3:%.*]] = add <2 x i64> [[TMP2]], splat (i64 2)316; VF2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]317; VF2-NEXT: [[TMP5:%.*]] = zext <2 x i32> [[WIDE_LOAD]] to <2 x i64>318; VF2-NEXT: [[TMP6:%.*]] = add <2 x i64> [[TMP5]], splat (i64 2)319; VF2-NEXT: [[TMP7:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>320; VF2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP7]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>321; VF2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8322; VF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2323; VF2-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100324; VF2-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]325; VF2: [[MIDDLE_BLOCK]]:326; VF2-NEXT: br label %[[EXIT:.*]]327; VF2: [[EXIT]]:328; VF2-NEXT: ret void329;330; VF4-LABEL: define void @test_2xi64_mismatching_cast_add_interleave_group(331; VF4-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {332; VF4-NEXT: [[ENTRY:.*:]]333; VF4-NEXT: br label %[[VECTOR_PH:.*]]334; VF4: [[VECTOR_PH]]:335; VF4-NEXT: br label %[[VECTOR_BODY:.*]]336; VF4: [[VECTOR_BODY]]:337; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]338; VF4-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1339; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]340; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 8341; VF4-NEXT: [[TMP2:%.*]] = sext <4 x i32> [[WIDE_LOAD]] to <4 x i64>342; VF4-NEXT: [[TMP3:%.*]] = add <4 x i64> [[TMP2]], splat (i64 2)343; VF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]344; VF4-NEXT: [[TMP5:%.*]] = zext <4 x i32> [[WIDE_LOAD]] to <4 x i64>345; VF4-NEXT: [[TMP6:%.*]] = add <4 x i64> [[TMP5]], splat (i64 2)346; VF4-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[TMP3]], <4 x i64> [[TMP6]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>347; VF4-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x i64> [[TMP7]], <8 x i64> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>348; VF4-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8349; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4350; VF4-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100351; VF4-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]352; VF4: [[MIDDLE_BLOCK]]:353; VF4-NEXT: br label %[[EXIT:.*]]354; VF4: [[EXIT]]:355; VF4-NEXT: ret void356;357entry:358 br label %loop359 360loop:361 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]362 %idx.0 = shl nsw i64 %iv, 1363 %gep.src.0 = getelementptr inbounds i32, ptr %src, i64 %iv364 %l.0 = load i32 , ptr %gep.src.0, align 8365 %ext.0 = sext i32 %l.0 to i64366 %add.0 = add i64 %ext.0, 2367 %dst.0 = getelementptr inbounds i64, ptr %dst, i64 %idx.0368 store i64 %add.0, ptr %dst.0, align 8369 %idx.1 = add i64 %idx.0, 1370 %dst.1 = getelementptr inbounds i64, ptr %dst, i64 %idx.1371 %ext.1 = zext i32 %l.0 to i64372 %add.1 = add i64 %ext.1, 2373 store i64 %add.1, ptr %dst.1, align 8374 %iv.next = add nuw nsw i64 %iv, 1375 %ec = icmp eq i64 %iv.next, 100376 br i1 %ec, label %exit, label %loop377 378exit:379 ret void380}381 382define void @test_2xi64_add_cast_interleave_group(ptr noalias %dst, ptr %src) {383; VF2-LABEL: define void @test_2xi64_add_cast_interleave_group(384; VF2-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {385; VF2-NEXT: [[ENTRY:.*:]]386; VF2-NEXT: br label %[[VECTOR_PH:.*]]387; VF2: [[VECTOR_PH]]:388; VF2-NEXT: br label %[[VECTOR_BODY:.*]]389; VF2: [[VECTOR_BODY]]:390; VF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]391; VF2-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1392; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]393; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 8394; VF2-NEXT: [[TMP2:%.*]] = add <2 x i32> [[WIDE_LOAD]], splat (i32 2)395; VF2-NEXT: [[TMP3:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64>396; VF2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]397; VF2-NEXT: [[TMP5:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>398; VF2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP5]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>399; VF2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8400; VF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2401; VF2-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100402; VF2-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]403; VF2: [[MIDDLE_BLOCK]]:404; VF2-NEXT: br label %[[EXIT:.*]]405; VF2: [[EXIT]]:406; VF2-NEXT: ret void407;408; VF4-LABEL: define void @test_2xi64_add_cast_interleave_group(409; VF4-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {410; VF4-NEXT: [[ENTRY:.*:]]411; VF4-NEXT: br label %[[VECTOR_PH:.*]]412; VF4: [[VECTOR_PH]]:413; VF4-NEXT: br label %[[VECTOR_BODY:.*]]414; VF4: [[VECTOR_BODY]]:415; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]416; VF4-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1417; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]418; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 8419; VF4-NEXT: [[TMP2:%.*]] = add <4 x i32> [[WIDE_LOAD]], splat (i32 2)420; VF4-NEXT: [[TMP3:%.*]] = zext <4 x i32> [[TMP2]] to <4 x i64>421; VF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]422; VF4-NEXT: [[TMP5:%.*]] = shufflevector <4 x i64> [[TMP3]], <4 x i64> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>423; VF4-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x i64> [[TMP5]], <8 x i64> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>424; VF4-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8425; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4426; VF4-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100427; VF4-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]428; VF4: [[MIDDLE_BLOCK]]:429; VF4-NEXT: br label %[[EXIT:.*]]430; VF4: [[EXIT]]:431; VF4-NEXT: ret void432;433entry:434 br label %loop435 436loop:437 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]438 %idx.0 = shl nsw i64 %iv, 1439 %gep.src.0 = getelementptr inbounds i32, ptr %src, i64 %iv440 %l.0 = load i32 , ptr %gep.src.0, align 8441 %add.0 = add i32 %l.0, 2442 %ext.0 = zext i32 %add.0 to i64443 %dst.0 = getelementptr inbounds i64, ptr %dst, i64 %idx.0444 store i64 %ext.0, ptr %dst.0, align 8445 %idx.1 = add i64 %idx.0, 1446 %add.1 = add i32 %l.0, 2447 %ext.1 = zext i32 %add.1 to i64448 %dst.1 = getelementptr inbounds i64, ptr %dst, i64 %idx.1449 store i64 %ext.1, ptr %dst.1, align 8450 %iv.next = add nuw nsw i64 %iv, 1451 %ec = icmp eq i64 %iv.next, 100452 br i1 %ec, label %exit, label %loop453 454exit:455 ret void456}457 458define void @test_2xi64_mismatching_add_cast_interleave_group(ptr noalias %dst, ptr %src) {459; VF2-LABEL: define void @test_2xi64_mismatching_add_cast_interleave_group(460; VF2-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {461; VF2-NEXT: [[ENTRY:.*:]]462; VF2-NEXT: br label %[[VECTOR_PH:.*]]463; VF2: [[VECTOR_PH]]:464; VF2-NEXT: br label %[[VECTOR_BODY:.*]]465; VF2: [[VECTOR_BODY]]:466; VF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]467; VF2-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1468; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]469; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 8470; VF2-NEXT: [[TMP2:%.*]] = add <2 x i32> [[WIDE_LOAD]], splat (i32 2)471; VF2-NEXT: [[TMP3:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64>472; VF2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]473; VF2-NEXT: [[TMP5:%.*]] = sub <2 x i32> [[WIDE_LOAD]], splat (i32 2)474; VF2-NEXT: [[TMP6:%.*]] = zext <2 x i32> [[TMP5]] to <2 x i64>475; VF2-NEXT: [[TMP7:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>476; VF2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP7]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>477; VF2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8478; VF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2479; VF2-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100480; VF2-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]481; VF2: [[MIDDLE_BLOCK]]:482; VF2-NEXT: br label %[[EXIT:.*]]483; VF2: [[EXIT]]:484; VF2-NEXT: ret void485;486; VF4-LABEL: define void @test_2xi64_mismatching_add_cast_interleave_group(487; VF4-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {488; VF4-NEXT: [[ENTRY:.*:]]489; VF4-NEXT: br label %[[VECTOR_PH:.*]]490; VF4: [[VECTOR_PH]]:491; VF4-NEXT: br label %[[VECTOR_BODY:.*]]492; VF4: [[VECTOR_BODY]]:493; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]494; VF4-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1495; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]496; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 8497; VF4-NEXT: [[TMP2:%.*]] = add <4 x i32> [[WIDE_LOAD]], splat (i32 2)498; VF4-NEXT: [[TMP3:%.*]] = zext <4 x i32> [[TMP2]] to <4 x i64>499; VF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]500; VF4-NEXT: [[TMP5:%.*]] = sub <4 x i32> [[WIDE_LOAD]], splat (i32 2)501; VF4-NEXT: [[TMP6:%.*]] = zext <4 x i32> [[TMP5]] to <4 x i64>502; VF4-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[TMP3]], <4 x i64> [[TMP6]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>503; VF4-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x i64> [[TMP7]], <8 x i64> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>504; VF4-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8505; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4506; VF4-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100507; VF4-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]508; VF4: [[MIDDLE_BLOCK]]:509; VF4-NEXT: br label %[[EXIT:.*]]510; VF4: [[EXIT]]:511; VF4-NEXT: ret void512;513entry:514 br label %loop515 516loop:517 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]518 %idx.0 = shl nsw i64 %iv, 1519 %gep.src.0 = getelementptr inbounds i32, ptr %src, i64 %iv520 %l.0 = load i32 , ptr %gep.src.0, align 8521 %add.0 = add i32 %l.0, 2522 %ext.0 = zext i32 %add.0 to i64523 %dst.0 = getelementptr inbounds i64, ptr %dst, i64 %idx.0524 store i64 %ext.0, ptr %dst.0, align 8525 %idx.1 = add i64 %idx.0, 1526 %add.1 = sub i32 %l.0, 2527 %ext.1 = zext i32 %add.1 to i64528 %dst.1 = getelementptr inbounds i64, ptr %dst, i64 %idx.1529 store i64 %ext.1, ptr %dst.1, align 8530 %iv.next = add nuw nsw i64 %iv, 1531 %ec = icmp eq i64 %iv.next, 100532 br i1 %ec, label %exit, label %loop533 534exit:535 ret void536}537 538define void @test_2xi64_add_mismatching_cast_interleave_group(ptr noalias %dst, ptr %src) {539; VF2-LABEL: define void @test_2xi64_add_mismatching_cast_interleave_group(540; VF2-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {541; VF2-NEXT: [[ENTRY:.*:]]542; VF2-NEXT: br label %[[VECTOR_PH:.*]]543; VF2: [[VECTOR_PH]]:544; VF2-NEXT: br label %[[VECTOR_BODY:.*]]545; VF2: [[VECTOR_BODY]]:546; VF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]547; VF2-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1548; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]549; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 8550; VF2-NEXT: [[TMP2:%.*]] = add <2 x i32> [[WIDE_LOAD]], splat (i32 2)551; VF2-NEXT: [[TMP3:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64>552; VF2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]553; VF2-NEXT: [[TMP5:%.*]] = sext <2 x i32> [[TMP2]] to <2 x i64>554; VF2-NEXT: [[TMP6:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>555; VF2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP6]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>556; VF2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8557; VF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2558; VF2-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100559; VF2-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]560; VF2: [[MIDDLE_BLOCK]]:561; VF2-NEXT: br label %[[EXIT:.*]]562; VF2: [[EXIT]]:563; VF2-NEXT: ret void564;565; VF4-LABEL: define void @test_2xi64_add_mismatching_cast_interleave_group(566; VF4-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {567; VF4-NEXT: [[ENTRY:.*:]]568; VF4-NEXT: br label %[[VECTOR_PH:.*]]569; VF4: [[VECTOR_PH]]:570; VF4-NEXT: br label %[[VECTOR_BODY:.*]]571; VF4: [[VECTOR_BODY]]:572; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]573; VF4-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1574; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]575; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 8576; VF4-NEXT: [[TMP2:%.*]] = add <4 x i32> [[WIDE_LOAD]], splat (i32 2)577; VF4-NEXT: [[TMP3:%.*]] = zext <4 x i32> [[TMP2]] to <4 x i64>578; VF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]579; VF4-NEXT: [[TMP5:%.*]] = sext <4 x i32> [[TMP2]] to <4 x i64>580; VF4-NEXT: [[TMP6:%.*]] = shufflevector <4 x i64> [[TMP3]], <4 x i64> [[TMP5]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>581; VF4-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x i64> [[TMP6]], <8 x i64> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>582; VF4-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8583; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4584; VF4-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100585; VF4-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]586; VF4: [[MIDDLE_BLOCK]]:587; VF4-NEXT: br label %[[EXIT:.*]]588; VF4: [[EXIT]]:589; VF4-NEXT: ret void590;591entry:592 br label %loop593 594loop:595 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]596 %idx.0 = shl nsw i64 %iv, 1597 %gep.src.0 = getelementptr inbounds i32, ptr %src, i64 %iv598 %l.0 = load i32 , ptr %gep.src.0, align 8599 %add.0 = add i32 %l.0, 2600 %ext.0 = zext i32 %add.0 to i64601 %dst.0 = getelementptr inbounds i64, ptr %dst, i64 %idx.0602 store i64 %ext.0, ptr %dst.0, align 8603 %idx.1 = add i64 %idx.0, 1604 %add.1 = add i32 %l.0, 2605 %ext.1 = sext i32 %add.1 to i64606 %dst.1 = getelementptr inbounds i64, ptr %dst, i64 %idx.1607 store i64 %ext.1, ptr %dst.1, align 8608 %iv.next = add nuw nsw i64 %iv, 1609 %ec = icmp eq i64 %iv.next, 100610 br i1 %ec, label %exit, label %loop611 612exit:613 ret void614}615 616define void @test_2xi64_sub_mismatching_ops_cast_interleave_group(ptr noalias %dst, ptr %src) {617; VF2-LABEL: define void @test_2xi64_sub_mismatching_ops_cast_interleave_group(618; VF2-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {619; VF2-NEXT: [[ENTRY:.*:]]620; VF2-NEXT: br label %[[VECTOR_PH:.*]]621; VF2: [[VECTOR_PH]]:622; VF2-NEXT: br label %[[VECTOR_BODY:.*]]623; VF2: [[VECTOR_BODY]]:624; VF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]625; VF2-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1626; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]627; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 8628; VF2-NEXT: [[TMP2:%.*]] = sub <2 x i32> [[WIDE_LOAD]], splat (i32 2)629; VF2-NEXT: [[TMP3:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64>630; VF2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]631; VF2-NEXT: [[TMP5:%.*]] = sub <2 x i32> splat (i32 2), [[WIDE_LOAD]]632; VF2-NEXT: [[TMP6:%.*]] = zext <2 x i32> [[TMP5]] to <2 x i64>633; VF2-NEXT: [[TMP7:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>634; VF2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP7]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>635; VF2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8636; VF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2637; VF2-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100638; VF2-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]639; VF2: [[MIDDLE_BLOCK]]:640; VF2-NEXT: br label %[[EXIT:.*]]641; VF2: [[EXIT]]:642; VF2-NEXT: ret void643;644; VF4-LABEL: define void @test_2xi64_sub_mismatching_ops_cast_interleave_group(645; VF4-SAME: ptr noalias [[DST:%.*]], ptr [[SRC:%.*]]) {646; VF4-NEXT: [[ENTRY:.*:]]647; VF4-NEXT: br label %[[VECTOR_PH:.*]]648; VF4: [[VECTOR_PH]]:649; VF4-NEXT: br label %[[VECTOR_BODY:.*]]650; VF4: [[VECTOR_BODY]]:651; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]652; VF4-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1653; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]654; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 8655; VF4-NEXT: [[TMP2:%.*]] = sub <4 x i32> [[WIDE_LOAD]], splat (i32 2)656; VF4-NEXT: [[TMP3:%.*]] = zext <4 x i32> [[TMP2]] to <4 x i64>657; VF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]658; VF4-NEXT: [[TMP5:%.*]] = sub <4 x i32> splat (i32 2), [[WIDE_LOAD]]659; VF4-NEXT: [[TMP6:%.*]] = zext <4 x i32> [[TMP5]] to <4 x i64>660; VF4-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[TMP3]], <4 x i64> [[TMP6]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>661; VF4-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x i64> [[TMP7]], <8 x i64> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>662; VF4-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8663; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4664; VF4-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100665; VF4-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]666; VF4: [[MIDDLE_BLOCK]]:667; VF4-NEXT: br label %[[EXIT:.*]]668; VF4: [[EXIT]]:669; VF4-NEXT: ret void670;671entry:672 br label %loop673 674loop:675 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]676 %idx.0 = shl nsw i64 %iv, 1677 %gep.src.0 = getelementptr inbounds i32, ptr %src, i64 %iv678 %l.0 = load i32 , ptr %gep.src.0, align 8679 %add.0 = sub i32 %l.0, 2680 %ext.0 = zext i32 %add.0 to i64681 %dst.0 = getelementptr inbounds i64, ptr %dst, i64 %idx.0682 store i64 %ext.0, ptr %dst.0, align 8683 %idx.1 = add i64 %idx.0, 1684 %add.1 = sub i32 2, %l.0685 %ext.1 = zext i32 %add.1 to i64686 %dst.1 = getelementptr inbounds i64, ptr %dst, i64 %idx.1687 store i64 %ext.1, ptr %dst.1, align 8688 %iv.next = add nuw nsw i64 %iv, 1689 %ec = icmp eq i64 %iv.next, 100690 br i1 %ec, label %exit, label %loop691 692exit:693 ret void694}695