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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -mcpu=apple-m1 -S %s | FileCheck %s3 4target triple = "arm64-apple-macosx"5 6define void @test_remove_vector_loop_region_epilogue(ptr %dst, i1 %c) {7; CHECK-LABEL: define void @test_remove_vector_loop_region_epilogue(8; CHECK-SAME: ptr [[DST:%.*]], i1 [[C:%.*]]) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: [[ITER_CHECK:.*]]:10; CHECK-NEXT: [[TC:%.*]] = select i1 [[C]], i64 8, i64 011; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TC]], 812; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]13; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:14; CHECK-NEXT: br i1 true, label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]15; CHECK: [[VECTOR_PH]]:16; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TC]], 6417; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TC]], [[N_MOD_VF]]18; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]19; CHECK: [[VECTOR_BODY]]:20; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DST]], i64 1621; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[DST]], i64 3222; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[DST]], i64 4823; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[DST]], align 424; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[TMP2]], align 425; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[TMP3]], align 426; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[TMP4]], align 427; CHECK-NEXT: br label %[[MIDDLE_BLOCK:.*]]28; CHECK: [[MIDDLE_BLOCK]]:29; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TC]], [[N_VEC]]30; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]31; CHECK: [[VEC_EPILOG_ITER_CHECK]]:32; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 833; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF0:![0-9]+]]34; CHECK: [[VEC_EPILOG_PH]]:35; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]36; CHECK-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]]37; CHECK: [[VEC_EPILOG_VECTOR_BODY]]:38; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[DST]], i64 [[VEC_EPILOG_RESUME_VAL]]39; CHECK-NEXT: store <8 x i8> zeroinitializer, ptr [[TMP5]], align 440; CHECK-NEXT: br label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]]41; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]:42; CHECK-NEXT: br i1 true, label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]]43; CHECK: [[VEC_EPILOG_SCALAR_PH]]:44; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TC]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ]45; CHECK-NEXT: br label %[[LOOP:.*]]46; CHECK: [[LOOP]]:47; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]48; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]]49; CHECK-NEXT: store i8 0, ptr [[GEP]], align 450; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 151; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[TC]]52; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP1:![0-9]+]]53; CHECK: [[EXIT]]:54; CHECK-NEXT: ret void55;56entry:57 %tc = select i1 %c, i64 8, i64 058 br label %loop59 60loop:61 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]62 %gep = getelementptr i8, ptr %dst, i64 %iv63 store i8 0, ptr %gep, align 464 %iv.next = add i64 %iv, 165 %ec = icmp eq i64 %iv.next, %tc66 br i1 %ec, label %exit, label %loop67 68exit:69 ret void70}71;.72; CHECK: [[PROF0]] = !{!"branch_weights", i32 8, i32 56}73; CHECK: [[LOOP1]] = distinct !{[[LOOP1]], [[META2:![0-9]+]], [[META3:![0-9]+]]}74; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}75; CHECK: [[META3]] = !{!"llvm.loop.isvectorized", i32 1}76;.77