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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-macosx -S %s | FileCheck %s3 4; Test case for https://github.com/llvm/llvm-project/issues/169668.5define i32 @gep_with_all_invariant_operands(ptr %src.0, ptr %src.1, i64 %n, i1 %cond) #0 {6; CHECK-LABEL: define i32 @gep_with_all_invariant_operands(7; CHECK-SAME: ptr [[SRC_0:%.*]], ptr [[SRC_1:%.*]], i64 [[N:%.*]], i1 [[COND:%.*]]) #[[ATTR0:[0-9]+]] {8; CHECK-NEXT: [[ENTRY:.*:]]9; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 110; CHECK-NEXT: br label %[[VECTOR_PH:.*]]11; CHECK: [[VECTOR_PH]]:12; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()13; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 414; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()15; CHECK-NEXT: [[TMP4:%.*]] = shl nuw i64 [[TMP3]], 216; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP0]], [[TMP4]]17; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[TMP0]], [[TMP4]]18; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i64 [[TMP5]], i64 019; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 [[TMP0]])20; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[SRC_0]], i64 [[N]]21; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[COND]], ptr [[SRC_1]], ptr [[TMP8]]22; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x ptr> poison, ptr [[TMP9]], i64 023; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 4 x ptr> poison, <vscale x 4 x i32> zeroinitializer24; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]25; CHECK: [[VECTOR_BODY]]:26; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]27; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]28; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 [[BROADCAST_SPLAT]], <vscale x 4 x i1> [[ACTIVE_LANE_MASK]], <vscale x 4 x i32> poison)29; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP2]]30; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX]], i64 [[TMP7]])31; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 4 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 032; CHECK-NEXT: [[TMP11:%.*]] = xor i1 [[TMP10]], true33; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]34; CHECK: [[MIDDLE_BLOCK]]:35; CHECK-NEXT: [[TMP12:%.*]] = xor <vscale x 4 x i1> [[ACTIVE_LANE_MASK]], splat (i1 true)36; CHECK-NEXT: [[FIRST_INACTIVE_LANE:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1(<vscale x 4 x i1> [[TMP12]], i1 false)37; CHECK-NEXT: [[LAST_ACTIVE_LANE:%.*]] = sub i64 [[FIRST_INACTIVE_LANE]], 138; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.vscale.i64()39; CHECK-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 440; CHECK-NEXT: [[TMP15:%.*]] = mul i64 [[TMP14]], 041; CHECK-NEXT: [[TMP16:%.*]] = extractelement <vscale x 4 x i32> [[WIDE_MASKED_GATHER]], i64 [[LAST_ACTIVE_LANE]]42; CHECK-NEXT: br label %[[EXIT:.*]]43; CHECK: [[EXIT]]:44; CHECK-NEXT: ret i32 [[TMP16]]45;46entry:47 br label %loop48 49loop:50 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]51 %gep = getelementptr i32, ptr %src.0, i64 %n52 %ptr = select i1 %cond, ptr %src.1, ptr %gep53 %val = load i32, ptr %ptr, align 454 %iv.next = add i64 %iv, 155 %cmp = icmp ult i64 %iv, %n56 br i1 %cmp, label %loop, label %exit, !llvm.loop !057 58exit:59 ret i32 %val60}61 62attributes #0 = { "target-cpu"="neoverse-v2" }63 64!0 = distinct !{!0, !1, !2}65!1 = !{!"llvm.loop.vectorize.enable", i1 true}66!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}67;.68; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}69; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}70; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}71;.72