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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=loop-vectorize -tail-predication=enabled -prefer-predicate-over-epilogue=predicate-dont-vectorize -enable-wide-lane-mask -S | FileCheck %s3 4target triple = "thumbv8.1m.main-arm-unknown-eabihf"5 6define void @f0(ptr noalias %dst, ptr readonly %src, i64 %n) #0 {7; CHECK-LABEL: define void @f0(8; CHECK-SAME: ptr noalias [[DST:%.*]], ptr readonly [[SRC:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: [[ENTRY:.*:]]10; CHECK-NEXT: [[VAL:%.*]] = icmp sgt i64 [[N]], 011; CHECK-NEXT: br i1 [[VAL]], label %[[FOR_BODY_PREHEADER:.*]], label %[[FOR_END:.*]]12; CHECK: [[FOR_BODY_PREHEADER]]:13; CHECK-NEXT: br label %[[VECTOR_PH:.*]]14; CHECK: [[VECTOR_PH]]:15; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[N]], 3116; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 3217; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]18; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]19; CHECK: [[VECTOR_BODY]]:20; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]21; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1622; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 [[INDEX]], i64 [[N]])23; CHECK-NEXT: [[ACTIVE_LANE_MASK1:%.*]] = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 [[TMP0]], i64 [[N]])24; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX]]25; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i32 1626; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 [[TMP1]], <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> poison)27; CHECK-NEXT: [[WIDE_MASKED_LOAD2:%.*]] = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 [[TMP3]], <16 x i1> [[ACTIVE_LANE_MASK1]], <16 x i8> poison)28; CHECK-NEXT: [[TMP4:%.*]] = mul <16 x i8> [[WIDE_MASKED_LOAD]], splat (i8 3)29; CHECK-NEXT: [[TMP5:%.*]] = mul <16 x i8> [[WIDE_MASKED_LOAD2]], splat (i8 3)30; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX]]31; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i32 1632; CHECK-NEXT: call void @llvm.masked.store.v16i8.p0(<16 x i8> [[TMP4]], ptr align 1 [[TMP6]], <16 x i1> [[ACTIVE_LANE_MASK]])33; CHECK-NEXT: call void @llvm.masked.store.v16i8.p0(<16 x i8> [[TMP5]], ptr align 1 [[TMP8]], <16 x i1> [[ACTIVE_LANE_MASK1]])34; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 3235; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]36; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]37; CHECK: [[MIDDLE_BLOCK]]:38; CHECK-NEXT: br label %[[FOR_END_LOOPEXIT:.*]]39; CHECK: [[FOR_END_LOOPEXIT]]:40; CHECK-NEXT: br label %[[FOR_END]]41; CHECK: [[FOR_END]]:42; CHECK-NEXT: ret void43;44entry:45 %val = icmp sgt i64 %n, 046 br i1 %val, label %for.body, label %for.end47 48for.body:49 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]50 %arrayidx = getelementptr inbounds i8, ptr %src, i64 %indvars.iv51 %0 = load i8, ptr %arrayidx, align 152 %mul = mul i8 %0, 353 %arrayidx3 = getelementptr inbounds i8, ptr %dst, i64 %indvars.iv54 store i8 %mul, ptr %arrayidx3, align 155 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 156 %exitcond.not = icmp eq i64 %indvars.iv.next, %n57 br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !158 59for.end:60 ret void61}62 63attributes #0 = { nofree norecurse nounwind "target-features"="+armv8.1-m.main,+mve.fp" }64 65!1 = distinct !{!1, !2, !3}66!2 = !{!"llvm.loop.vectorize.width", i32 16}67!3 = !{!"llvm.loop.interleave.count", i32 2}68;.69; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}70; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}71; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}72;.73