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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; REQUIRES: asserts3; RUN: opt < %s -hoist-runtime-checks -p 'loop-vectorize' -force-vector-interleave=1 -S \4; RUN: -force-vector-width=4 -debug-only=loop-accesses,loop-vectorize,loop-utils 2> %t | FileCheck %s5; RUN: cat %t | FileCheck %s --check-prefix=DEBUG6 7target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"8target triple = "thumbv8.1m.main-none-unknown-eabi"9 10; Equivalent example in C:11; void diff_checks(int32_t *dst, int32_t *src, int m, int n) {12; for (int i = 0; i < m; i++) {13; for (int j = 0; j < n; j++) {14; dst[(i * (n + 1)) + j] = src[(i * n) + j];15; }16; }17; }18; NOTE: The strides of the starting address values in the inner loop differ, i.e.19; '(i * (n + 1))' vs '(i * n)'.20 21; DEBUG-LABEL: 'diff_checks'22; DEBUG: LAA: Found an analyzable loop: inner.loop23; DEBUG: LAA: Not creating diff runtime check, since these cannot be hoisted out of the outer loop24; DEBUG: LAA: Adding RT check for range:25; DEBUG-NEXT: LAA: Expanded RT check for range to include outer loop in order to permit hoisting26; DEBUG-NEXT: LAA: ... but need to check stride is positive: (4 + (4 * %n))27; DEBUG-NEXT: Start: %dst End: ((4 * %n) + ((4 + (4 * %n)) * (-1 + %m)) + %dst)28; DEBUG-NEXT: LAA: Adding RT check for range:29; DEBUG-NEXT: LAA: Expanded RT check for range to include outer loop in order to permit hoisting30; DEBUG-NEXT: LAA: ... but need to check stride is positive: (4 * %n)31; DEBUG-NEXT: Start: %src End: ((4 * %m * %n) + %src)32 33define void @diff_checks(ptr nocapture noundef writeonly %dst, ptr nocapture noundef readonly %src, i32 noundef %m, i32 noundef %n) #0 {34; CHECK-LABEL: define void @diff_checks35; CHECK-SAME: (ptr noundef writeonly captures(none) [[DST:%.*]], ptr noundef readonly captures(none) [[SRC:%.*]], i32 noundef [[M:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {36; CHECK-NEXT: entry:37; CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[N]], 138; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[M]], -139; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[N]], 240; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 441; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP0]], [[TMP2]]42; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], [[TMP1]]43; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i32 [[TMP4]]44; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[N]], [[M]]45; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP5]], 246; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SRC]], i32 [[TMP6]]47; CHECK-NEXT: br label [[OUTER_LOOP:%.*]]48; CHECK: outer.loop:49; CHECK-NEXT: [[I_023_US:%.*]] = phi i32 [ [[INC10_US:%.*]], [[INNER_LOOP_EXIT:%.*]] ], [ 0, [[ENTRY:%.*]] ]50; CHECK-NEXT: [[MUL_US:%.*]] = mul nsw i32 [[I_023_US]], [[N]]51; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[SRC]], i32 [[MUL_US]]52; CHECK-NEXT: [[MUL6_US:%.*]] = mul nsw i32 [[I_023_US]], [[ADD5]]53; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[DST]], i32 [[MUL6_US]]54; CHECK-NEXT: br label [[VECTOR_MEMCHECK:%.*]]55; CHECK: vector.memcheck:56; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP1]]57; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP]]58; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]59; CHECK-NEXT: [[STRIDE_CHECK:%.*]] = icmp slt i32 [[TMP2]], 060; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[FOUND_CONFLICT]], [[STRIDE_CHECK]]61; CHECK-NEXT: [[STRIDE_CHECK2:%.*]] = icmp slt i32 [[TMP1]], 062; CHECK-NEXT: [[TMP10:%.*]] = or i1 [[TMP9]], [[STRIDE_CHECK2]]63; CHECK-NEXT: br i1 [[TMP10]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]64; CHECK: vector.ph:65; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 366; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N_RND_UP]], 467; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N_RND_UP]], [[N_MOD_VF]]68; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]69; CHECK: vector.body:70; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]71; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[INDEX]], i32 [[N]])72; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP7]], i32 [[INDEX]]73; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 [[TMP11]], <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> poison), !alias.scope [[META0:![0-9]+]]74; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP8]], i32 [[INDEX]]75; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[WIDE_MASKED_LOAD]], ptr align 4 [[TMP12]], <4 x i1> [[ACTIVE_LANE_MASK]]), !alias.scope [[META3:![0-9]+]], !noalias [[META0]]76; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 477; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]78; CHECK-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]79; CHECK: middle.block:80; CHECK-NEXT: br label [[INNER_LOOP_EXIT]]81; CHECK: scalar.ph:82; CHECK-NEXT: br label [[INNER_LOOP:%.*]]83; CHECK: inner.loop:84; CHECK-NEXT: [[J_021_US:%.*]] = phi i32 [ 0, [[SCALAR_PH]] ], [ [[INC_US:%.*]], [[INNER_LOOP]] ]85; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr i32, ptr [[TMP7]], i32 [[J_021_US]]86; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX_US]], align 487; CHECK-NEXT: [[ARRAYIDX8_US:%.*]] = getelementptr i32, ptr [[TMP8]], i32 [[J_021_US]]88; CHECK-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX8_US]], align 489; CHECK-NEXT: [[INC_US]] = add nuw nsw i32 [[J_021_US]], 190; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_US]], [[N]]91; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[INNER_LOOP_EXIT]], label [[INNER_LOOP]], !llvm.loop [[LOOP8:![0-9]+]]92; CHECK: inner.loop.exit:93; CHECK-NEXT: [[INC10_US]] = add nuw nsw i32 [[I_023_US]], 194; CHECK-NEXT: [[EXITCOND26_NOT:%.*]] = icmp eq i32 [[INC10_US]], [[M]]95; CHECK-NEXT: br i1 [[EXITCOND26_NOT]], label [[EXIT:%.*]], label [[OUTER_LOOP]]96; CHECK: exit:97; CHECK-NEXT: ret void98;99entry:100 %add5 = add nsw i32 %n, 1101 br label %outer.loop102 103outer.loop:104 %i.023.us = phi i32 [ %inc10.us, %inner.loop.exit ], [ 0, %entry ]105 %mul.us = mul nsw i32 %i.023.us, %n106 %0 = getelementptr i32, ptr %src, i32 %mul.us107 %mul6.us = mul nsw i32 %i.023.us, %add5108 %1 = getelementptr i32, ptr %dst, i32 %mul6.us109 br label %inner.loop110 111inner.loop:112 %j.021.us = phi i32 [ 0, %outer.loop ], [ %inc.us, %inner.loop ]113 %arrayidx.us = getelementptr i32, ptr %0, i32 %j.021.us114 %2 = load i32, ptr %arrayidx.us, align 4115 %arrayidx8.us = getelementptr i32, ptr %1, i32 %j.021.us116 store i32 %2, ptr %arrayidx8.us, align 4117 %inc.us = add nuw nsw i32 %j.021.us, 1118 %exitcond.not = icmp eq i32 %inc.us, %n119 br i1 %exitcond.not, label %inner.loop.exit, label %inner.loop120 121inner.loop.exit:122 %inc10.us = add nuw nsw i32 %i.023.us, 1123 %exitcond26.not = icmp eq i32 %inc10.us, %m124 br i1 %exitcond26.not, label %exit, label %outer.loop125 126exit:127 ret void128}129 130attributes #0 = { "target-cpu"="cortex-m55" }131