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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=loop-vectorize,instcombine,simplifycfg -simplifycfg-require-and-preserve-domtree=1 -tail-predication=enabled -force-vector-interleave=2 < %s -S -o - | FileCheck %s3 4target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"5target triple = "thumbv8.1m.main-arm-none-eabi"6 7; 4x to use VADDLV8define i64 @add_i32_i64(ptr nocapture readonly %x, i32 %n) #0 {9; CHECK-LABEL: @add_i32_i64(10; CHECK-NEXT: entry:11; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N:%.*]], 812; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]13; CHECK: vector.ph:14; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], -815; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]16; CHECK: vector.body:17; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]18; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ]19; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[TMP7:%.*]], [[VECTOR_BODY]] ]20; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i32 [[INDEX]]21; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i32 1622; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 423; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP8]], align 424; CHECK-NEXT: [[TMP1:%.*]] = sext <4 x i32> [[WIDE_LOAD]] to <4 x i64>25; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP1]])26; CHECK-NEXT: [[TMP3]] = add i64 [[VEC_PHI]], [[TMP2]]27; CHECK-NEXT: [[TMP9:%.*]] = sext <4 x i32> [[WIDE_LOAD2]] to <4 x i64>28; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP9]])29; CHECK-NEXT: [[TMP7]] = add i64 [[VEC_PHI1]], [[TMP6]]30; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 831; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]32; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]33; CHECK: middle.block:34; CHECK-NEXT: [[BIN_RDX:%.*]] = add i64 [[TMP7]], [[TMP3]]35; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]36; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]37; CHECK: scalar.ph:38; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER:%.*]] ]39; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[BIN_RDX]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]40; CHECK-NEXT: br label [[FOR_BODY:%.*]]41; CHECK: loop:42; CHECK-NEXT: [[I_08:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]43; CHECK-NEXT: [[R_07:%.*]] = phi i64 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]44; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X]], i32 [[I_08]]45; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 446; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP5]] to i6447; CHECK-NEXT: [[ADD]] = add nsw i64 [[R_07]], [[CONV]]48; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 149; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]50; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]51; CHECK: exit:52; CHECK-NEXT: [[R_0_LCSSA:%.*]] = phi i64 [ [[ADD]], [[FOR_BODY]] ], [ [[BIN_RDX]], [[MIDDLE_BLOCK]] ]53; CHECK-NEXT: ret i64 [[R_0_LCSSA]]54;55entry:56 br label %loop57 58loop:59 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]60 %red = phi i64 [ 0, %entry ], [ %red.next, %loop ]61 %gep.x = getelementptr inbounds i32, ptr %x, i32 %iv62 %0 = load i32, ptr %gep.x, align 463 %conv = sext i32 %0 to i6464 %red.next = add nsw i64 %red, %conv65 %iv.next = add nuw nsw i32 %iv, 166 %ec = icmp eq i32 %iv.next, %n67 br i1 %ec, label %exit, label %loop68 69exit:70 %red.lcssa = phi i64 [ %red.next, %loop ]71 ret i64 %red.lcssa72}73 74; 4x to use VMLAL.u3275define i64 @mla_i32_i64(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) #0 {76; CHECK-LABEL: @mla_i32_i64(77; CHECK-NEXT: entry:78; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N:%.*]], 879; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]80; CHECK: vector.ph:81; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], -882; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]83; CHECK: vector.body:84; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]85; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ]86; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[VECTOR_BODY]] ]87; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i32 [[INDEX]]88; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i32 1689; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 490; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP12]], align 491; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[Y:%.*]], i32 [[INDEX]]92; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i32 1693; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 494; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP13]], align 495; CHECK-NEXT: [[TMP2:%.*]] = mul nsw <4 x i32> [[WIDE_LOAD1]], [[WIDE_LOAD]]96; CHECK-NEXT: [[TMP14:%.*]] = mul nsw <4 x i32> [[WIDE_LOAD4]], [[WIDE_LOAD2]]97; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i32> [[TMP2]] to <4 x i64>98; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP3]])99; CHECK-NEXT: [[TMP5]] = add i64 [[VEC_PHI]], [[TMP4]]100; CHECK-NEXT: [[TMP9:%.*]] = sext <4 x i32> [[TMP14]] to <4 x i64>101; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP9]])102; CHECK-NEXT: [[TMP11]] = add i64 [[VEC_PHI1]], [[TMP10]]103; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8104; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]105; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]106; CHECK: middle.block:107; CHECK-NEXT: [[BIN_RDX:%.*]] = add i64 [[TMP11]], [[TMP5]]108; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]109; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]110; CHECK: scalar.ph:111; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER:%.*]] ]112; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[BIN_RDX]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]113; CHECK-NEXT: br label [[FOR_BODY:%.*]]114; CHECK: loop:115; CHECK-NEXT: [[I_010:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]116; CHECK-NEXT: [[R_09:%.*]] = phi i64 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]117; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X]], i32 [[I_010]]118; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4119; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[Y]], i32 [[I_010]]120; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4121; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], [[TMP7]]122; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[MUL]] to i64123; CHECK-NEXT: [[ADD]] = add nsw i64 [[R_09]], [[CONV]]124; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_010]], 1125; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]126; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]127; CHECK: exit:128; CHECK-NEXT: [[R_0_LCSSA:%.*]] = phi i64 [ [[ADD]], [[FOR_BODY]] ], [ [[BIN_RDX]], [[MIDDLE_BLOCK]] ]129; CHECK-NEXT: ret i64 [[R_0_LCSSA]]130;131entry:132 br label %loop133 134loop:135 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]136 %red = phi i64 [ 0, %entry ], [ %red.next, %loop ]137 %gep.x = getelementptr inbounds i32, ptr %x, i32 %iv138 %0 = load i32, ptr %gep.x, align 4139 %gep.y = getelementptr inbounds i32, ptr %y, i32 %iv140 %1 = load i32, ptr %gep.y, align 4141 %mul = mul nsw i32 %1, %0142 %conv = sext i32 %mul to i64143 %red.next = add nsw i64 %red, %conv144 %iv.next = add nuw nsw i32 %iv, 1145 %ec = icmp eq i32 %iv.next, %n146 br i1 %ec, label %exit, label %loop147 148exit:149 %red.lcssa = phi i64 [ %red.next, %loop ]150 ret i64 %red.lcssa151}152 153attributes #0 = { "target-features"="+mve" }154