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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=loop-vectorize,instcombine,simplifycfg < %s -S -o - | FileCheck %s --check-prefix=CHECK3; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -disable-output < %s 2>&1 | FileCheck %s --check-prefix=CHECK-COST4; REQUIRES: asserts5 6target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"7target triple = "thumbv8.1m.main-arm-none-eabi"8 9; CHECK-COST-LABEL: arm_offset_q1510 11define void @arm_offset_q15(ptr nocapture readonly %pSrc, i16 signext %offset, ptr nocapture noalias %pDst, i32 %blockSize) #0 {12; CHECK-LABEL: @arm_offset_q15(13; CHECK-NEXT: entry:14; CHECK-NEXT: [[CMP_NOT6:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 015; CHECK-NEXT: br i1 [[CMP_NOT6]], label [[WHILE_END:%.*]], label [[VECTOR_PH:%.*]]16; CHECK: vector.ph:17; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[BLOCKSIZE]], 718; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -819; CHECK-NEXT: [[BROADCAST_SPLATINSERT7:%.*]] = insertelement <8 x i16> poison, i16 [[OFFSET:%.*]], i64 020; CHECK-NEXT: [[BROADCAST_SPLAT8:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT7]], <8 x i16> poison, <8 x i32> zeroinitializer21; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]22; CHECK: vector.body:23; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]24; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i32 [[INDEX]], 125; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i32 [[OFFSET_IDX]]26; CHECK-NEXT: [[OFFSET_IDX5:%.*]] = shl i32 [[INDEX]], 127; CHECK-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i32 [[OFFSET_IDX5]]28; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 [[INDEX]], i32 [[BLOCKSIZE]])29; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 [[NEXT_GEP]], <8 x i1> [[ACTIVE_LANE_MASK]], <8 x i16> poison)30; CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> [[WIDE_MASKED_LOAD]], <8 x i16> [[BROADCAST_SPLAT8]])31; CHECK-NEXT: call void @llvm.masked.store.v8i16.p0(<8 x i16> [[TMP0]], ptr align 2 [[NEXT_GEP6]], <8 x i1> [[ACTIVE_LANE_MASK]])32; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 833; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]34; CHECK-NEXT: br i1 [[TMP1]], label [[WHILE_END]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]35; CHECK: while.end:36; CHECK-NEXT: ret void37;38entry:39 %cmp.not6 = icmp eq i32 %blockSize, 040 br i1 %cmp.not6, label %while.end, label %while.body41 42while.body: ; preds = %entry, %while.body43 %blkCnt.09 = phi i32 [ %dec, %while.body ], [ %blockSize, %entry ]44 %pSrc.addr.08 = phi ptr [ %incdec.ptr, %while.body ], [ %pSrc, %entry ]45 %pDst.addr.07 = phi ptr [ %incdec.ptr3, %while.body ], [ %pDst, %entry ]46 %incdec.ptr = getelementptr inbounds i16, ptr %pSrc.addr.08, i32 147 %0 = load i16, ptr %pSrc.addr.08, align 248 %1 = tail call i16 @llvm.sadd.sat.i16(i16 %0, i16 %offset)49 %incdec.ptr3 = getelementptr inbounds i16, ptr %pDst.addr.07, i32 150 store i16 %1, ptr %pDst.addr.07, align 251 %dec = add i32 %blkCnt.09, -152 %cmp.not = icmp eq i32 %dec, 053 br i1 %cmp.not, label %while.end, label %while.body54 55while.end: ; preds = %while.body, %entry56 ret void57}58 59declare i16 @llvm.sadd.sat.i16(i16, i16)60 61attributes #0 = { "target-features"="+mve" }62;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:63; CHECK-COST: {{.*}}64