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1; RUN: opt -passes=loop-vectorize < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-2,CHECK-NO42; RUN: opt -passes=loop-vectorize -mve-max-interleave-factor=1 < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO2,CHECK-NO43; RUN: opt -passes=loop-vectorize -mve-max-interleave-factor=2 < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-2,CHECK-NO44; RUN: opt -passes=loop-vectorize -mve-max-interleave-factor=4 < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-2,CHECK-45 6target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"7target triple = "thumbv8.1m.main-none-none-eabi"8 9; CHECK-LABEL: vld210; CHECK-2: vector.body11; CHECK-NO2-NOT: vector.body12define void @vld2(ptr nocapture readonly %pIn, ptr nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 {13entry:14 %tmp.0.extract.trunc = trunc i32 %scale.coerce to i1615 %0 = bitcast i16 %tmp.0.extract.trunc to half16 %mul = mul i32 %numCols, %numRows17 %shr = lshr i32 %mul, 218 %cmp26 = icmp eq i32 %shr, 019 br i1 %cmp26, label %while.end, label %while.body20 21while.body: ; preds = %entry, %while.body22 %pIn.addr.029 = phi ptr [ %add.ptr, %while.body ], [ %pIn, %entry ]23 %pOut.addr.028 = phi ptr [ %add.ptr7, %while.body ], [ %pOut, %entry ]24 %blkCnt.027 = phi i32 [ %dec, %while.body ], [ %shr, %entry ]25 %1 = load half, ptr %pIn.addr.029, align 226 %arrayidx2 = getelementptr inbounds half, ptr %pIn.addr.029, i32 127 %2 = load half, ptr %arrayidx2, align 228 %mul3 = fmul half %1, %029 %mul4 = fmul half %2, %030 store half %mul3, ptr %pOut.addr.028, align 231 %arrayidx6 = getelementptr inbounds half, ptr %pOut.addr.028, i32 132 store half %mul4, ptr %arrayidx6, align 233 %add.ptr = getelementptr inbounds half, ptr %pIn.addr.029, i32 234 %add.ptr7 = getelementptr inbounds half, ptr %pOut.addr.028, i32 235 %dec = add nsw i32 %blkCnt.027, -136 %cmp = icmp eq i32 %dec, 037 br i1 %cmp, label %while.end, label %while.body38 39while.end: ; preds = %while.body, %entry40 ret void41}42 43; CHECK-LABEL: vld444; CHECK-4: vector.body45; CHECK-NO4-NOT: vector.body46define void @vld4(ptr nocapture readonly %pIn, ptr nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 {47entry:48 %tmp.0.extract.trunc = trunc i32 %scale.coerce to i1649 %0 = bitcast i16 %tmp.0.extract.trunc to half50 %mul = mul i32 %numCols, %numRows51 %shr = lshr i32 %mul, 252 %cmp38 = icmp eq i32 %shr, 053 br i1 %cmp38, label %while.end, label %while.body54 55while.body: ; preds = %entry, %while.body56 %pIn.addr.041 = phi ptr [ %add.ptr, %while.body ], [ %pIn, %entry ]57 %pOut.addr.040 = phi ptr [ %add.ptr13, %while.body ], [ %pOut, %entry ]58 %blkCnt.039 = phi i32 [ %dec, %while.body ], [ %shr, %entry ]59 %1 = load half, ptr %pIn.addr.041, align 260 %arrayidx2 = getelementptr inbounds half, ptr %pIn.addr.041, i32 161 %2 = load half, ptr %arrayidx2, align 262 %arrayidx3 = getelementptr inbounds half, ptr %pIn.addr.041, i32 263 %3 = load half, ptr %arrayidx3, align 264 %arrayidx4 = getelementptr inbounds half, ptr %pIn.addr.041, i32 365 %4 = load half, ptr %arrayidx4, align 266 %mul5 = fmul half %1, %067 %mul6 = fmul half %2, %068 %mul7 = fmul half %3, %069 %mul8 = fmul half %4, %070 store half %mul5, ptr %pOut.addr.040, align 271 %arrayidx10 = getelementptr inbounds half, ptr %pOut.addr.040, i32 172 store half %mul6, ptr %arrayidx10, align 273 %arrayidx11 = getelementptr inbounds half, ptr %pOut.addr.040, i32 274 store half %mul7, ptr %arrayidx11, align 275 %arrayidx12 = getelementptr inbounds half, ptr %pOut.addr.040, i32 376 store half %mul8, ptr %arrayidx12, align 277 %add.ptr = getelementptr inbounds half, ptr %pIn.addr.041, i32 478 %add.ptr13 = getelementptr inbounds half, ptr %pOut.addr.040, i32 479 %dec = add nsw i32 %blkCnt.039, -180 %cmp = icmp eq i32 %dec, 081 br i1 %cmp, label %while.end, label %while.body82 83while.end: ; preds = %while.body, %entry84 ret void85}86 87attributes #0 = { "target-features"="+armv8.1-m.main,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-crypto,-d32,-fp-armv8,-fp-armv8sp,-neon,-vfp3,-vfp3sp,-vfp4,-vfp4sp" }88