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1; RUN: opt -mtriple=thumbv8.1m.main-arm-eabihf -mattr=+mve.fp -passes=loop-vectorize -tail-predication=enabled -S < %s | \2; RUN: FileCheck %s3 4target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"5 6; Check that loop hint predicate.enable loop can overrule the TTI hook. For7; this test case, the TTI hook rejects tail-predication:8;9; ARMHWLoops: Trip count does not fit into 32bits10; preferPredicateOverEpilogue: hardware-loop is not profitable.11;12define dso_local void @tail_folding(ptr noalias nocapture %A, ptr noalias nocapture readonly %B, ptr noalias nocapture readonly %C) {13; CHECK-LABEL: tail_folding(14; CHECK: vector.body:15; CHECK-NOT: call <4 x i32> @llvm.masked.load.v4i32.p0(16; CHECK-NOT: call void @llvm.masked.store.v4i32.p0(17; CHECK: br i1 %{{.*}}, label %{{.*}}, label %vector.body, !llvm.loop [[VEC_LOOP1:![0-9]+]]18;19; CHECK: br i1 %{{.*}}, label %{{.*}}, label %for.body, !llvm.loop [[SCALAR_LOOP1:![0-9]+]]20entry:21 br label %for.body22 23for.cond.cleanup:24 ret void25 26for.body:27 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]28 %arrayidx = getelementptr inbounds i32, ptr %B, i64 %indvars.iv29 %0 = load i32, ptr %arrayidx, align 430 %arrayidx2 = getelementptr inbounds i32, ptr %C, i64 %indvars.iv31 %1 = load i32, ptr %arrayidx2, align 432 %add = add nsw i32 %1, %033 %arrayidx4 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv34 store i32 %add, ptr %arrayidx4, align 435 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 136 %exitcond = icmp eq i64 %indvars.iv.next, 43037 br i1 %exitcond, label %for.cond.cleanup, label %for.body38}39 40; The same test case but now with predicate.enable = true should get41; tail-folded.42;43define dso_local void @predicate_loop_hint(ptr noalias nocapture %A, ptr noalias nocapture readonly %B, ptr noalias nocapture readonly %C) {44; CHECK-LABEL: predicate_loop_hint(45; CHECK: vector.body:46; CHECK: %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]47; CHECK: %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 %index, i64 430)48; CHECK: %[[WML1:.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0({{.*}}<4 x i1> %active.lane.mask49; CHECK: %[[WML2:.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0({{.*}}<4 x i1> %active.lane.mask50; CHECK: %[[ADD:.*]] = add nsw <4 x i32> %[[WML2]], %[[WML1]]51; CHECK: call void @llvm.masked.store.v4i32.p0(<4 x i32> %[[ADD]], {{.*}}<4 x i1> %active.lane.mask52; CHECK: %index.next = add nuw i64 %index, 453; CHECK: br i1 %{{.*}}, label %{{.*}}, label %vector.body, !llvm.loop [[VEC_LOOP2:![0-9]+]]54;55; CHECK-NOT: br i1 %{{.*}}, label %{{.*}}, label %for.body, !llvm.loop56entry:57 br label %for.body58 59for.cond.cleanup:60 ret void61 62for.body:63 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]64 %arrayidx = getelementptr inbounds i32, ptr %B, i64 %indvars.iv65 %0 = load i32, ptr %arrayidx, align 466 %arrayidx2 = getelementptr inbounds i32, ptr %C, i64 %indvars.iv67 %1 = load i32, ptr %arrayidx2, align 468 %add = add nsw i32 %1, %069 %arrayidx4 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv70 store i32 %add, ptr %arrayidx4, align 471 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 172 %exitcond = icmp eq i64 %indvars.iv.next, 43073 br i1 %exitcond, label %for.cond.cleanup, label %for.body, !llvm.loop !674}75 76; CHECK: [[VEC_LOOP1]] = distinct !{[[VEC_LOOP1]], [[MD_IS_VEC:![0-9]+]], [[MD_RT_UNROLL_DIS:![0-9]+]]}77; CHECK-NEXT: [[MD_IS_VEC:![0-9]+]] = !{!"llvm.loop.isvectorized", i32 1}78; CHECK-NEXT: [[MD_RT_UNROLL_DIS]] = !{!"llvm.loop.unroll.runtime.disable"}79; CHECK-NEXT: [[SCALAR_LOOP1]] = distinct !{[[SCALAR_LOOP1]], [[MD_RT_UNROLL_DIS]], [[MD_IS_VEC]]}80; CHECK-NEXT: [[VEC_LOOP2]] = distinct !{[[VEC_LOOP2]], [[MD_IS_VEC]], [[MD_RT_UNROLL_DIS]]}81 82!6 = distinct !{!6, !7, !8}83!7 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}84!8 = !{!"llvm.loop.vectorize.enable", i1 true}85