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1; RUN: opt -passes=loop-vectorize -hexagon-autohvx=1 -force-vector-width=64 -prefer-predicate-over-epilogue=predicate-dont-vectorize -S %s | FileCheck %s2 3target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"4target triple = "hexagon"5 6; Test for PR45572.7 8; Check that interleave groups and decisions based on them are correctly9; invalidated with tail-folding on platforms where masked interleaved accesses10; are disabled.11 12; Make sure a vector body has been created, 64 element vectors are used and a block predicate has been computed.13; Also make sure the loads are not widened.14 15; CHECK-LABEL: @test116; CHECK: vector.body:17; CHECK: icmp ule <64 x i32> %vec.ind18; CHECK-NOT: load <{{.*}} x i32>19 20 21define void @test1(ptr %arg, i32 %N) #0 {22entry:23 %tmp = alloca i3224 br label %loop25 26loop: ; preds = %bb2, %bb27 %iv = phi i32 [ %iv.next, %loop], [ 0, %entry ]28 %idx.mul = mul nuw nsw i32 %iv, 729 %idx.start = add nuw nsw i32 %idx.mul, 130 %tmp6 = getelementptr inbounds i32, ptr %arg, i32 %idx.start31 %tmp7 = load i32, ptr %tmp6, align 432 %tmp8 = add nuw nsw i32 %idx.start, 133 %tmp9 = getelementptr inbounds i32, ptr %arg, i32 %tmp834 %tmp10 = load i32, ptr %tmp9, align 435 %tmp11 = add nuw nsw i32 %idx.start, 236 %tmp12 = getelementptr inbounds i32, ptr %arg, i32 %tmp1137 %tmp13 = load i32, ptr %tmp12, align 438 %tmp14 = add nuw nsw i32 %idx.start, 339 %tmp15 = getelementptr inbounds i32, ptr %arg, i32 %tmp1440 %tmp16 = load i32, ptr %tmp15, align 441 %tmp18 = add nuw nsw i32 %idx.start, 442 %tmp19 = getelementptr inbounds i32, ptr %arg, i32 %tmp1843 %tmp20 = load i32, ptr %tmp19, align 444 %tmp21 = add nuw nsw i32 %idx.start, 545 %tmp22 = getelementptr inbounds i32, ptr %arg, i32 %tmp2146 %tmp23 = load i32, ptr %tmp22, align 447 %tmp25 = add nuw nsw i32 %idx.start, 648 %tmp26 = getelementptr inbounds i32, ptr %arg, i32 %tmp2549 %tmp27 = load i32, ptr %tmp26, align 450 %add = add i32 %tmp7, %tmp2751 store i32 %add, ptr %tmp, align 152 %iv.next= add nuw nsw i32 %iv, 153 %exit.cond = icmp eq i32 %iv.next, %N54 br i1 %exit.cond, label %exit, label %loop55 56exit: ; preds = %loop57 ret void58}59 60; The loop below only requires tail folding due to interleave groups with gaps.61; Make sure the loads are not widened.62 63; CHECK-LABEL: @test264; CHECK: vector.body:65; CHECK-NOT: load <{{.*}} x i32>66define void @test2(ptr %arg) #1 {67entry:68 %tmp = alloca i3269 br label %loop70 71loop: ; preds = %bb2, %bb72 %iv = phi i32 [ %iv.next, %loop], [ 0, %entry ]73 %idx.start = mul nuw nsw i32 %iv, 574 %tmp6 = getelementptr inbounds i32, ptr %arg, i32 %idx.start75 %tmp7 = load i32, ptr %tmp6, align 476 %tmp8 = add nuw nsw i32 %idx.start, 177 %tmp9 = getelementptr inbounds i32, ptr %arg, i32 %tmp878 %tmp10 = load i32, ptr %tmp9, align 479 %tmp11 = add nuw nsw i32 %idx.start, 280 %tmp12 = getelementptr inbounds i32, ptr %arg, i32 %tmp1181 %tmp13 = load i32, ptr %tmp12, align 482 %tmp14 = add nuw nsw i32 %idx.start, 383 %tmp15 = getelementptr inbounds i32, ptr %arg, i32 %tmp1484 %tmp16 = load i32, ptr %tmp15, align 485 %add = add i32 %tmp7, %tmp1686 store i32 %add, ptr %tmp, align 187 %iv.next= add nuw nsw i32 %iv, 188 %exit.cond = icmp eq i32 %iv.next, 12889 br i1 %exit.cond, label %exit, label %loop90 91exit: ; preds = %loop92 ret void93}94 95 96attributes #0 = { "target-features"="+hvx,+hvx-length128b" }97attributes #1 = { optsize "target-features"="+hvx,+hvx-length128b" }98