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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -S %s | FileCheck %s3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"5target triple = "riscv64-unknown-linux-gnu"6 7; Test case for https://github.com/llvm/llvm-project/issues/111874.8define i32 @any_of_reduction_used_in_blend(ptr %src, i64 %N, i1 %c.0, i1 %c.1) #0 {9; CHECK-LABEL: define i32 @any_of_reduction_used_in_blend(10; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]], i1 [[C_0:%.*]], i1 [[C_1:%.*]]) #[[ATTR0:[0-9]+]] {11; CHECK-NEXT: [[ENTRY:.*]]:12; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]13; CHECK: [[LOOP_HEADER]]:14; CHECK-NEXT: [[ANY_OF_RED:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[ANY_OF_RED_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]15; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH]] ]16; CHECK-NEXT: br i1 [[C_0]], label %[[LOOP_LATCH]], label %[[ELSE_1:.*]]17; CHECK: [[ELSE_1]]:18; CHECK-NEXT: br i1 [[C_1]], label %[[LOOP_LATCH]], label %[[ELSE_2:.*]]19; CHECK: [[ELSE_2]]:20; CHECK-NEXT: [[L:%.*]] = load ptr, ptr [[SRC]], align 821; CHECK-NEXT: [[C_2:%.*]] = icmp eq ptr [[L]], null22; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C_2]], i32 0, i32 [[ANY_OF_RED]]23; CHECK-NEXT: br label %[[LOOP_LATCH]]24; CHECK: [[LOOP_LATCH]]:25; CHECK-NEXT: [[ANY_OF_RED_NEXT]] = phi i32 [ [[ANY_OF_RED]], %[[LOOP_HEADER]] ], [ [[ANY_OF_RED]], %[[ELSE_1]] ], [ [[SEL]], %[[ELSE_2]] ]26; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 127; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]28; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]29; CHECK: [[EXIT]]:30; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[ANY_OF_RED_NEXT]], %[[LOOP_LATCH]] ]31; CHECK-NEXT: ret i32 [[RES]]32;33entry:34 br label %loop.header35 36loop.header:37 %any.of.red = phi i32 [ 0, %entry ], [ %any.of.red.next, %loop.latch ]38 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]39 br i1 %c.0, label %loop.latch, label %else.140 41else.1:42 br i1 %c.1, label %loop.latch, label %else.243 44else.2:45 %l = load ptr, ptr %src, align 846 %c.2 = icmp eq ptr %l, null47 %sel = select i1 %c.2, i32 0, i32 %any.of.red48 br label %loop.latch49 50loop.latch:51 %any.of.red.next = phi i32 [ %any.of.red, %loop.header ], [ %any.of.red, %else.1 ], [ %sel, %else.2 ]52 %iv.next = add i64 %iv, 153 %ec = icmp eq i64 %iv.next, %N54 br i1 %ec, label %exit, label %loop.header55 56exit:57 %res = phi i32 [ %any.of.red.next, %loop.latch ]58 ret i32 %res59}60 61define i32 @any_of_reduction_used_in_blend_with_multiple_phis(ptr %src, i64 %N, i1 %c.0, i1 %c.1) #0 {62; CHECK-LABEL: define i32 @any_of_reduction_used_in_blend_with_multiple_phis(63; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]], i1 [[C_0:%.*]], i1 [[C_1:%.*]]) #[[ATTR0]] {64; CHECK-NEXT: [[ENTRY:.*]]:65; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]66; CHECK: [[LOOP_HEADER]]:67; CHECK-NEXT: [[ANY_OF_RED:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[ANY_OF_RED_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]68; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH]] ]69; CHECK-NEXT: br i1 [[C_0]], label %[[X_1:.*]], label %[[ELSE_1:.*]]70; CHECK: [[ELSE_1]]:71; CHECK-NEXT: br i1 [[C_1]], label %[[X_1]], label %[[ELSE_2:.*]]72; CHECK: [[ELSE_2]]:73; CHECK-NEXT: [[L:%.*]] = load ptr, ptr [[SRC]], align 874; CHECK-NEXT: [[C_2:%.*]] = icmp eq ptr [[L]], null75; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C_2]], i32 0, i32 [[ANY_OF_RED]]76; CHECK-NEXT: br label %[[LOOP_LATCH]]77; CHECK: [[X_1]]:78; CHECK-NEXT: [[P:%.*]] = phi i32 [ [[ANY_OF_RED]], %[[LOOP_HEADER]] ], [ [[ANY_OF_RED]], %[[ELSE_1]] ]79; CHECK-NEXT: br label %[[LOOP_LATCH]]80; CHECK: [[LOOP_LATCH]]:81; CHECK-NEXT: [[ANY_OF_RED_NEXT]] = phi i32 [ [[P]], %[[X_1]] ], [ [[SEL]], %[[ELSE_2]] ]82; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 183; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]84; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]85; CHECK: [[EXIT]]:86; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[ANY_OF_RED_NEXT]], %[[LOOP_LATCH]] ]87; CHECK-NEXT: ret i32 [[RES]]88;89entry:90 br label %loop.header91 92loop.header:93 %any.of.red = phi i32 [ 0, %entry ], [ %any.of.red.next, %loop.latch ]94 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]95 br i1 %c.0, label %x.1, label %else.196 97else.1:98 br i1 %c.1, label %x.1, label %else.299 100else.2:101 %l = load ptr, ptr %src, align 8102 %c.2 = icmp eq ptr %l, null103 %sel = select i1 %c.2, i32 0, i32 %any.of.red104 br label %loop.latch105 106x.1:107 %p = phi i32 [ %any.of.red, %loop.header ], [ %any.of.red, %else.1 ]108 br label %loop.latch109 110loop.latch:111 %any.of.red.next = phi i32 [ %p, %x.1 ], [ %sel, %else.2 ]112 %iv.next = add i64 %iv, 1113 %ec = icmp eq i64 %iv.next, %N114 br i1 %ec, label %exit, label %loop.header115 116exit:117 %res = phi i32 [ %any.of.red.next, %loop.latch ]118 ret i32 %res119}120 121attributes #0 = { "target-cpu"="sifive-p670" }122