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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -S %s | FileCheck %s3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"5target triple = "riscv64-unknown-linux-gnu"6 7define void @block_with_dead_inst_1(ptr %src, i64 %N) #0 {8; CHECK-LABEL: define void @block_with_dead_inst_1(9; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {10; CHECK-NEXT: [[ENTRY:.*:]]11; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -312; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[TMP0]], 313; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 114; CHECK-NEXT: br label %[[VECTOR_PH:.*]]15; CHECK: [[VECTOR_PH]]:16; CHECK-NEXT: [[TMP11:%.*]] = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()17; CHECK-NEXT: [[TMP4:%.*]] = mul nsw <vscale x 8 x i64> [[TMP11]], splat (i64 3)18; CHECK-NEXT: [[INDUCTION:%.*]] = add nsw <vscale x 8 x i64> zeroinitializer, [[TMP4]]19; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]20; CHECK: [[VECTOR_BODY]]:21; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 8 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]22; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP2]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]23; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)24; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP12]] to i6425; CHECK-NEXT: [[TMP16:%.*]] = mul nsw i64 3, [[TMP17]]26; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[TMP16]], i64 027; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i64> [[DOTSPLATINSERT]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer28; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i16, ptr [[SRC]], <vscale x 8 x i64> [[VEC_IND]]29; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x ptr> align 2 [[TMP20]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP12]])30; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP17]]31; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <vscale x 8 x i64> [[VEC_IND]], [[DOTSPLAT]]32; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[AVL_NEXT]], 033; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]34; CHECK: [[MIDDLE_BLOCK]]:35; CHECK-NEXT: br label %[[EXIT:.*]]36; CHECK: [[EXIT]]:37; CHECK-NEXT: ret void38;39entry:40 br label %loop.header41 42loop.header: ; preds = %cond.end7, %entry43 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]44 %xor1315 = phi i16 [ 1, %entry ], [ %xor, %loop.latch ]45 %xor = xor i16 0, 046 %gep = getelementptr i16, ptr %src, i64 %iv47 %l = load i16, ptr %gep, align 248 %c = icmp eq i16 %l, 049 br i1 %c, label %then, label %loop.latch50 51then:52 %dead.gep = getelementptr i64, ptr %src, i64 %iv53 br label %loop.latch54 55loop.latch:56 store i16 %xor, ptr %gep57 %iv.next = add nsw i64 %iv, 358 %1 = icmp eq i64 %iv.next, %N59 br i1 %1, label %exit, label %loop.header60 61exit:62 ret void63}64 65define void @block_with_dead_inst_2(ptr %src) #0 {66; CHECK-LABEL: define void @block_with_dead_inst_2(67; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {68; CHECK-NEXT: [[ENTRY:.*:]]69; CHECK-NEXT: br label %[[VECTOR_PH:.*]]70; CHECK: [[VECTOR_PH]]:71; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()72; CHECK-NEXT: [[TMP1:%.*]] = mul nsw <vscale x 8 x i64> [[TMP5]], splat (i64 3)73; CHECK-NEXT: [[INDUCTION:%.*]] = add nsw <vscale x 8 x i64> zeroinitializer, [[TMP1]]74; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]75; CHECK: [[VECTOR_BODY]]:76; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 8 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]77; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 333, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]78; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)79; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP9]] to i6480; CHECK-NEXT: [[TMP13:%.*]] = mul nsw i64 3, [[TMP7]]81; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[TMP13]], i64 082; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer83; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i16, ptr [[SRC]], <vscale x 8 x i64> [[VEC_IND]]84; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x ptr> align 2 [[TMP10]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP9]])85; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP7]]86; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <vscale x 8 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]87; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[AVL_NEXT]], 088; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]89; CHECK: [[MIDDLE_BLOCK]]:90; CHECK-NEXT: br label %[[EXIT:.*]]91; CHECK: [[EXIT]]:92; CHECK-NEXT: ret void93;94entry:95 br label %loop.header96 97loop.header: ; preds = %cond.end7, %entry98 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]99 %xor1315 = phi i16 [ 0, %entry ], [ %xor, %loop.latch ]100 %xor = xor i16 0, 0101 %gep = getelementptr i16, ptr %src, i64 %iv102 %l = load i16, ptr %gep, align 2103 %c = icmp eq i16 %l, 0104 br i1 %c, label %loop.latch, label %else105 106else:107 %dead.gep = getelementptr i64, ptr %src, i64 %iv108 br label %loop.latch109 110loop.latch:111 store i16 %xor, ptr %gep112 %iv.next = add nsw i64 %iv, 3113 %ec = icmp eq i64 %iv.next, 1000114 br i1 %ec, label %exit, label %loop.header115 116exit:117 ret void118}119 120define void @multiple_blocks_with_dead_insts_3(ptr %src) #0 {121; CHECK-LABEL: define void @multiple_blocks_with_dead_insts_3(122; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {123; CHECK-NEXT: [[ENTRY:.*:]]124; CHECK-NEXT: br label %[[VECTOR_PH:.*]]125; CHECK: [[VECTOR_PH]]:126; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()127; CHECK-NEXT: [[TMP1:%.*]] = mul nsw <vscale x 8 x i64> [[TMP5]], splat (i64 3)128; CHECK-NEXT: [[INDUCTION:%.*]] = add nsw <vscale x 8 x i64> zeroinitializer, [[TMP1]]129; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]130; CHECK: [[VECTOR_BODY]]:131; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 8 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]132; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 333, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]133; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)134; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP9]] to i64135; CHECK-NEXT: [[TMP13:%.*]] = mul nsw i64 3, [[TMP7]]136; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[TMP13]], i64 0137; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer138; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i16, ptr [[SRC]], <vscale x 8 x i64> [[VEC_IND]]139; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x ptr> align 2 [[TMP10]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP9]])140; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP7]]141; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <vscale x 8 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]142; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[AVL_NEXT]], 0143; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]144; CHECK: [[MIDDLE_BLOCK]]:145; CHECK-NEXT: br label %[[EXIT:.*]]146; CHECK: [[EXIT]]:147; CHECK-NEXT: ret void148;149entry:150 br label %loop.header151 152loop.header: ; preds = %cond.end7, %entry153 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]154 %xor1315 = phi i16 [ 0, %entry ], [ %xor, %loop.latch ]155 %xor = xor i16 0, 0156 %gep = getelementptr i16, ptr %src, i64 %iv157 %l = load i16, ptr %gep, align 2158 %c = icmp eq i16 %l, 0159 br i1 %c, label %then, label %else160 161then:162 %dead.gep.1 = getelementptr i64, ptr %src, i64 %iv163 br label %loop.latch164 165else:166 %dead.gep.2 = getelementptr i64, ptr %src, i64 %iv167 br label %loop.latch168 169loop.latch:170 store i16 %xor, ptr %gep171 %iv.next = add nsw i64 %iv, 3172 %ec = icmp eq i64 %iv.next, 1000173 br i1 %ec, label %exit, label %loop.header174 175exit:176 ret void177}178 179define void @multiple_blocks_with_dead_insts_4(ptr %src, i64 %N) #0 {180; CHECK-LABEL: define void @multiple_blocks_with_dead_insts_4(181; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {182; CHECK-NEXT: [[ENTRY:.*:]]183; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -3184; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[TMP0]], 3185; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1186; CHECK-NEXT: br label %[[VECTOR_PH:.*]]187; CHECK: [[VECTOR_PH]]:188; CHECK-NEXT: [[TMP11:%.*]] = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()189; CHECK-NEXT: [[TMP4:%.*]] = mul nsw <vscale x 8 x i64> [[TMP11]], splat (i64 3)190; CHECK-NEXT: [[INDUCTION:%.*]] = add nsw <vscale x 8 x i64> zeroinitializer, [[TMP4]]191; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]192; CHECK: [[VECTOR_BODY]]:193; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 8 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]194; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP2]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]195; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)196; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP12]] to i64197; CHECK-NEXT: [[TMP16:%.*]] = mul nsw i64 3, [[TMP17]]198; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[TMP16]], i64 0199; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i64> [[DOTSPLATINSERT]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer200; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i16, ptr [[SRC]], <vscale x 8 x i64> [[VEC_IND]]201; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x ptr> align 2 [[TMP20]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP12]])202; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP17]]203; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <vscale x 8 x i64> [[VEC_IND]], [[DOTSPLAT]]204; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[AVL_NEXT]], 0205; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]206; CHECK: [[MIDDLE_BLOCK]]:207; CHECK-NEXT: br label %[[EXIT:.*]]208; CHECK: [[EXIT]]:209; CHECK-NEXT: ret void210;211entry:212 br label %loop.header213 214loop.header: ; preds = %cond.end7, %entry215 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]216 %xor1315 = phi i16 [ 1, %entry ], [ %xor, %loop.latch ]217 %xor = xor i16 0, 0218 %gep = getelementptr i16, ptr %src, i64 %iv219 %l = load i16, ptr %gep, align 2220 %c = icmp eq i16 %l, 0221 br i1 %c, label %then, label %else222 223then:224 br label %then.1225 226then.1:227 %dead.gep.1 = getelementptr i64, ptr %src, i64 %iv228 br label %loop.latch229 230else:231 %dead.gep.2 = getelementptr i64, ptr %src, i64 %iv232 br label %loop.latch233 234loop.latch:235 store i16 %xor, ptr %gep236 %iv.next = add nsw i64 %iv, 3237 %ec = icmp eq i64 %iv.next, %N238 br i1 %ec, label %exit, label %loop.header239 240exit:241 ret void242}243 244define void @multiple_blocks_with_dead_inst_multiple_successors_5(ptr %src) #0 {245; CHECK-LABEL: define void @multiple_blocks_with_dead_inst_multiple_successors_5(246; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {247; CHECK-NEXT: [[ENTRY:.*:]]248; CHECK-NEXT: br label %[[VECTOR_PH:.*]]249; CHECK: [[VECTOR_PH]]:250; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()251; CHECK-NEXT: [[TMP1:%.*]] = mul nsw <vscale x 8 x i64> [[TMP5]], splat (i64 3)252; CHECK-NEXT: [[INDUCTION:%.*]] = add nsw <vscale x 8 x i64> zeroinitializer, [[TMP1]]253; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]254; CHECK: [[VECTOR_BODY]]:255; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 8 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]256; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 333, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]257; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)258; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP9]] to i64259; CHECK-NEXT: [[TMP13:%.*]] = mul nsw i64 3, [[TMP7]]260; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[TMP13]], i64 0261; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer262; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i16, ptr [[SRC]], <vscale x 8 x i64> [[VEC_IND]]263; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x ptr> align 2 [[TMP10]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP9]])264; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP7]]265; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <vscale x 8 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]266; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[AVL_NEXT]], 0267; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]268; CHECK: [[MIDDLE_BLOCK]]:269; CHECK-NEXT: br label %[[EXIT:.*]]270; CHECK: [[EXIT]]:271; CHECK-NEXT: ret void272;273entry:274 br label %loop.header275 276loop.header: ; preds = %cond.end7, %entry277 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]278 %xor1315 = phi i16 [ 1, %entry ], [ %xor, %loop.latch ]279 %xor = xor i16 0, 0280 %gep = getelementptr i16, ptr %src, i64 %iv281 %l = load i16, ptr %gep, align 2282 %c = icmp eq i16 %l, 0283 br i1 %c, label %then, label %else284 285then:286 br label %then.1287 288then.1:289 %dead.gep.1 = getelementptr i64, ptr %src, i64 %iv290 br label %loop.latch291 292else:293 br label %else.2294 295else.2:296 %dead.gep.2 = getelementptr i64, ptr %src, i64 %iv297 br label %loop.latch298 299loop.latch:300 store i16 %xor, ptr %gep301 %iv.next = add nsw i64 %iv, 3302 %ec = icmp eq i64 %iv.next, 1000303 br i1 %ec, label %exit, label %loop.header304 305exit:306 ret void307}308 309define void @multiple_blocks_with_dead_inst_multiple_successors_6(ptr %src, i1 %ic, i64 %N) #0 {310; CHECK-LABEL: define void @multiple_blocks_with_dead_inst_multiple_successors_6(311; CHECK-SAME: ptr [[SRC:%.*]], i1 [[IC:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {312; CHECK-NEXT: [[ENTRY:.*:]]313; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -3314; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[TMP0]], 3315; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1316; CHECK-NEXT: br label %[[VECTOR_PH:.*]]317; CHECK: [[VECTOR_PH]]:318; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x i1> poison, i1 [[IC]], i64 0319; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x i1> [[BROADCAST_SPLATINSERT]], <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer320; CHECK-NEXT: [[TMP8:%.*]] = xor <vscale x 8 x i1> [[BROADCAST_SPLAT]], splat (i1 true)321; CHECK-NEXT: [[TMP11:%.*]] = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()322; CHECK-NEXT: [[TMP5:%.*]] = mul nsw <vscale x 8 x i64> [[TMP11]], splat (i64 3)323; CHECK-NEXT: [[INDUCTION:%.*]] = add nsw <vscale x 8 x i64> zeroinitializer, [[TMP5]]324; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]325; CHECK: [[VECTOR_BODY]]:326; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 8 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]327; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP2]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]328; CHECK-NEXT: [[TMP27:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)329; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP27]] to i64330; CHECK-NEXT: [[TMP16:%.*]] = mul nsw i64 3, [[TMP12]]331; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[TMP16]], i64 0332; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i64> [[DOTSPLATINSERT]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer333; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i16, ptr [[SRC]], <vscale x 8 x i64> [[VEC_IND]]334; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 8 x i16> @llvm.vp.gather.nxv8i16.nxv8p0(<vscale x 8 x ptr> align 2 [[TMP20]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP27]])335; CHECK-NEXT: [[TMP17:%.*]] = icmp eq <vscale x 8 x i16> [[WIDE_MASKED_GATHER]], zeroinitializer336; CHECK-NEXT: [[TMP14:%.*]] = select <vscale x 8 x i1> [[TMP17]], <vscale x 8 x i1> [[TMP8]], <vscale x 8 x i1> zeroinitializer337; CHECK-NEXT: [[TMP28:%.*]] = xor <vscale x 8 x i1> [[TMP17]], splat (i1 true)338; CHECK-NEXT: [[TMP22:%.*]] = or <vscale x 8 x i1> [[TMP14]], [[TMP28]]339; CHECK-NEXT: [[TMP23:%.*]] = select <vscale x 8 x i1> [[TMP17]], <vscale x 8 x i1> [[BROADCAST_SPLAT]], <vscale x 8 x i1> zeroinitializer340; CHECK-NEXT: [[TMP24:%.*]] = or <vscale x 8 x i1> [[TMP22]], [[TMP23]]341; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x ptr> align 2 [[TMP20]], <vscale x 8 x i1> [[TMP24]], i32 [[TMP27]])342; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP12]]343; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <vscale x 8 x i64> [[VEC_IND]], [[DOTSPLAT]]344; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[AVL_NEXT]], 0345; CHECK-NEXT: br i1 [[TMP26]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]346; CHECK: [[MIDDLE_BLOCK]]:347; CHECK-NEXT: br label %[[EXIT:.*]]348; CHECK: [[EXIT]]:349; CHECK-NEXT: ret void350;351entry:352 br label %loop.header353 354loop.header: ; preds = %cond.end7, %entry355 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]356 %xor1315 = phi i16 [ 1, %entry ], [ %xor, %loop.latch ]357 %xor = xor i16 0, 0358 %gep = getelementptr i16, ptr %src, i64 %iv359 %l = load i16, ptr %gep, align 2360 %c = icmp eq i16 %l, 0361 br i1 %c, label %then, label %else362 363then:364 br i1 %ic, label %then.1, label %else365 366then.1:367 %dead.gep.1 = getelementptr i64, ptr %src, i64 %iv368 br label %loop.latch369 370else:371 br label %else.2372 373else.2:374 %dead.gep.2 = getelementptr i64, ptr %src, i64 %iv375 br label %loop.latch376 377loop.latch:378 store i16 %xor, ptr %gep379 %iv.next = add nsw i64 %iv, 3380 %ec = icmp eq i64 %iv.next, %N381 br i1 %ec, label %exit, label %loop.header382 383exit:384 ret void385}386 387define void @empty_block_with_phi_1(ptr %src, i64 %N) #0 {388; CHECK-LABEL: define void @empty_block_with_phi_1(389; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {390; CHECK-NEXT: [[ENTRY:.*:]]391; CHECK-NEXT: br label %[[VECTOR_PH:.*]]392; CHECK: [[VECTOR_PH]]:393; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]394; CHECK: [[VECTOR_BODY]]:395; CHECK-NEXT: [[TMP9:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]396; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]397; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)398; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i16, ptr [[SRC]], i64 [[TMP9]]399; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 8 x i16> @llvm.vp.load.nxv8i16.p0(ptr align 2 [[TMP10]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP13]])400; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <vscale x 8 x i16> [[VP_OP_LOAD]], zeroinitializer401; CHECK-NEXT: [[PREDPHI:%.*]] = select <vscale x 8 x i1> [[TMP2]], <vscale x 8 x i16> splat (i16 99), <vscale x 8 x i16> [[VP_OP_LOAD]]402; CHECK-NEXT: call void @llvm.vp.store.nxv8i16.p0(<vscale x 8 x i16> [[PREDPHI]], ptr align 2 [[TMP10]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP13]])403; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP13]] to i64404; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP11]], [[TMP9]]405; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP11]]406; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[AVL_NEXT]], 0407; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]408; CHECK: [[MIDDLE_BLOCK]]:409; CHECK-NEXT: br label %[[EXIT:.*]]410; CHECK: [[EXIT]]:411; CHECK-NEXT: ret void412;413entry:414 br label %loop.header415 416loop.header: ; preds = %cond.end7, %entry417 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]418 %xor1315 = phi i32 [ 1, %entry ], [ %xor, %loop.latch ]419 %xor = xor i32 0, 0420 %gep = getelementptr i16, ptr %src, i64 %iv421 %l = load i16, ptr %gep, align 2422 %c = icmp eq i16 %l, 0423 br i1 %c, label %then, label %loop.latch424 425then:426 br label %loop.latch427 428loop.latch:429 %p = phi i16 [ %l, %loop.header ], [ 99, %then ]430 store i16 %p, ptr %gep431 %iv.next = add nsw i64 %iv, 1432 %1 = icmp eq i64 %iv.next, %N433 br i1 %1, label %exit, label %loop.header434 435exit:436 ret void437}438 439define void @empty_block_with_phi_2(ptr %src, i64 %N) #0 {440; CHECK-LABEL: define void @empty_block_with_phi_2(441; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {442; CHECK-NEXT: [[ENTRY:.*:]]443; CHECK-NEXT: br label %[[VECTOR_PH:.*]]444; CHECK: [[VECTOR_PH]]:445; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]446; CHECK: [[VECTOR_BODY]]:447; CHECK-NEXT: [[TMP9:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]448; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]449; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)450; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i16, ptr [[SRC]], i64 [[TMP9]]451; CHECK-NEXT: [[WIDE_LOAD:%.*]] = call <vscale x 8 x i16> @llvm.vp.load.nxv8i16.p0(ptr align 2 [[TMP10]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP13]])452; CHECK-NEXT: [[TMP12:%.*]] = icmp eq <vscale x 8 x i16> [[WIDE_LOAD]], zeroinitializer453; CHECK-NEXT: [[PREDPHI:%.*]] = select <vscale x 8 x i1> [[TMP12]], <vscale x 8 x i16> [[WIDE_LOAD]], <vscale x 8 x i16> splat (i16 99)454; CHECK-NEXT: call void @llvm.vp.store.nxv8i16.p0(<vscale x 8 x i16> [[PREDPHI]], ptr align 2 [[TMP10]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP13]])455; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP13]] to i64456; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP11]], [[TMP9]]457; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP11]]458; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[AVL_NEXT]], 0459; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]460; CHECK: [[MIDDLE_BLOCK]]:461; CHECK-NEXT: br label %[[EXIT:.*]]462; CHECK: [[EXIT]]:463; CHECK-NEXT: ret void464;465entry:466 br label %loop.header467 468loop.header: ; preds = %cond.end7, %entry469 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]470 %xor1315 = phi i32 [ 1, %entry ], [ %xor, %loop.latch ]471 %xor = xor i32 0, 0472 %gep = getelementptr i16, ptr %src, i64 %iv473 %l = load i16, ptr %gep, align 2474 %c = icmp eq i16 %l, 0475 br i1 %c, label %loop.latch, label %else476 477else:478 br label %loop.latch479 480loop.latch:481 %p = phi i16 [ %l, %loop.header ], [ 99, %else ]482 store i16 %p, ptr %gep483 %iv.next = add nsw i64 %iv, 1484 %1 = icmp eq i64 %iv.next, %N485 br i1 %1, label %exit, label %loop.header486 487exit:488 ret void489}490 491; Test case for https://github.com/llvm/llvm-project/issues/100591.492define void @dead_load_in_block(ptr %dst, ptr %src, i8 %N, i64 %x) #0 {493; CHECK-LABEL: define void @dead_load_in_block(494; CHECK-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]], i8 [[N:%.*]], i64 [[X:%.*]]) #[[ATTR0]] {495; CHECK-NEXT: [[ENTRY:.*:]]496; CHECK-NEXT: [[N_EXT:%.*]] = zext i8 [[N]] to i64497; CHECK-NEXT: [[UMIN7:%.*]] = call i64 @llvm.umin.i64(i64 [[N_EXT]], i64 1)498; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[N_EXT]], [[UMIN7]]499; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[TMP0]], 3500; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[UMIN7]], [[TMP1]]501; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 1502; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]503; CHECK: [[VECTOR_MEMCHECK]]:504; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[N_EXT]], i64 1)505; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[N_EXT]], [[UMIN]]506; CHECK-NEXT: [[TMP8:%.*]] = udiv i64 [[TMP7]], 3507; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[UMIN]], [[TMP8]]508; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 12509; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[TMP10]], 4510; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP11]]511; CHECK-NEXT: [[TMP12:%.*]] = shl i64 [[X]], 2512; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP12]]513; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 4514; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP13]]515; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[SRC]], i64 4516; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP2]]517; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SCEVGEP1]], [[SCEVGEP]]518; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]519; CHECK-NEXT: [[BOUND04:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP3]]520; CHECK-NEXT: [[BOUND15:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP]]521; CHECK-NEXT: [[FOUND_CONFLICT6:%.*]] = and i1 [[BOUND04]], [[BOUND15]]522; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT6]]523; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]524; CHECK: [[VECTOR_PH]]:525; CHECK-NEXT: [[TMP24:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64()526; CHECK-NEXT: [[TMP25:%.*]] = mul <vscale x 4 x i64> [[TMP24]], splat (i64 3)527; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 4 x i64> zeroinitializer, [[TMP25]]528; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]529; CHECK: [[VECTOR_BODY]]:530; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]531; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP3]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]532; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)533; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP18]] to i64534; CHECK-NEXT: [[TMP23:%.*]] = mul i64 3, [[TMP17]]535; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP23]], i64 0536; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer537; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[DST]], <vscale x 4 x i64> [[VEC_IND]]538; CHECK-NEXT: call void @llvm.vp.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x ptr> align 4 [[TMP21]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP18]]), !alias.scope [[META10:![0-9]+]], !noalias [[META13:![0-9]+]]539; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP17]]540; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]541; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[AVL_NEXT]], 0542; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]543; CHECK: [[MIDDLE_BLOCK]]:544; CHECK-NEXT: br label %[[EXIT:.*]]545; CHECK: [[SCALAR_PH]]:546; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]547; CHECK: [[LOOP_HEADER]]:548; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]549; CHECK-NEXT: [[L_0:%.*]] = load i32, ptr [[SRC]], align 4550; CHECK-NEXT: [[C_0:%.*]] = icmp eq i32 [[L_0]], 0551; CHECK-NEXT: br i1 [[C_0]], label %[[LOOP_LATCH]], label %[[THEN:.*]]552; CHECK: [[THEN]]:553; CHECK-NEXT: [[GEP_SRC_X:%.*]] = getelementptr i32, ptr [[SRC]], i64 [[X]]554; CHECK-NEXT: [[L_DEAD:%.*]] = load i32, ptr [[GEP_SRC_X]], align 4555; CHECK-NEXT: br label %[[LOOP_LATCH]]556; CHECK: [[LOOP_LATCH]]:557; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV]]558; CHECK-NEXT: store i32 0, ptr [[GEP_DST]], align 4559; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 3560; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[IV]], [[N_EXT]]561; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP_HEADER]], label %[[EXIT]], !llvm.loop [[LOOP17:![0-9]+]]562; CHECK: [[EXIT]]:563; CHECK-NEXT: ret void564;565entry:566 %N.ext = zext i8 %N to i64567 br label %loop.header568 569loop.header:570 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]571 %l.0 = load i32, ptr %src, align 4572 %c.0 = icmp eq i32 %l.0, 0573 br i1 %c.0, label %loop.latch , label %then574 575then:576 %gep.src.x = getelementptr i32, ptr %src, i64 %x577 %l.dead = load i32, ptr %gep.src.x, align 4578 br label %loop.latch579 580loop.latch:581 %gep.dst = getelementptr i32, ptr %dst, i64 %iv582 store i32 0, ptr %gep.dst, align 4583 %iv.next = add i64 %iv, 3584 %cmp = icmp ult i64 %iv, %N.ext585 br i1 %cmp, label %loop.header, label %exit586 587exit:588 ret void589}590 591attributes #0 = { "target-features"="+64bit,+v" }592;.593; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}594; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}595; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}596; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}597; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}598; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]}599; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}600; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]]}601; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}602; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]], [[META2]]}603; CHECK: [[META10]] = !{[[META11:![0-9]+]]}604; CHECK: [[META11]] = distinct !{[[META11]], [[META12:![0-9]+]]}605; CHECK: [[META12]] = distinct !{[[META12]], !"LVerDomain"}606; CHECK: [[META13]] = !{[[META14:![0-9]+]], [[META15:![0-9]+]]}607; CHECK: [[META14]] = distinct !{[[META14]], [[META12]]}608; CHECK: [[META15]] = distinct !{[[META15]], [[META12]]}609; CHECK: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]], [[META2]]}610; CHECK: [[LOOP17]] = distinct !{[[LOOP17]], [[META1]]}611;.612