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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -mtriple riscv64-linux-gnu -mattr=+v,+f -S %s | FileCheck %s3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"5 6; Test with a dead load in the loop, from7; https://github.com/llvm/llvm-project/issues/997018define void @dead_load(ptr %p, i16 %start) {9; CHECK-LABEL: define void @dead_load(10; CHECK-SAME: ptr [[P:%.*]], i16 [[START:%.*]]) #[[ATTR0:[0-9]+]] {11; CHECK-NEXT: [[ENTRY:.*:]]12; CHECK-NEXT: [[START_EXT:%.*]] = sext i16 [[START]] to i6413; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[START_EXT]], i64 111)14; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[SMAX]], [[START_EXT]]15; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP0]], i64 1)16; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[SMAX]], [[UMIN]]17; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[START_EXT]]18; CHECK-NEXT: [[TMP3:%.*]] = udiv i64 [[TMP2]], 319; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[UMIN]], [[TMP3]]20; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], 121; CHECK-NEXT: br label %[[VECTOR_PH:.*]]22; CHECK: [[VECTOR_PH]]:23; CHECK-NEXT: [[TMP15:%.*]] = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()24; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[START_EXT]], i64 025; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i64> [[DOTSPLATINSERT]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer26; CHECK-NEXT: [[TMP17:%.*]] = mul <vscale x 8 x i64> [[TMP15]], splat (i64 3)27; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 8 x i64> [[DOTSPLAT]], [[TMP17]]28; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]29; CHECK: [[VECTOR_BODY]]:30; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 8 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]31; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP5]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]32; CHECK-NEXT: [[TMP16:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)33; CHECK-NEXT: [[TMP19:%.*]] = zext i32 [[TMP16]] to i6434; CHECK-NEXT: [[TMP20:%.*]] = mul i64 3, [[TMP19]]35; CHECK-NEXT: [[DOTSPLATINSERT1:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[TMP20]], i64 036; CHECK-NEXT: [[DOTSPLAT2:%.*]] = shufflevector <vscale x 8 x i64> [[DOTSPLATINSERT1]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer37; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i16, ptr [[P]], <vscale x 8 x i64> [[VEC_IND]]38; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x ptr> align 2 [[TMP21]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP16]])39; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP19]]40; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 8 x i64> [[VEC_IND]], [[DOTSPLAT2]]41; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[AVL_NEXT]], 042; CHECK-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]43; CHECK: [[MIDDLE_BLOCK]]:44; CHECK-NEXT: br label %[[EXIT:.*]]45; CHECK: [[EXIT]]:46; CHECK-NEXT: ret void47;48entry:49 %start.ext = sext i16 %start to i6450 br label %loop51 52loop:53 %iv = phi i64 [ %start.ext, %entry ], [ %iv.next, %loop ]54 %gep = getelementptr i16, ptr %p, i64 %iv55 store i16 0, ptr %gep, align 256 %l = load i16, ptr %gep, align 257 %iv.next = add i64 %iv, 358 %cmp = icmp slt i64 %iv, 11159 br i1 %cmp, label %loop, label %exit60 61exit:62 ret void63}64 65; Test case for https://github.com/llvm/llvm-project/issues/100464.66; Loop with a live-out %l and scalar epilogue required due to an interleave67; group. As the scalar epilogue is required the live-out is fed from the scalar68; epilogue and dead in the vector loop.69define i8 @dead_live_out_due_to_scalar_epilogue_required(ptr %src, ptr %dst) {70; CHECK-LABEL: define i8 @dead_live_out_due_to_scalar_epilogue_required(71; CHECK-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]]) #[[ATTR0]] {72; CHECK-NEXT: [[ENTRY:.*:]]73; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]74; CHECK: [[VECTOR_MEMCHECK]]:75; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 100576; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SRC]], i64 100577; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP1]]78; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP]]79; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]80; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]81; CHECK: [[VECTOR_PH]]:82; CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.stepvector.nxv16i32()83; CHECK-NEXT: [[TMP1:%.*]] = mul <vscale x 16 x i32> [[TMP0]], splat (i32 4)84; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 16 x i32> zeroinitializer, [[TMP1]]85; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]86; CHECK: [[VECTOR_BODY]]:87; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 16 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]88; CHECK-NEXT: [[AVL:%.*]] = phi i32 [ 252, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]89; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 16, i1 true)90; CHECK-NEXT: [[TMP3:%.*]] = mul i32 4, [[TMP2]]91; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 16 x i32> poison, i32 [[TMP3]], i64 092; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 16 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer93; CHECK-NEXT: [[TMP9:%.*]] = sext <vscale x 16 x i32> [[VEC_IND]] to <vscale x 16 x i64>94; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[SRC]], <vscale x 16 x i64> [[TMP9]]95; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 16 x i8> @llvm.vp.gather.nxv16i8.nxv16p0(<vscale x 16 x ptr> align 1 [[TMP6]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP2]]), !alias.scope [[META3:![0-9]+]]96; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[DST]], <vscale x 16 x i64> [[TMP9]]97; CHECK-NEXT: call void @llvm.vp.scatter.nxv16i8.nxv16p0(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x ptr> align 1 [[TMP7]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP2]]), !alias.scope [[META6:![0-9]+]], !noalias [[META3]]98; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP2]]99; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 16 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]100; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[AVL_NEXT]], 0101; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]102; CHECK: [[MIDDLE_BLOCK]]:103; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP2]] to i64104; CHECK-NEXT: [[TMP11:%.*]] = sub i64 [[TMP10]], 1105; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()106; CHECK-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP12]], 16107; CHECK-NEXT: [[TMP17:%.*]] = mul i64 [[TMP13]], 0108; CHECK-NEXT: [[TMP15:%.*]] = extractelement <vscale x 16 x i8> [[WIDE_MASKED_GATHER]], i64 [[TMP11]]109; CHECK-NEXT: br label %[[EXIT:.*]]110; CHECK: [[SCALAR_PH]]:111; CHECK-NEXT: br label %[[LOOP:.*]]112; CHECK: [[LOOP]]:113; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]114; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[IV]] to i64115; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IDXPROM]]116; CHECK-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1117; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IDXPROM]]118; CHECK-NEXT: store i8 0, ptr [[GEP_DST]], align 1119; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 4120; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IV]], 1001121; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP9:![0-9]+]]122; CHECK: [[EXIT]]:123; CHECK-NEXT: [[R:%.*]] = phi i8 [ [[L]], %[[LOOP]] ], [ [[TMP15]], %[[MIDDLE_BLOCK]] ]124; CHECK-NEXT: ret i8 [[R]]125;126entry:127 br label %loop128 129loop:130 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]131 %idxprom = sext i32 %iv to i64132 %gep.src = getelementptr i8, ptr %src, i64 %idxprom133 %l = load i8, ptr %gep.src, align 1134 %gep.dst = getelementptr i8, ptr %dst, i64 %idxprom135 store i8 0, ptr %gep.dst, align 1136 %iv.next = add i32 %iv, 4137 %cmp = icmp ult i32 %iv, 1001138 br i1 %cmp, label %loop, label %exit139 140exit:141 %r = phi i8 [ %l, %loop ]142 ret i8 %r143}144 145declare i16 @llvm.umax.i16(i16, i16)146 147; Test case for https://github.com/llvm/llvm-project/issues/106780.148define i32 @cost_of_exit_branch_and_cond_insts(ptr %a, ptr %b, i1 %c, i16 %x) #0 {149; CHECK-LABEL: define i32 @cost_of_exit_branch_and_cond_insts(150; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i1 [[C:%.*]], i16 [[X:%.*]]) #[[ATTR2:[0-9]+]] {151; CHECK-NEXT: [[ENTRY:.*]]:152; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[X]] to i32153; CHECK-NEXT: [[UMAX3:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP0]], i32 111)154; CHECK-NEXT: [[TMP1:%.*]] = sub i32 770, [[UMAX3]]155; CHECK-NEXT: [[SMAX4:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP1]], i32 0)156; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[SMAX4]], 1157; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i32 [[TMP2]], 19158; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]159; CHECK: [[VECTOR_MEMCHECK]]:160; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A]], i64 1161; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[X]] to i32162; CHECK-NEXT: [[UMAX1:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP3]], i32 111)163; CHECK-NEXT: [[TMP4:%.*]] = sub i32 770, [[UMAX1]]164; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP4]], i32 0)165; CHECK-NEXT: [[TMP5:%.*]] = zext nneg i32 [[SMAX]] to i64166; CHECK-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[TMP5]], 2167; CHECK-NEXT: [[TMP7:%.*]] = add nuw nsw i64 [[TMP6]], 4168; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP7]]169; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[A]], [[SCEVGEP2]]170; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[B]], [[SCEVGEP]]171; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]172; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]173; CHECK: [[VECTOR_PH]]:174; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP2]], 8175; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[N_MOD_VF]], 0176; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i32 8, i32 [[N_MOD_VF]]177; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP2]], [[TMP9]]178; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i1> poison, i1 [[C]], i64 0179; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i1> [[BROADCAST_SPLATINSERT]], <8 x i1> poison, <8 x i32> zeroinitializer180; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]181; CHECK: [[VECTOR_BODY]]:182; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE18:.*]] ]183; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[B]], i32 [[INDEX]]184; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]185; CHECK: [[PRED_STORE_IF]]:186; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META10:![0-9]+]], !noalias [[META13:![0-9]+]]187; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]188; CHECK: [[PRED_STORE_CONTINUE]]:189; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]190; CHECK: [[PRED_STORE_IF5]]:191; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META10]], !noalias [[META13]]192; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]193; CHECK: [[PRED_STORE_CONTINUE6]]:194; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]195; CHECK: [[PRED_STORE_IF7]]:196; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META10]], !noalias [[META13]]197; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE8]]198; CHECK: [[PRED_STORE_CONTINUE8]]:199; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]200; CHECK: [[PRED_STORE_IF9]]:201; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META10]], !noalias [[META13]]202; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE10]]203; CHECK: [[PRED_STORE_CONTINUE10]]:204; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]205; CHECK: [[PRED_STORE_IF11]]:206; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META10]], !noalias [[META13]]207; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE12]]208; CHECK: [[PRED_STORE_CONTINUE12]]:209; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14:.*]]210; CHECK: [[PRED_STORE_IF13]]:211; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META10]], !noalias [[META13]]212; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE14]]213; CHECK: [[PRED_STORE_CONTINUE14]]:214; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF15:.*]], label %[[PRED_STORE_CONTINUE16:.*]]215; CHECK: [[PRED_STORE_IF15]]:216; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META10]], !noalias [[META13]]217; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE16]]218; CHECK: [[PRED_STORE_CONTINUE16]]:219; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF17:.*]], label %[[PRED_STORE_CONTINUE18]]220; CHECK: [[PRED_STORE_IF17]]:221; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META10]], !noalias [[META13]]222; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE18]]223; CHECK: [[PRED_STORE_CONTINUE18]]:224; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr align 4 [[TMP11]], <8 x i1> [[BROADCAST_SPLAT]]), !alias.scope [[META13]]225; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8226; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]227; CHECK-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]228; CHECK: [[MIDDLE_BLOCK]]:229; CHECK-NEXT: br label %[[SCALAR_PH]]230; CHECK: [[SCALAR_PH]]:231; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]232; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]233; CHECK: [[LOOP_HEADER]]:234; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]235; CHECK-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_EXITING:.*]]236; CHECK: [[THEN]]:237; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[IV]]238; CHECK-NEXT: store i1 false, ptr [[A]], align 1239; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4240; CHECK-NEXT: br label %[[LOOP_EXITING]]241; CHECK: [[LOOP_EXITING]]:242; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1243; CHECK-NEXT: [[UMAX:%.*]] = tail call i16 @llvm.umax.i16(i16 [[X]], i16 111)244; CHECK-NEXT: [[UMAX_EXT:%.*]] = zext i16 [[UMAX]] to i32245; CHECK-NEXT: [[SUB:%.*]] = sub i32 770, [[UMAX_EXT]]246; CHECK-NEXT: [[EC:%.*]] = icmp slt i32 [[IV]], [[SUB]]247; CHECK-NEXT: br i1 [[EC]], label %[[LOOP_LATCH]], label %[[EXIT:.*]]248; CHECK: [[LOOP_LATCH]]:249; CHECK-NEXT: br label %[[LOOP_HEADER]], !llvm.loop [[LOOP16:![0-9]+]]250; CHECK: [[EXIT]]:251; CHECK-NEXT: br label %[[RETURN:.*]]252; CHECK: [[RETURN]]:253; CHECK-NEXT: ret i32 0254;255entry:256 br label %loop.header257 258loop.header:259 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]260 br i1 %c, label %then, label %loop.exiting261 262then:263 %gep = getelementptr inbounds i32, ptr %b, i32 %iv264 store i1 false, ptr %a, align 1265 store i32 0, ptr %gep, align 4266 br label %loop.exiting267 268loop.exiting:269 %iv.next = add i32 %iv, 1270 %umax = tail call i16 @llvm.umax.i16(i16 %x, i16 111)271 %umax.ext = zext i16 %umax to i32272 %sub = sub i32 770, %umax.ext273 %ec = icmp slt i32 %iv, %sub274 br i1 %ec, label %loop.latch, label %exit275 276loop.latch:277 br label %loop.header278 279exit:280 br label %return281 282return:283 ret i32 0284}285 286; Test case for https://github.com/llvm/llvm-project/issues/107473.287define void @test_phi_in_latch_redundant(ptr %dst, i32 %a) {288; CHECK-LABEL: define void @test_phi_in_latch_redundant(289; CHECK-SAME: ptr [[DST:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {290; CHECK-NEXT: [[ENTRY:.*:]]291; CHECK-NEXT: br label %[[VECTOR_PH:.*]]292; CHECK: [[VECTOR_PH]]:293; CHECK-NEXT: [[TMP0:%.*]] = xor i32 [[A]], -1294; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[TMP0]], i64 0295; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer296; CHECK-NEXT: [[TMP6:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64()297; CHECK-NEXT: [[TMP7:%.*]] = mul <vscale x 4 x i64> [[TMP6]], splat (i64 9)298; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 4 x i64> zeroinitializer, [[TMP7]]299; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]300; CHECK: [[VECTOR_BODY]]:301; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]302; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 37, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]303; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)304; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP8]] to i64305; CHECK-NEXT: [[TMP9:%.*]] = mul i64 9, [[TMP5]]306; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP9]], i64 0307; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT1]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer308; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[DST]], <vscale x 4 x i64> [[VEC_IND]]309; CHECK-NEXT: call void @llvm.vp.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> [[BROADCAST_SPLAT]], <vscale x 4 x ptr> align 4 [[TMP16]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP8]])310; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP5]]311; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT2]]312; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[AVL_NEXT]], 0313; CHECK-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]314; CHECK: [[MIDDLE_BLOCK]]:315; CHECK-NEXT: br label %[[EXIT:.*]]316; CHECK: [[EXIT]]:317; CHECK-NEXT: ret void318;319entry:320 br label %loop.header321 322loop.header:323 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]324 br i1 false, label %loop.latch, label %then325 326then:327 %not.a = xor i32 %a, -1328 br label %loop.latch329 330loop.latch:331 %p = phi i32 [ %not.a, %then ], [ 0, %loop.header ]332 %gep = getelementptr i32, ptr %dst, i64 %iv333 store i32 %p, ptr %gep, align 4334 %iv.next = add i64 %iv, 9335 %ec = icmp slt i64 %iv, 322336 br i1 %ec, label %loop.header, label %exit337 338exit:339 ret void340}341 342; Test for https://github.com/llvm/llvm-project/issues/108098.343define void @gather_interleave_group_with_dead_insert_pos(i64 %N, ptr noalias %src, ptr noalias %dst) #0 {344; CHECK-LABEL: define void @gather_interleave_group_with_dead_insert_pos(345; CHECK-SAME: i64 [[N:%.*]], ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR2]] {346; CHECK-NEXT: [[ENTRY:.*:]]347; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 0)348; CHECK-NEXT: [[TMP0:%.*]] = add nuw i64 [[SMAX]], 1349; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 1350; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1351; CHECK-NEXT: br label %[[VECTOR_PH:.*]]352; CHECK: [[VECTOR_PH]]:353; CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64()354; CHECK-NEXT: [[TMP4:%.*]] = mul nsw <vscale x 4 x i64> [[TMP9]], splat (i64 2)355; CHECK-NEXT: [[INDUCTION:%.*]] = add nsw <vscale x 4 x i64> zeroinitializer, [[TMP4]]356; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]357; CHECK: [[VECTOR_BODY]]:358; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]359; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]360; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP2]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]361; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)362; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP10]] to i64363; CHECK-NEXT: [[TMP12:%.*]] = mul nsw i64 2, [[TMP16]]364; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP12]], i64 0365; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[DOTSPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer366; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[EVL_BASED_IV]], 2367; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[OFFSET_IDX]]368; CHECK-NEXT: [[INTERLEAVE_EVL:%.*]] = mul nuw nsw i32 [[TMP10]], 2369; CHECK-NEXT: [[WIDE_MASKED_VEC:%.*]] = call <vscale x 8 x i8> @llvm.vp.load.nxv8i8.p0(ptr align 1 [[TMP22]], <vscale x 8 x i1> splat (i1 true), i32 [[INTERLEAVE_EVL]])370; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.vector.deinterleave2.nxv8i8(<vscale x 8 x i8> [[WIDE_MASKED_VEC]])371; CHECK-NEXT: [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[STRIDED_VEC]], 0372; CHECK-NEXT: [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[STRIDED_VEC]], 1373; CHECK-NEXT: [[TMP18:%.*]] = zext <vscale x 4 x i8> [[TMP17]] to <vscale x 4 x i32>374; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr [[DST]], <vscale x 4 x i64> [[VEC_IND]]375; CHECK-NEXT: call void @llvm.vp.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> [[TMP18]], <vscale x 4 x ptr> align 4 [[TMP19]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])376; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]377; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP16]]378; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <vscale x 4 x i64> [[VEC_IND]], [[DOTSPLAT]]379; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i64 [[AVL_NEXT]], 0380; CHECK-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]381; CHECK: [[MIDDLE_BLOCK]]:382; CHECK-NEXT: br label %[[EXIT:.*]]383; CHECK: [[EXIT]]:384; CHECK-NEXT: ret void385;386entry:387 br label %loop388 389loop:390 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]391 %gep.src.0 = getelementptr i8, ptr %src, i64 %iv392 %l.dead = load i8, ptr %gep.src.0, align 1393 %iv.1 = add i64 %iv, 1394 %gep.src.1 = getelementptr i8, ptr %src, i64 %iv.1395 %l.1 = load i8, ptr %gep.src.1, align 1396 %ext = zext i8 %l.1 to i32397 %gep.dst = getelementptr i32, ptr %dst, i64 %iv398 store i32 %ext, ptr %gep.dst, align 4399 %iv.next = add nsw i64 %iv, 2400 %ec = icmp slt i64 %iv, %N401 br i1 %ec, label %loop, label %exit402 403exit:404 ret void405}406 407attributes #0 = { "target-features"="+64bit,+v" }408 409;.410; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}411; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}412; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}413; CHECK: [[META3]] = !{[[META4:![0-9]+]]}414; CHECK: [[META4]] = distinct !{[[META4]], [[META5:![0-9]+]]}415; CHECK: [[META5]] = distinct !{[[META5]], !"LVerDomain"}416; CHECK: [[META6]] = !{[[META7:![0-9]+]]}417; CHECK: [[META7]] = distinct !{[[META7]], [[META5]]}418; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}419; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]}420; CHECK: [[META10]] = !{[[META11:![0-9]+]]}421; CHECK: [[META11]] = distinct !{[[META11]], [[META12:![0-9]+]]}422; CHECK: [[META12]] = distinct !{[[META12]], !"LVerDomain"}423; CHECK: [[META13]] = !{[[META14:![0-9]+]]}424; CHECK: [[META14]] = distinct !{[[META14]], [[META12]]}425; CHECK: [[LOOP15]] = distinct !{[[LOOP15]], [[META1]], [[META2]]}426; CHECK: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]]}427; CHECK: [[LOOP17]] = distinct !{[[LOOP17]], [[META1]], [[META2]]}428; CHECK: [[LOOP18]] = distinct !{[[LOOP18]], [[META1]], [[META2]]}429;.430