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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=loop-vectorize -mtriple riscv64-linux-gnu -mattr=+v,+f -S 2>%t | FileCheck %s3 4; This is a collection of tests whose only purpose is to show changes in the5; default configuration. Please keep these tests minimal - if you're testing6; functionality of some specific configuration, please place that in a7; separate test file with a hard coded configuration (even if that8; configuration is the current default).9 10target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"11target triple = "riscv64"12 13define void @vector_add(ptr noalias nocapture %a, i64 %v) {14; CHECK-LABEL: @vector_add(15; CHECK-NEXT: entry:16; CHECK-NEXT: br label [[VECTOR_PH:%.*]]17; CHECK: vector.ph:18; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[V:%.*]], i64 019; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer20; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]21; CHECK: vector.body:22; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]23; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1024, [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]24; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)25; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[INDEX]]26; CHECK-NEXT: [[WIDE_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP7]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP10]])27; CHECK-NEXT: [[TMP9:%.*]] = add <vscale x 2 x i64> [[WIDE_LOAD]], [[BROADCAST_SPLAT]]28; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP9]], ptr align 8 [[TMP7]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP10]])29; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP10]] to i6430; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP8]], [[INDEX]]31; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP8]]32; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[AVL_NEXT]], 033; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]34; CHECK: middle.block:35; CHECK-NEXT: br label [[FOR_BODY:%.*]]36; CHECK: for.end:37; CHECK-NEXT: ret void38;39entry:40 br label %for.body41 42for.body:43 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]44 %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv45 %elem = load i64, ptr %arrayidx46 %add = add i64 %elem, %v47 store i64 %add, ptr %arrayidx48 %iv.next = add nuw nsw i64 %iv, 149 %exitcond.not = icmp eq i64 %iv.next, 102450 br i1 %exitcond.not, label %for.end, label %for.body51 52for.end:53 ret void54}55 56define i64 @vector_add_reduce(ptr noalias nocapture %a) {57; CHECK-LABEL: @vector_add_reduce(58; CHECK-NEXT: entry:59; CHECK-NEXT: br label [[VECTOR_PH:%.*]]60; CHECK: vector.ph:61; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]62; CHECK: vector.body:63; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]64; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ]65; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1024, [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]66; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)67; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[INDEX]]68; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP7]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP8]])69; CHECK-NEXT: [[TMP12:%.*]] = add <vscale x 2 x i64> [[VEC_PHI]], [[VP_OP_LOAD]]70; CHECK-NEXT: [[TMP9]] = call <vscale x 2 x i64> @llvm.vp.merge.nxv2i64(<vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> [[TMP12]], <vscale x 2 x i64> [[VEC_PHI]], i32 [[TMP8]])71; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP8]] to i6472; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP13]], [[INDEX]]73; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP13]]74; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[AVL_NEXT]], 075; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]76; CHECK: middle.block:77; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> [[TMP9]])78; CHECK-NEXT: br label [[FOR_BODY:%.*]]79; CHECK: for.end:80; CHECK-NEXT: ret i64 [[TMP11]]81;82entry:83 br label %for.body84 85for.body:86 %iv = phi i64 [0, %entry], [%iv.next, %for.body]87 %sum = phi i64 [0, %entry], [%sum.next, %for.body]88 %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv89 %elem = load i64, ptr %arrayidx90 %iv.next = add nuw nsw i64 %iv, 191 %sum.next = add i64 %sum, %elem92 %exitcond.not = icmp eq i64 %iv.next, 102493 br i1 %exitcond.not, label %for.end, label %for.body94 95for.end:96 ret i64 %sum.next97}98 99