104 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -passes=loop-vectorize \3; RUN: -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue \4; RUN: -mtriple=riscv64 -mattr=+v -S < %s | FileCheck %s5 6; Make sure we do not vectorize a loop with a widened int induction.7define void @test_wide_integer_induction(ptr noalias %a, i64 %N) {8; CHECK-LABEL: define void @test_wide_integer_induction(9; CHECK-SAME: ptr noalias [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {10; CHECK-NEXT: entry:11; CHECK-NEXT: br label [[ENTRY:%.*]]12; CHECK: vector.ph:13; CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()14; CHECK-NEXT: [[TMP1:%.*]] = mul <vscale x 2 x i64> [[TMP9]], splat (i64 1)15; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i64> zeroinitializer, [[TMP1]]16; CHECK-NEXT: br label [[FOR_BODY:%.*]]17; CHECK: vector.body:18; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDEX_EVL_NEXT:%.*]], [[FOR_BODY]] ]19; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i64> [ [[INDUCTION]], [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[FOR_BODY]] ]20; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], [[ENTRY]] ], [ [[AVL_NEXT:%.*]], [[FOR_BODY]] ]21; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)22; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i6423; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP12]], i64 024; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer25; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[EVL_BASED_IV]]26; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[VEC_IND]], ptr align 8 [[TMP14]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP11]])27; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP12]], [[EVL_BASED_IV]]28; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP12]]29; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]30; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[AVL_NEXT]], 031; CHECK-NEXT: br i1 [[TMP15]], label [[MIDDLE_BLOCK:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]32; CHECK: middle.block:33; CHECK-NEXT: br label [[FOR_BODY1:%.*]]34; CHECK: for.cond.cleanup:35; CHECK-NEXT: ret void36;37entry:38 br label %for.body39 40for.body:41 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]42 %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv43 store i64 %iv, ptr %arrayidx, align 844 %iv.next = add nuw nsw i64 %iv, 145 %exitcond.not = icmp eq i64 %iv.next, %N46 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body47 48for.cond.cleanup:49 ret void50}51 52; Make sure we do not vectorize a loop with a widened ptr induction.53define void @test_wide_ptr_induction(ptr noalias %a, ptr noalias %b, i64 %N) {54; CHECK-LABEL: define void @test_wide_ptr_induction(55; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {56; CHECK-NEXT: entry:57; CHECK-NEXT: br label [[VECTOR_PH:%.*]]58; CHECK: vector.ph:59; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]60; CHECK: vector.body:61; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]62; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[B]], [[VECTOR_PH]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ]63; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]64; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()65; CHECK-NEXT: [[TMP6:%.*]] = mul <vscale x 2 x i64> [[TMP5]], splat (i64 8)66; CHECK-NEXT: [[VECTOR_GEP:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <vscale x 2 x i64> [[TMP6]]67; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)68; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[EVL_BASED_IV]]69; CHECK-NEXT: call void @llvm.vp.store.nxv2p0.p0(<vscale x 2 x ptr> [[VECTOR_GEP]], ptr align 8 [[TMP8]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP7]])70; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP7]] to i6471; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP9]], [[EVL_BASED_IV]]72; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP9]]73; CHECK-NEXT: [[TMP11:%.*]] = mul i64 8, [[TMP9]]74; CHECK-NEXT: [[PTR_IND]] = getelementptr i8, ptr [[POINTER_PHI]], i64 [[TMP11]]75; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[AVL_NEXT]], 076; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]77; CHECK: middle.block:78; CHECK-NEXT: br label [[FOR_BODY:%.*]]79; CHECK: for.cond.cleanup:80; CHECK-NEXT: ret void81;82entry:83 br label %for.body84 85for.body:86 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]87 %addr = phi ptr [ %incdec.ptr, %for.body ], [ %b, %entry ]88 %incdec.ptr = getelementptr inbounds i8, ptr %addr, i64 889 %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv90 store ptr %addr, ptr %arrayidx, align 891 %iv.next = add nuw nsw i64 %iv, 192 %exitcond.not = icmp eq i64 %iv.next, %N93 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body94 95for.cond.cleanup:96 ret void97}98;.99; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}100; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}101; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}102; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}103;.104