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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -scalable-vectorization=on -S %s | FileCheck %s3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"5target triple = "riscv64-unknown-linux-gnu"6 7define i64 @pr97452_scalable_vf1_for(ptr %src, ptr noalias %dst) #0 {8; CHECK-LABEL: define i64 @pr97452_scalable_vf1_for(9; CHECK-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR0:[0-9]+]] {10; CHECK-NEXT: [[ENTRY:.*:]]11; CHECK-NEXT: br label %[[VECTOR_PH:.*]]12; CHECK: [[VECTOR_PH]]:13; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()14; CHECK-NEXT: [[TMP1:%.*]] = mul nuw i64 [[TMP0]], 215; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i3216; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vscale.i32()17; CHECK-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP3]], 218; CHECK-NEXT: [[TMP5:%.*]] = sub i32 [[TMP4]], 119; CHECK-NEXT: [[VECTOR_RECUR_INIT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 0, i32 [[TMP5]]20; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]21; CHECK: [[VECTOR_BODY]]:22; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]23; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <vscale x 2 x i64> [ [[VECTOR_RECUR_INIT]], %[[VECTOR_PH]] ], [ [[VP_OP_LOAD:%.*]], %[[VECTOR_BODY]] ]24; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 23, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]25; CHECK-NEXT: [[PREV_EVL:%.*]] = phi i32 [ [[TMP2]], %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]26; CHECK-NEXT: [[TMP6]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)27; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[EVL_BASED_IV]]28; CHECK-NEXT: [[VP_OP_LOAD]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP9]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP6]])29; CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> [[VECTOR_RECUR]], <vscale x 2 x i64> [[VP_OP_LOAD]], i32 -1, <vscale x 2 x i1> splat (i1 true), i32 [[PREV_EVL]], i32 [[TMP6]])30; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[EVL_BASED_IV]]31; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP10]], ptr align 8 [[TMP11]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP6]])32; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP6]] to i6433; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP12]], [[EVL_BASED_IV]]34; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP12]]35; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[AVL_NEXT]], 036; CHECK-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]37; CHECK: [[MIDDLE_BLOCK]]:38; CHECK-NEXT: [[TMP15:%.*]] = sub i64 [[TMP12]], 139; CHECK-NEXT: [[TMP16:%.*]] = sub i64 [[TMP15]], 140; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()41; CHECK-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 242; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[TMP18]], 043; CHECK-NEXT: [[TMP20:%.*]] = extractelement <vscale x 2 x i64> [[VP_OP_LOAD]], i64 [[TMP16]]44; CHECK-NEXT: [[TMP21:%.*]] = call i32 @llvm.vscale.i32()45; CHECK-NEXT: [[TMP22:%.*]] = mul nuw i32 [[TMP21]], 246; CHECK-NEXT: [[TMP23:%.*]] = sub i32 [[TMP22]], 147; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 2 x i64> [[VECTOR_RECUR]], i32 [[TMP23]]48; CHECK-NEXT: [[TMP25:%.*]] = icmp eq i64 [[TMP15]], 049; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP25]], i64 [[TMP24]], i64 [[TMP20]]50; CHECK-NEXT: br label %[[EXIT:.*]]51; CHECK: [[EXIT]]:52; CHECK-NEXT: ret i64 [[TMP26]]53;54entry:55 br label %loop56 57loop:58 %for = phi i64 [ 0, %entry ], [ %l, %loop ]59 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]60 %iv.next = add i64 %iv, 161 %gep.src = getelementptr inbounds i64, ptr %src, i64 %iv62 %l = load i64, ptr %gep.src, align 863 %gep.dst = getelementptr inbounds i64, ptr %dst, i64 %iv64 store i64 %for, ptr %gep.dst65 %ec = icmp eq i64 %iv, 2266 br i1 %ec, label %exit, label %loop67 68exit:69 %res = phi i64 [ %for, %loop ]70 ret i64 %res71}72 73attributes #0 = { "target-features"="+64bit,+v,+zvl128b,+zvl256b" }74;.75; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}76; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}77; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}78;.79