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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -S %s | FileCheck %s3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"5target triple = "riscv64-unknown-linux-gnu"6 7; Test case for https://github.com/llvm/llvm-project/issues/106417.8define void @skip_free_iv_truncate(i16 %x, ptr %A) #0 {9; CHECK-LABEL: define void @skip_free_iv_truncate(10; CHECK-SAME: i16 [[X:%.*]], ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {11; CHECK-NEXT: [[ENTRY:.*:]]12; CHECK-NEXT: [[X_I32:%.*]] = sext i16 [[X]] to i3213; CHECK-NEXT: [[X_I64:%.*]] = sext i16 [[X]] to i6414; CHECK-NEXT: [[INVARIANT_GEP:%.*]] = getelementptr i8, ptr [[A]], i64 -815; CHECK-NEXT: [[SMAX20:%.*]] = call i64 @llvm.smax.i64(i64 [[X_I64]], i64 99)16; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[SMAX20]], [[X_I64]]17; CHECK-NEXT: [[UMIN21:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP0]], i64 1)18; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[SMAX20]], [[UMIN21]]19; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[X_I64]]20; CHECK-NEXT: [[TMP3:%.*]] = udiv i64 [[TMP2]], 321; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[UMIN21]], [[TMP3]]22; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], 123; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]24; CHECK: [[VECTOR_MEMCHECK]]:25; CHECK-NEXT: [[TMP31:%.*]] = shl nsw i64 [[X_I64]], 126; CHECK-NEXT: [[SCEVGEP9:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP31]]27; CHECK-NEXT: [[SMAX10:%.*]] = call i64 @llvm.smax.i64(i64 [[X_I64]], i64 99)28; CHECK-NEXT: [[TMP32:%.*]] = sub i64 [[SMAX10]], [[X_I64]]29; CHECK-NEXT: [[UMIN11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP32]], i64 1)30; CHECK-NEXT: [[TMP33:%.*]] = sub i64 [[SMAX10]], [[UMIN11]]31; CHECK-NEXT: [[TMP34:%.*]] = sub i64 [[TMP33]], [[X_I64]]32; CHECK-NEXT: [[TMP35:%.*]] = udiv i64 [[TMP34]], 333; CHECK-NEXT: [[TMP36:%.*]] = add i64 [[UMIN11]], [[TMP35]]34; CHECK-NEXT: [[TMP37:%.*]] = mul i64 [[TMP36]], 635; CHECK-NEXT: [[TMP38:%.*]] = add i64 [[TMP37]], [[TMP31]]36; CHECK-NEXT: [[TMP39:%.*]] = add i64 [[TMP38]], 237; CHECK-NEXT: [[SCEVGEP12:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP39]]38; CHECK-NEXT: [[TMP40:%.*]] = shl nsw i64 [[X_I64]], 339; CHECK-NEXT: [[SCEVGEP13:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP40]]40; CHECK-NEXT: [[TMP41:%.*]] = mul i64 [[TMP36]], 2441; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP41]], [[TMP40]]42; CHECK-NEXT: [[TMP43:%.*]] = add i64 [[TMP42]], 843; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP43]]44; CHECK-NEXT: [[TMP44:%.*]] = add nsw i64 [[TMP40]], -845; CHECK-NEXT: [[SCEVGEP15:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP44]]46; CHECK-NEXT: [[SCEVGEP16:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP42]]47; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[SCEVGEP9]], [[SCEVGEP14]]48; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SCEVGEP13]], [[SCEVGEP12]]49; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]50; CHECK-NEXT: [[BOUND017:%.*]] = icmp ult ptr [[SCEVGEP9]], [[SCEVGEP16]]51; CHECK-NEXT: [[BOUND118:%.*]] = icmp ult ptr [[SCEVGEP15]], [[SCEVGEP12]]52; CHECK-NEXT: [[FOUND_CONFLICT19:%.*]] = and i1 [[BOUND017]], [[BOUND118]]53; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT19]]54; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]55; CHECK: [[VECTOR_PH]]:56; CHECK-NEXT: [[TMP53:%.*]] = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()57; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[X_I64]], i64 058; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i64> [[DOTSPLATINSERT]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer59; CHECK-NEXT: [[TMP55:%.*]] = mul <vscale x 8 x i64> [[TMP53]], splat (i64 3)60; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 8 x i64> [[DOTSPLAT]], [[TMP55]]61; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]62; CHECK: [[VECTOR_BODY]]:63; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 8 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]64; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP5]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]65; CHECK-NEXT: [[TMP27:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)66; CHECK-NEXT: [[TMP28:%.*]] = zext i32 [[TMP27]] to i6467; CHECK-NEXT: [[TMP58:%.*]] = mul i64 3, [[TMP28]]68; CHECK-NEXT: [[DOTSPLATINSERT24:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[TMP58]], i64 069; CHECK-NEXT: [[DOTSPLAT25:%.*]] = shufflevector <vscale x 8 x i64> [[DOTSPLATINSERT24]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer70; CHECK-NEXT: [[TMP59:%.*]] = getelementptr i16, ptr [[A]], <vscale x 8 x i64> [[VEC_IND]]71; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x ptr> align 2 [[TMP59]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP27]]), !alias.scope [[META0:![0-9]+]], !noalias [[META3:![0-9]+]]72; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP28]]73; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 8 x i64> [[VEC_IND]], [[DOTSPLAT25]]74; CHECK-NEXT: [[TMP29:%.*]] = icmp eq i64 [[AVL_NEXT]], 075; CHECK-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]76; CHECK: [[MIDDLE_BLOCK]]:77; CHECK-NEXT: br label %[[EXIT:.*]]78; CHECK: [[SCALAR_PH]]:79; CHECK-NEXT: br label %[[LOOP:.*]]80; CHECK: [[LOOP]]:81; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[X_I64]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]82; CHECK-NEXT: [[IV_CONV:%.*]] = phi i32 [ [[X_I32]], %[[SCALAR_PH]] ], [ [[TMP64:%.*]], %[[LOOP]] ]83; CHECK-NEXT: [[GEP_I64:%.*]] = getelementptr i64, ptr [[A]], i64 [[IV]]84; CHECK-NEXT: [[TMP61:%.*]] = load i64, ptr [[GEP_I64]], align 885; CHECK-NEXT: [[TMP62:%.*]] = sext i32 [[IV_CONV]] to i6486; CHECK-NEXT: [[GEP_CONV:%.*]] = getelementptr i64, ptr [[INVARIANT_GEP]], i64 [[TMP62]]87; CHECK-NEXT: [[TMP63:%.*]] = load i64, ptr [[GEP_CONV]], align 888; CHECK-NEXT: [[GEP_I16:%.*]] = getelementptr i16, ptr [[A]], i64 [[IV]]89; CHECK-NEXT: store i16 0, ptr [[GEP_I16]], align 290; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 391; CHECK-NEXT: [[TMP64]] = trunc i64 [[IV_NEXT]] to i3292; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[IV]], 9993; CHECK-NEXT: br i1 [[C]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP9:![0-9]+]]94; CHECK: [[EXIT]]:95; CHECK-NEXT: ret void96;97entry:98 %x.i32 = sext i16 %x to i3299 %x.i64 = sext i16 %x to i64100 %invariant.gep = getelementptr i8, ptr %A, i64 -8101 br label %loop102 103loop:104 %iv = phi i64 [ %x.i64, %entry ], [ %iv.next, %loop ]105 %iv.conv = phi i32 [ %x.i32, %entry ], [ %5, %loop ]106 %gep.i64 = getelementptr i64, ptr %A, i64 %iv107 %2 = load i64, ptr %gep.i64, align 8108 %3 = sext i32 %iv.conv to i64109 %gep.conv = getelementptr i64, ptr %invariant.gep, i64 %3110 %4 = load i64, ptr %gep.conv, align 8111 %gep.i16 = getelementptr i16, ptr %A, i64 %iv112 store i16 0, ptr %gep.i16, align 2113 %iv.next = add i64 %iv, 3114 %5 = trunc i64 %iv.next to i32115 %c = icmp slt i64 %iv, 99116 br i1 %c, label %loop, label %exit117 118exit:119 ret void120}121 122define void @test_3_inductions(ptr noalias %dst, ptr noalias %src, i64 %n) #1 {123; CHECK-LABEL: define void @test_3_inductions(124; CHECK-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {125; CHECK-NEXT: [[ENTRY:.*:]]126; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1127; CHECK-NEXT: br label %[[VECTOR_PH:.*]]128; CHECK: [[VECTOR_PH]]:129; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x ptr> poison, ptr [[DST]], i64 0130; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 2 x ptr> poison, <vscale x 2 x i32> zeroinitializer131; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.stepvector.nxv2i32()132; CHECK-NEXT: [[TMP2:%.*]] = mul <vscale x 2 x i32> [[TMP1]], splat (i32 2)133; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i32> splat (i32 1), [[TMP2]]134; CHECK-NEXT: [[INDUCTION1:%.*]] = add <vscale x 2 x i32> zeroinitializer, [[TMP2]]135; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]136; CHECK: [[VECTOR_BODY]]:137; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]138; CHECK-NEXT: [[VEC_IND2:%.*]] = phi <vscale x 2 x i32> [ [[INDUCTION1]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT5:%.*]], %[[VECTOR_BODY]] ]139; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP0]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]140; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)141; CHECK-NEXT: [[TMP4:%.*]] = mul i32 2, [[TMP3]]142; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <vscale x 2 x i32> poison, i32 [[TMP4]], i64 0143; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <vscale x 2 x i32> [[BROADCAST_SPLATINSERT3]], <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer144; CHECK-NEXT: [[TMP5:%.*]] = or <vscale x 2 x i32> [[VEC_IND2]], [[VEC_IND]]145; CHECK-NEXT: [[TMP6:%.*]] = sext <vscale x 2 x i32> [[TMP5]] to <vscale x 2 x i64>146; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[SRC]], <vscale x 2 x i64> [[TMP6]]147; CHECK-NEXT: call void @llvm.vp.scatter.nxv2p0.nxv2p0(<vscale x 2 x ptr> [[TMP7]], <vscale x 2 x ptr> align 8 [[BROADCAST_SPLAT]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP3]])148; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP3]] to i64149; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP8]]150; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i32> [[VEC_IND]], [[BROADCAST_SPLAT4]]151; CHECK-NEXT: [[VEC_IND_NEXT5]] = add <vscale x 2 x i32> [[VEC_IND2]], [[BROADCAST_SPLAT4]]152; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[AVL_NEXT]], 0153; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]154; CHECK: [[MIDDLE_BLOCK]]:155; CHECK-NEXT: br label %[[EXIT:.*]]156; CHECK: [[EXIT]]:157; CHECK-NEXT: ret void158;159entry:160 br label %loop161 162loop:163 %iv.0 = phi i32 [ 1, %entry ], [ %iv.0.next, %loop ]164 %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ]165 %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ]166 %iv.or = or i32 %iv.2, %iv.0167 %iv.or.ext = sext i32 %iv.or to i64168 %gep.src = getelementptr i8, ptr %src, i64 %iv.or.ext169 store ptr %gep.src, ptr %dst, align 8170 %iv.0.next = add i32 %iv.0, 2171 %iv.1.next = add i64 %iv.1, 1172 %iv.2.next = add i32 %iv.2, 2173 %ec = icmp eq i64 %iv.1, %n174 br i1 %ec, label %exit, label %loop175 176exit:177 ret void178}179 180define void @redundant_iv_trunc_for_cse(ptr noalias %src, ptr noalias %dst, i64 %n) #0 {181; CHECK-LABEL: define void @redundant_iv_trunc_for_cse(182; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {183; CHECK-NEXT: [[ENTRY:.*:]]184; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1185; CHECK-NEXT: br label %[[VECTOR_PH:.*]]186; CHECK: [[VECTOR_PH]]:187; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.stepvector.nxv4i32()188; CHECK-NEXT: [[TMP2:%.*]] = mul <vscale x 4 x i32> [[TMP1]], splat (i32 1)189; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 4 x i32> zeroinitializer, [[TMP2]]190; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]191; CHECK: [[VECTOR_BODY]]:192; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]193; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]194; CHECK-NEXT: [[VEC_IND1:%.*]] = phi <vscale x 4 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT2:%.*]], %[[VECTOR_BODY]] ]195; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP0]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]196; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)197; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[TMP3]], i64 0198; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer199; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[EVL_BASED_IV]]200; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP4]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP3]])201; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <vscale x 4 x i32> [[VP_OP_LOAD]], zeroinitializer202; CHECK-NEXT: [[TMP6:%.*]] = shl <vscale x 4 x i32> [[VEC_IND1]], splat (i32 16)203; CHECK-NEXT: [[PREDPHI:%.*]] = select <vscale x 4 x i1> [[TMP5]], <vscale x 4 x i32> [[TMP6]], <vscale x 4 x i32> [[VEC_IND]]204; CHECK-NEXT: [[TMP7:%.*]] = trunc <vscale x 4 x i32> [[PREDPHI]] to <vscale x 4 x i8>205; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[EVL_BASED_IV]]206; CHECK-NEXT: call void @llvm.vp.store.nxv4i8.p0(<vscale x 4 x i8> [[TMP7]], ptr align 1 [[TMP8]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP3]])207; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP3]] to i64208; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP9]], [[EVL_BASED_IV]]209; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP9]]210; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]211; CHECK-NEXT: [[VEC_IND_NEXT2]] = add <vscale x 4 x i32> [[VEC_IND1]], [[BROADCAST_SPLAT]]212; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[AVL_NEXT]], 0213; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]214; CHECK: [[MIDDLE_BLOCK]]:215; CHECK-NEXT: br label %[[EXIT:.*]]216; CHECK: [[EXIT]]:217; CHECK-NEXT: ret void218;219entry:220 br label %loop.header221 222loop.header:223 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]224 %gep.src = getelementptr inbounds i32, ptr %src, i64 %iv225 %l = load i32, ptr %gep.src226 %c.0 = icmp eq i32 %l, 0227 %trunc.iv = trunc i64 %iv to i32228 br i1 %c.0, label %then, label %loop.latch229 230then:231 %trunc.iv.2 = trunc i64 %iv to i32232 %shl.iv = shl i32 %trunc.iv.2, 16233 br label %loop.latch234 235loop.latch:236 %p = phi i32 [ %shl.iv, %then ], [ %trunc.iv, %loop.header ]237 %trunc.p = trunc i32 %p to i8238 %gep.dst = getelementptr inbounds i8, ptr %dst, i64 %iv239 store i8 %trunc.p, ptr %gep.dst, align 1240 %iv.next = add i64 %iv, 1241 %ec = icmp eq i64 %iv, %n242 br i1 %ec, label %exit, label %loop.header243 244exit:245 ret void246}247 248 249 250attributes #0 = { "target-features"="+64bit,+v,+zvl256b" }251attributes #1 = { "target-cpu"="sifive-p670" }252;.253; CHECK: [[META0]] = !{[[META1:![0-9]+]]}254; CHECK: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]}255; CHECK: [[META2]] = distinct !{[[META2]], !"LVerDomain"}256; CHECK: [[META3]] = !{[[META4:![0-9]+]], [[META5:![0-9]+]]}257; CHECK: [[META4]] = distinct !{[[META4]], [[META2]]}258; CHECK: [[META5]] = distinct !{[[META5]], [[META2]]}259; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META7:![0-9]+]], [[META8:![0-9]+]]}260; CHECK: [[META7]] = !{!"llvm.loop.isvectorized", i32 1}261; CHECK: [[META8]] = !{!"llvm.loop.unroll.runtime.disable"}262; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META7]]}263; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META7]], [[META8]]}264; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META7]], [[META8]]}265;.266