65 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -p loop-vectorize -mtriple riscv64 -mattr=+v < %s -S | FileCheck %s3 4; Make sure we don't duplicate the safe divisor cost in the VPlan cost model.5 6define void @pr154103(ptr noalias %a, ptr noalias %b, ptr noalias %c, ptr noalias %d) {7; CHECK-LABEL: define void @pr154103(8; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], ptr noalias [[D:%.*]]) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: [[ENTRY:.*]]:10; CHECK-NEXT: br label %[[LOOP:.*]]11; CHECK: [[LOOP]]:12; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]13; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[A]], i64 [[IV]]14; CHECK-NEXT: [[X:%.*]] = load i8, ptr [[GEP]], align 115; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[X]] to i6416; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 0, [[CONV]]17; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[DIV]], 018; CHECK-NEXT: br i1 [[CMP]], label %[[THEN:.*]], label %[[LATCH]]19; CHECK: [[THEN]]:20; CHECK-NEXT: [[Y:%.*]] = load i8, ptr [[B]], align 121; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[Y]] to i6422; CHECK-NEXT: [[NOT:%.*]] = xor i64 [[ZEXT]], 023; CHECK-NEXT: br label %[[LATCH]]24; CHECK: [[LATCH]]:25; CHECK-NEXT: [[COND:%.*]] = phi i64 [ [[NOT]], %[[THEN]] ], [ 0, %[[LOOP]] ]26; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[COND]] to i1627; CHECK-NEXT: store i16 [[TRUNC]], ptr [[C]], align 228; CHECK-NEXT: store i32 0, ptr [[D]], align 429; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 730; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV]], 031; CHECK-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]]32; CHECK: [[EXIT]]:33; CHECK-NEXT: ret void34;35entry:36 br label %loop37 38loop:39 %iv = phi i64 [ 1, %entry ], [ %iv.next, %latch ]40 %gep = getelementptr i8, ptr %a, i64 %iv41 %x = load i8, ptr %gep, align 142 %conv = zext i8 %x to i6443 %div = sdiv i64 0, %conv44 %cmp = icmp sgt i64 %div, 045 br i1 %cmp, label %then, label %latch46 47then:48 %y = load i8, ptr %b49 %zext = zext i8 %y to i6450 %not = xor i64 %zext, 051 br label %latch52 53latch:54 %cond = phi i64 [ %not, %then ], [ 0, %loop ]55 %trunc = trunc i64 %cond to i1656 store i16 %trunc, ptr %c57 store i32 0, ptr %d58 %iv.next = add i64 %iv, 759 %done = icmp eq i64 %iv, 060 br i1 %done, label %exit, label %loop61 62exit:63 ret void64}65