42 lines · plain
1; REQUIRES: asserts2; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfh -debug-only=loop-vectorize,vplan --disable-output -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s --check-prefix=ZVFH3; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfhmin -debug-only=loop-vectorize,vplan --disable-output -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s --check-prefix=ZVFHMIN4 5define void @add(ptr noalias nocapture readonly %src1, ptr noalias nocapture readonly %src2, i32 signext %size, ptr noalias nocapture writeonly %result) {6; ZVFH-LABEL: add7; ZVFH: LV(REG): VF = vscale x 48; ZVFH-NEXT: LV(REG): Found max usage: 2 item9; ZVFH-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 6 registers10; ZVFH-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers11; ZVFH-NEXT: LV(REG): Found invariant usage: 1 item12; ZVFH-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers13; ZVFHMIN-LABEL: add14; ZVFHMIN: LV(REG): VF = vscale x 415; ZVFHMIN-NEXT: LV(REG): Found max usage: 2 item16; ZVFHMIN-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 6 registers17; ZVFHMIN-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers18; ZVFHMIN-NEXT: LV(REG): Found invariant usage: 1 item19; ZVFHMIN-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers20 21entry:22 %conv = zext i32 %size to i6423 %cmp10.not = icmp eq i32 %size, 024 br i1 %cmp10.not, label %for.cond.cleanup, label %for.body25 26for.cond.cleanup:27 ret void28 29for.body:30 %i.011 = phi i64 [ %add4, %for.body ], [ 0, %entry ]31 %arrayidx = getelementptr inbounds half, ptr %src1, i64 %i.01132 %0 = load half, ptr %arrayidx, align 433 %arrayidx2 = getelementptr inbounds half, ptr %src2, i64 %i.01134 %1 = load half, ptr %arrayidx2, align 435 %add = fadd half %0, %136 %arrayidx3 = getelementptr inbounds half, ptr %result, i64 %i.01137 store half %add, ptr %arrayidx3, align 438 %add4 = add nuw nsw i64 %i.011, 139 %exitcond.not = icmp eq i64 %add4, %conv40 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body41}42