1052 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "for.body:" --version 52;; This is the loop in c++ being vectorize in this file with3;; vector.reverse4;; #pragma clang loop vectorize_width(4, scalable)5;; for (int i = N-1; i >= 0; --i)6;; a[i] = b[i] + 1.0;7 8; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -S < %s \9; RUN: | FileCheck --check-prefix=RV64 %s10 11; RUN: opt -passes=loop-vectorize -mtriple=riscv32 -mattr=+v -S < %s \12; RUN: | FileCheck --check-prefix=RV32 %s13 14; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v \15; RUN: -force-vector-interleave=2 -S < %s \16; RUN: | FileCheck --check-prefix=RV64-UF2 %s17 18define void @vector_reverse_i32(ptr noalias %A, ptr noalias %B) {19; RV64-LABEL: define void @vector_reverse_i32(20; RV64-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0:[0-9]+]] {21; RV64-NEXT: [[ENTRY:.*:]]22; RV64-NEXT: br label %[[VECTOR_PH:.*]]23; RV64: [[VECTOR_PH]]:24; RV64-NEXT: br label %[[VECTOR_BODY:.*]]25; RV64: [[VECTOR_BODY]]:26; RV64-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]27; RV64-NEXT: [[AVL:%.*]] = phi i64 [ 1023, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]28; RV64-NEXT: [[TMP19:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)29; RV64-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]30; RV64-NEXT: [[TMP7:%.*]] = add nsw i64 [[OFFSET_IDX]], -131; RV64-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP7]]32; RV64-NEXT: [[TMP24:%.*]] = zext i32 [[TMP19]] to i6433; RV64-NEXT: [[TMP9:%.*]] = mul i64 0, [[TMP24]]34; RV64-NEXT: [[TMP10:%.*]] = sub i64 [[TMP24]], 135; RV64-NEXT: [[TMP11:%.*]] = mul i64 -1, [[TMP10]]36; RV64-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP8]], i64 [[TMP9]]37; RV64-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP12]], i64 [[TMP11]]38; RV64-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP13]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP19]])39; RV64-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP19]])40; RV64-NEXT: [[TMP14:%.*]] = add <vscale x 4 x i32> [[REVERSE]], splat (i32 1)41; RV64-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP7]]42; RV64-NEXT: [[TMP16:%.*]] = zext i32 [[TMP19]] to i6443; RV64-NEXT: [[TMP25:%.*]] = mul i64 0, [[TMP16]]44; RV64-NEXT: [[TMP17:%.*]] = sub i64 [[TMP16]], 145; RV64-NEXT: [[TMP18:%.*]] = mul i64 -1, [[TMP17]]46; RV64-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP15]], i64 [[TMP25]]47; RV64-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP20]], i64 [[TMP18]]48; RV64-NEXT: [[VP_REVERSE1:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[TMP14]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP19]])49; RV64-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[VP_REVERSE1]], ptr align 4 [[TMP21]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP19]])50; RV64-NEXT: [[TMP22:%.*]] = zext i32 [[TMP19]] to i6451; RV64-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP22]], [[INDEX]]52; RV64-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP22]]53; RV64-NEXT: [[TMP23:%.*]] = icmp eq i64 [[AVL_NEXT]], 054; RV64-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]55; RV64: [[MIDDLE_BLOCK]]:56; RV64-NEXT: br label %[[EXIT:.*]]57; RV64: [[EXIT]]:58; RV64-NEXT: ret void59;60; RV32-LABEL: define void @vector_reverse_i32(61; RV32-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0:[0-9]+]] {62; RV32-NEXT: [[ENTRY:.*:]]63; RV32-NEXT: br label %[[VECTOR_PH:.*]]64; RV32: [[VECTOR_PH]]:65; RV32-NEXT: br label %[[VECTOR_BODY:.*]]66; RV32: [[VECTOR_BODY]]:67; RV32-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]68; RV32-NEXT: [[AVL:%.*]] = phi i64 [ 1023, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]69; RV32-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)70; RV32-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]71; RV32-NEXT: [[TMP7:%.*]] = add nsw i64 [[OFFSET_IDX]], -172; RV32-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP7]]73; RV32-NEXT: [[TMP10:%.*]] = mul i32 0, [[TMP9]]74; RV32-NEXT: [[TMP11:%.*]] = sub i32 [[TMP9]], 175; RV32-NEXT: [[TMP12:%.*]] = mul i32 -1, [[TMP11]]76; RV32-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP8]], i32 [[TMP10]]77; RV32-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP13]], i32 [[TMP12]]78; RV32-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP14]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])79; RV32-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])80; RV32-NEXT: [[TMP15:%.*]] = add <vscale x 4 x i32> [[REVERSE]], splat (i32 1)81; RV32-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP7]]82; RV32-NEXT: [[TMP17:%.*]] = mul i32 0, [[TMP9]]83; RV32-NEXT: [[TMP19:%.*]] = sub i32 [[TMP9]], 184; RV32-NEXT: [[TMP20:%.*]] = mul i32 -1, [[TMP19]]85; RV32-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[TMP16]], i32 [[TMP17]]86; RV32-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP18]], i32 [[TMP20]]87; RV32-NEXT: [[VP_REVERSE1:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[TMP15]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])88; RV32-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[VP_REVERSE1]], ptr align 4 [[TMP22]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])89; RV32-NEXT: [[TMP23:%.*]] = zext i32 [[TMP9]] to i6490; RV32-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP23]], [[INDEX]]91; RV32-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP23]]92; RV32-NEXT: [[TMP21:%.*]] = icmp eq i64 [[AVL_NEXT]], 093; RV32-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]94; RV32: [[MIDDLE_BLOCK]]:95; RV32-NEXT: br label %[[EXIT:.*]]96; RV32: [[EXIT]]:97; RV32-NEXT: ret void98;99; RV64-UF2-LABEL: define void @vector_reverse_i32(100; RV64-UF2-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0:[0-9]+]] {101; RV64-UF2-NEXT: [[ENTRY:.*]]:102; RV64-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()103; RV64-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3104; RV64-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1023, [[TMP1]]105; RV64-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]106; RV64-UF2: [[VECTOR_PH]]:107; RV64-UF2-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()108; RV64-UF2-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4109; RV64-UF2-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 2110; RV64-UF2-NEXT: [[N_VEC:%.*]] = urem i64 1023, [[TMP6]]111; RV64-UF2-NEXT: [[TMP7:%.*]] = sub i64 1023, [[N_VEC]]112; RV64-UF2-NEXT: [[TMP33:%.*]] = sub i64 1023, [[TMP7]]113; RV64-UF2-NEXT: br label %[[VECTOR_BODY:.*]]114; RV64-UF2: [[VECTOR_BODY]]:115; RV64-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]116; RV64-UF2-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]117; RV64-UF2-NEXT: [[TMP8:%.*]] = add nsw i64 [[OFFSET_IDX]], -1118; RV64-UF2-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP8]]119; RV64-UF2-NEXT: [[TMP10:%.*]] = mul i64 0, [[TMP5]]120; RV64-UF2-NEXT: [[TMP11:%.*]] = sub i64 [[TMP5]], 1121; RV64-UF2-NEXT: [[TMP12:%.*]] = mul i64 -1, [[TMP11]]122; RV64-UF2-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP9]], i64 [[TMP10]]123; RV64-UF2-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 [[TMP12]]124; RV64-UF2-NEXT: [[TMP15:%.*]] = mul i64 -1, [[TMP5]]125; RV64-UF2-NEXT: [[TMP16:%.*]] = sub i64 [[TMP5]], 1126; RV64-UF2-NEXT: [[TMP17:%.*]] = mul i64 -1, [[TMP16]]127; RV64-UF2-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[TMP9]], i64 [[TMP15]]128; RV64-UF2-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[TMP18]], i64 [[TMP17]]129; RV64-UF2-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP14]], align 4130; RV64-UF2-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]])131; RV64-UF2-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x i32>, ptr [[TMP19]], align 4132; RV64-UF2-NEXT: [[REVERSE2:%.*]] = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD1]])133; RV64-UF2-NEXT: [[TMP20:%.*]] = add <vscale x 4 x i32> [[REVERSE]], splat (i32 1)134; RV64-UF2-NEXT: [[TMP21:%.*]] = add <vscale x 4 x i32> [[REVERSE2]], splat (i32 1)135; RV64-UF2-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP8]]136; RV64-UF2-NEXT: [[TMP23:%.*]] = mul i64 0, [[TMP5]]137; RV64-UF2-NEXT: [[TMP24:%.*]] = sub i64 [[TMP5]], 1138; RV64-UF2-NEXT: [[TMP25:%.*]] = mul i64 -1, [[TMP24]]139; RV64-UF2-NEXT: [[TMP26:%.*]] = getelementptr inbounds i32, ptr [[TMP22]], i64 [[TMP23]]140; RV64-UF2-NEXT: [[TMP27:%.*]] = getelementptr inbounds i32, ptr [[TMP26]], i64 [[TMP25]]141; RV64-UF2-NEXT: [[TMP28:%.*]] = mul i64 -1, [[TMP5]]142; RV64-UF2-NEXT: [[TMP29:%.*]] = sub i64 [[TMP5]], 1143; RV64-UF2-NEXT: [[TMP30:%.*]] = mul i64 -1, [[TMP29]]144; RV64-UF2-NEXT: [[TMP31:%.*]] = getelementptr inbounds i32, ptr [[TMP22]], i64 [[TMP28]]145; RV64-UF2-NEXT: [[TMP32:%.*]] = getelementptr inbounds i32, ptr [[TMP31]], i64 [[TMP30]]146; RV64-UF2-NEXT: [[REVERSE3:%.*]] = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> [[TMP20]])147; RV64-UF2-NEXT: store <vscale x 4 x i32> [[REVERSE3]], ptr [[TMP27]], align 4148; RV64-UF2-NEXT: [[REVERSE4:%.*]] = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> [[TMP21]])149; RV64-UF2-NEXT: store <vscale x 4 x i32> [[REVERSE4]], ptr [[TMP32]], align 4150; RV64-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP6]]151; RV64-UF2-NEXT: [[TMP34:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[TMP7]]152; RV64-UF2-NEXT: br i1 [[TMP34]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]153; RV64-UF2: [[MIDDLE_BLOCK]]:154; RV64-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 1023, [[TMP7]]155; RV64-UF2-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]156; RV64-UF2: [[SCALAR_PH]]:157; RV64-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP33]], %[[MIDDLE_BLOCK]] ], [ 1023, %[[ENTRY]] ]158; RV64-UF2-NEXT: br label %[[FOR_BODY:.*]]159; RV64-UF2: [[FOR_BODY]]:160;161entry:162 br label %for.body163 164for.body:165 %dec.iv = phi i64 [ 1023, %entry ], [ %iv.next, %for.body ]166 %iv.next = add nsw i64 %dec.iv, -1167 %arrayidx.b = getelementptr inbounds i32, ptr %B, i64 %iv.next168 %0 = load i32, ptr %arrayidx.b, align 4169 %add = add i32 %0, 1170 %arrayidx.a = getelementptr inbounds i32, ptr %A, i64 %iv.next171 store i32 %add, ptr %arrayidx.a, align 4172 %cmp = icmp ugt i64 %dec.iv, 1173 br i1 %cmp, label %for.body, label %exit, !llvm.loop !0174 175exit:176 ret void177}178 179define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocapture noundef readonly %B, i32 noundef signext %n) {180; RV64-LABEL: define void @vector_reverse_i64(181; RV64-SAME: ptr noundef writeonly captures(none) [[A:%.*]], ptr noundef readonly captures(none) [[B:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] {182; RV64-NEXT: [[ENTRY:.*:]]183; RV64-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64184; RV64-NEXT: [[B1:%.*]] = ptrtoint ptr [[B]] to i64185; RV64-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[N]], 0186; RV64-NEXT: br i1 [[CMP7]], label %[[FOR_BODY_PREHEADER:.*]], label %[[FOR_COND_CLEANUP:.*]]187; RV64: [[FOR_BODY_PREHEADER]]:188; RV64-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64189; RV64-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]190; RV64: [[VECTOR_SCEVCHECK]]:191; RV64-NEXT: [[TMP3:%.*]] = add nsw i64 [[TMP0]], -1192; RV64-NEXT: [[TMP4:%.*]] = add i32 [[N]], -1193; RV64-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP3]] to i32194; RV64-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[TMP5]]195; RV64-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], [[TMP4]]196; RV64-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP3]], 4294967295197; RV64-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP9]]198; RV64-NEXT: br i1 [[TMP8]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]199; RV64: [[VECTOR_MEMCHECK]]:200; RV64-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()201; RV64-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 4202; RV64-NEXT: [[TMP13:%.*]] = mul i64 [[TMP12]], 4203; RV64-NEXT: [[TMP14:%.*]] = sub i64 [[B1]], [[A2]]204; RV64-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP14]], [[TMP13]]205; RV64-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]206; RV64: [[VECTOR_PH]]:207; RV64-NEXT: br label %[[VECTOR_BODY:.*]]208; RV64: [[VECTOR_BODY]]:209; RV64-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]210; RV64-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP0]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]211; RV64-NEXT: [[TMP20:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)212; RV64-NEXT: [[DOTCAST3:%.*]] = trunc i64 [[INDEX]] to i32213; RV64-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[N]], [[DOTCAST3]]214; RV64-NEXT: [[TMP21:%.*]] = add nsw i32 [[OFFSET_IDX]], -1215; RV64-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64216; RV64-NEXT: [[TMP23:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP22]]217; RV64-NEXT: [[TMP24:%.*]] = zext i32 [[TMP20]] to i64218; RV64-NEXT: [[TMP28:%.*]] = mul i64 0, [[TMP24]]219; RV64-NEXT: [[TMP25:%.*]] = sub i64 [[TMP24]], 1220; RV64-NEXT: [[TMP26:%.*]] = mul i64 -1, [[TMP25]]221; RV64-NEXT: [[TMP38:%.*]] = getelementptr i32, ptr [[TMP23]], i64 [[TMP28]]222; RV64-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[TMP38]], i64 [[TMP26]]223; RV64-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP27]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP20]])224; RV64-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP20]])225; RV64-NEXT: [[TMP29:%.*]] = add <vscale x 4 x i32> [[REVERSE]], splat (i32 1)226; RV64-NEXT: [[TMP30:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP22]]227; RV64-NEXT: [[TMP39:%.*]] = zext i32 [[TMP20]] to i64228; RV64-NEXT: [[TMP31:%.*]] = mul i64 0, [[TMP39]]229; RV64-NEXT: [[TMP32:%.*]] = sub i64 [[TMP39]], 1230; RV64-NEXT: [[TMP33:%.*]] = mul i64 -1, [[TMP32]]231; RV64-NEXT: [[TMP34:%.*]] = getelementptr i32, ptr [[TMP30]], i64 [[TMP31]]232; RV64-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr [[TMP34]], i64 [[TMP33]]233; RV64-NEXT: [[VP_REVERSE3:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[TMP29]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP20]])234; RV64-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[VP_REVERSE3]], ptr align 4 [[TMP35]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP20]])235; RV64-NEXT: [[TMP36:%.*]] = zext i32 [[TMP20]] to i64236; RV64-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP36]], [[INDEX]]237; RV64-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP36]]238; RV64-NEXT: [[TMP37:%.*]] = icmp eq i64 [[AVL_NEXT]], 0239; RV64-NEXT: br i1 [[TMP37]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]240; RV64: [[MIDDLE_BLOCK]]:241; RV64-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]]242; RV64: [[SCALAR_PH]]:243; RV64-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP0]], %[[VECTOR_SCEVCHECK]] ], [ [[TMP0]], %[[VECTOR_MEMCHECK]] ]244; RV64-NEXT: [[BC_RESUME_VAL4:%.*]] = phi i32 [ [[N]], %[[VECTOR_SCEVCHECK]] ], [ [[N]], %[[VECTOR_MEMCHECK]] ]245; RV64-NEXT: br label %[[FOR_BODY:.*]]246; RV64: [[FOR_COND_CLEANUP_LOOPEXIT]]:247; RV64-NEXT: br label %[[FOR_COND_CLEANUP]]248; RV64: [[FOR_COND_CLEANUP]]:249; RV64-NEXT: ret void250; RV64: [[FOR_BODY]]:251;252; RV32-LABEL: define void @vector_reverse_i64(253; RV32-SAME: ptr noundef writeonly captures(none) [[A:%.*]], ptr noundef readonly captures(none) [[B:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] {254; RV32-NEXT: [[ENTRY:.*:]]255; RV32-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i32256; RV32-NEXT: [[B1:%.*]] = ptrtoint ptr [[B]] to i32257; RV32-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[N]], 0258; RV32-NEXT: br i1 [[CMP7]], label %[[FOR_BODY_PREHEADER:.*]], label %[[FOR_COND_CLEANUP:.*]]259; RV32: [[FOR_BODY_PREHEADER]]:260; RV32-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64261; RV32-NEXT: br label %[[VECTOR_MEMCHECK:.*]]262; RV32: [[VECTOR_MEMCHECK]]:263; RV32-NEXT: [[TMP3:%.*]] = call i32 @llvm.vscale.i32()264; RV32-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP3]], 4265; RV32-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], 4266; RV32-NEXT: [[TMP6:%.*]] = sub i32 [[B1]], [[A2]]267; RV32-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i32 [[TMP6]], [[TMP5]]268; RV32-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]269; RV32: [[VECTOR_PH]]:270; RV32-NEXT: br label %[[VECTOR_BODY:.*]]271; RV32: [[VECTOR_BODY]]:272; RV32-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]273; RV32-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP0]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]274; RV32-NEXT: [[TMP16:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)275; RV32-NEXT: [[DOTCAST3:%.*]] = trunc i64 [[INDEX]] to i32276; RV32-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[N]], [[DOTCAST3]]277; RV32-NEXT: [[TMP13:%.*]] = add nsw i32 [[OFFSET_IDX]], -1278; RV32-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64279; RV32-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP14]]280; RV32-NEXT: [[TMP17:%.*]] = mul i32 0, [[TMP16]]281; RV32-NEXT: [[TMP18:%.*]] = sub i32 [[TMP16]], 1282; RV32-NEXT: [[TMP19:%.*]] = mul i32 -1, [[TMP18]]283; RV32-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP15]], i32 [[TMP17]]284; RV32-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP20]], i32 [[TMP19]]285; RV32-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP28]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])286; RV32-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])287; RV32-NEXT: [[TMP22:%.*]] = add <vscale x 4 x i32> [[REVERSE]], splat (i32 1)288; RV32-NEXT: [[TMP23:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP14]]289; RV32-NEXT: [[TMP21:%.*]] = mul i32 0, [[TMP16]]290; RV32-NEXT: [[TMP26:%.*]] = sub i32 [[TMP16]], 1291; RV32-NEXT: [[TMP27:%.*]] = mul i32 -1, [[TMP26]]292; RV32-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP23]], i32 [[TMP21]]293; RV32-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP24]], i32 [[TMP27]]294; RV32-NEXT: [[VP_REVERSE3:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[TMP22]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])295; RV32-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[VP_REVERSE3]], ptr align 4 [[TMP25]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])296; RV32-NEXT: [[TMP29:%.*]] = zext i32 [[TMP16]] to i64297; RV32-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP29]], [[INDEX]]298; RV32-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP29]]299; RV32-NEXT: [[TMP30:%.*]] = icmp eq i64 [[AVL_NEXT]], 0300; RV32-NEXT: br i1 [[TMP30]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]301; RV32: [[MIDDLE_BLOCK]]:302; RV32-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]]303; RV32: [[SCALAR_PH]]:304; RV32-NEXT: br label %[[FOR_BODY:.*]]305; RV32: [[FOR_COND_CLEANUP_LOOPEXIT]]:306; RV32-NEXT: br label %[[FOR_COND_CLEANUP]]307; RV32: [[FOR_COND_CLEANUP]]:308; RV32-NEXT: ret void309; RV32: [[FOR_BODY]]:310;311; RV64-UF2-LABEL: define void @vector_reverse_i64(312; RV64-UF2-SAME: ptr noundef writeonly captures(none) [[A:%.*]], ptr noundef readonly captures(none) [[B:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] {313; RV64-UF2-NEXT: [[ENTRY:.*:]]314; RV64-UF2-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64315; RV64-UF2-NEXT: [[B1:%.*]] = ptrtoint ptr [[B]] to i64316; RV64-UF2-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[N]], 0317; RV64-UF2-NEXT: br i1 [[CMP7]], label %[[FOR_BODY_PREHEADER:.*]], label %[[FOR_COND_CLEANUP:.*]]318; RV64-UF2: [[FOR_BODY_PREHEADER]]:319; RV64-UF2-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64320; RV64-UF2-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()321; RV64-UF2-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 3322; RV64-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]]323; RV64-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]324; RV64-UF2: [[VECTOR_SCEVCHECK]]:325; RV64-UF2-NEXT: [[TMP3:%.*]] = add nsw i64 [[TMP0]], -1326; RV64-UF2-NEXT: [[TMP4:%.*]] = add i32 [[N]], -1327; RV64-UF2-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP3]] to i32328; RV64-UF2-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[TMP5]]329; RV64-UF2-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], [[TMP4]]330; RV64-UF2-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP3]], 4294967295331; RV64-UF2-NEXT: [[TMP10:%.*]] = or i1 [[TMP7]], [[TMP9]]332; RV64-UF2-NEXT: br i1 [[TMP10]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]]333; RV64-UF2: [[VECTOR_MEMCHECK]]:334; RV64-UF2-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()335; RV64-UF2-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 4336; RV64-UF2-NEXT: [[TMP13:%.*]] = mul i64 [[TMP12]], 8337; RV64-UF2-NEXT: [[TMP14:%.*]] = sub i64 [[B1]], [[A2]]338; RV64-UF2-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP14]], [[TMP13]]339; RV64-UF2-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]340; RV64-UF2: [[VECTOR_PH]]:341; RV64-UF2-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()342; RV64-UF2-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 4343; RV64-UF2-NEXT: [[TMP19:%.*]] = mul i64 [[TMP18]], 2344; RV64-UF2-NEXT: [[N_VEC:%.*]] = urem i64 [[TMP0]], [[TMP19]]345; RV64-UF2-NEXT: [[TMP20:%.*]] = sub i64 [[TMP0]], [[N_VEC]]346; RV64-UF2-NEXT: [[TMP48:%.*]] = sub i64 [[TMP0]], [[TMP20]]347; RV64-UF2-NEXT: [[DOTCAST:%.*]] = trunc i64 [[TMP20]] to i32348; RV64-UF2-NEXT: [[TMP21:%.*]] = sub i32 [[N]], [[DOTCAST]]349; RV64-UF2-NEXT: br label %[[VECTOR_BODY:.*]]350; RV64-UF2: [[VECTOR_BODY]]:351; RV64-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]352; RV64-UF2-NEXT: [[DOTCAST3:%.*]] = trunc i64 [[INDEX]] to i32353; RV64-UF2-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[N]], [[DOTCAST3]]354; RV64-UF2-NEXT: [[TMP22:%.*]] = add nsw i32 [[OFFSET_IDX]], -1355; RV64-UF2-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64356; RV64-UF2-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP23]]357; RV64-UF2-NEXT: [[TMP25:%.*]] = mul i64 0, [[TMP18]]358; RV64-UF2-NEXT: [[TMP26:%.*]] = sub i64 [[TMP18]], 1359; RV64-UF2-NEXT: [[TMP27:%.*]] = mul i64 -1, [[TMP26]]360; RV64-UF2-NEXT: [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[TMP24]], i64 [[TMP25]]361; RV64-UF2-NEXT: [[TMP29:%.*]] = getelementptr inbounds i32, ptr [[TMP28]], i64 [[TMP27]]362; RV64-UF2-NEXT: [[TMP30:%.*]] = mul i64 -1, [[TMP18]]363; RV64-UF2-NEXT: [[TMP31:%.*]] = sub i64 [[TMP18]], 1364; RV64-UF2-NEXT: [[TMP32:%.*]] = mul i64 -1, [[TMP31]]365; RV64-UF2-NEXT: [[TMP33:%.*]] = getelementptr inbounds i32, ptr [[TMP24]], i64 [[TMP30]]366; RV64-UF2-NEXT: [[TMP34:%.*]] = getelementptr inbounds i32, ptr [[TMP33]], i64 [[TMP32]]367; RV64-UF2-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP29]], align 4368; RV64-UF2-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]])369; RV64-UF2-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 4 x i32>, ptr [[TMP34]], align 4370; RV64-UF2-NEXT: [[REVERSE5:%.*]] = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD4]])371; RV64-UF2-NEXT: [[TMP35:%.*]] = add <vscale x 4 x i32> [[REVERSE]], splat (i32 1)372; RV64-UF2-NEXT: [[TMP36:%.*]] = add <vscale x 4 x i32> [[REVERSE5]], splat (i32 1)373; RV64-UF2-NEXT: [[TMP37:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP23]]374; RV64-UF2-NEXT: [[TMP38:%.*]] = mul i64 0, [[TMP18]]375; RV64-UF2-NEXT: [[TMP39:%.*]] = sub i64 [[TMP18]], 1376; RV64-UF2-NEXT: [[TMP40:%.*]] = mul i64 -1, [[TMP39]]377; RV64-UF2-NEXT: [[TMP41:%.*]] = getelementptr inbounds i32, ptr [[TMP37]], i64 [[TMP38]]378; RV64-UF2-NEXT: [[TMP42:%.*]] = getelementptr inbounds i32, ptr [[TMP41]], i64 [[TMP40]]379; RV64-UF2-NEXT: [[TMP43:%.*]] = mul i64 -1, [[TMP18]]380; RV64-UF2-NEXT: [[TMP44:%.*]] = sub i64 [[TMP18]], 1381; RV64-UF2-NEXT: [[TMP45:%.*]] = mul i64 -1, [[TMP44]]382; RV64-UF2-NEXT: [[TMP46:%.*]] = getelementptr inbounds i32, ptr [[TMP37]], i64 [[TMP43]]383; RV64-UF2-NEXT: [[TMP47:%.*]] = getelementptr inbounds i32, ptr [[TMP46]], i64 [[TMP45]]384; RV64-UF2-NEXT: [[REVERSE6:%.*]] = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> [[TMP35]])385; RV64-UF2-NEXT: store <vscale x 4 x i32> [[REVERSE6]], ptr [[TMP42]], align 4386; RV64-UF2-NEXT: [[REVERSE7:%.*]] = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> [[TMP36]])387; RV64-UF2-NEXT: store <vscale x 4 x i32> [[REVERSE7]], ptr [[TMP47]], align 4388; RV64-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP19]]389; RV64-UF2-NEXT: [[TMP49:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[TMP20]]390; RV64-UF2-NEXT: br i1 [[TMP49]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]391; RV64-UF2: [[MIDDLE_BLOCK]]:392; RV64-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[TMP20]]393; RV64-UF2-NEXT: br i1 [[CMP_N]], label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]], label %[[SCALAR_PH]]394; RV64-UF2: [[SCALAR_PH]]:395; RV64-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP48]], %[[MIDDLE_BLOCK]] ], [ [[TMP0]], %[[FOR_BODY_PREHEADER]] ], [ [[TMP0]], %[[VECTOR_SCEVCHECK]] ], [ [[TMP0]], %[[VECTOR_MEMCHECK]] ]396; RV64-UF2-NEXT: [[BC_RESUME_VAL8:%.*]] = phi i32 [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ [[N]], %[[FOR_BODY_PREHEADER]] ], [ [[N]], %[[VECTOR_SCEVCHECK]] ], [ [[N]], %[[VECTOR_MEMCHECK]] ]397; RV64-UF2-NEXT: br label %[[FOR_BODY:.*]]398; RV64-UF2: [[FOR_COND_CLEANUP_LOOPEXIT]]:399; RV64-UF2-NEXT: br label %[[FOR_COND_CLEANUP]]400; RV64-UF2: [[FOR_COND_CLEANUP]]:401; RV64-UF2-NEXT: ret void402; RV64-UF2: [[FOR_BODY]]:403;404entry:405 %cmp7 = icmp sgt i32 %n, 0406 br i1 %cmp7, label %for.body.preheader, label %for.cond.cleanup407 408for.body.preheader: ; preds = %entry409 %0 = zext i32 %n to i64410 br label %for.body411 412for.cond.cleanup: ; preds = %for.body, %entry413 ret void414 415for.body: ; preds = %for.body.preheader, %for.body416 %indvars.iv = phi i64 [ %0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]417 %i.0.in8 = phi i32 [ %n, %for.body.preheader ], [ %i.0, %for.body ]418 %i.0 = add nsw i32 %i.0.in8, -1419 %idxprom = zext i32 %i.0 to i64420 %arrayidx = getelementptr inbounds i32, ptr %B, i64 %idxprom421 %1 = load i32, ptr %arrayidx, align 4422 %add9 = add i32 %1, 1423 %arrayidx3 = getelementptr inbounds i32, ptr %A, i64 %idxprom424 store i32 %add9, ptr %arrayidx3, align 4425 %cmp = icmp ugt i64 %indvars.iv, 1426 %indvars.iv.next = add nsw i64 %indvars.iv, -1427 br i1 %cmp, label %for.body, label %for.cond.cleanup, !llvm.loop !0428}429 430define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocapture noundef readonly %B, i32 noundef signext %n) {431; RV64-LABEL: define void @vector_reverse_f32(432; RV64-SAME: ptr noundef writeonly captures(none) [[A:%.*]], ptr noundef readonly captures(none) [[B:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] {433; RV64-NEXT: [[ENTRY:.*:]]434; RV64-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64435; RV64-NEXT: [[B1:%.*]] = ptrtoint ptr [[B]] to i64436; RV64-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[N]], 0437; RV64-NEXT: br i1 [[CMP7]], label %[[FOR_BODY_PREHEADER:.*]], label %[[FOR_COND_CLEANUP:.*]]438; RV64: [[FOR_BODY_PREHEADER]]:439; RV64-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64440; RV64-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]441; RV64: [[VECTOR_SCEVCHECK]]:442; RV64-NEXT: [[TMP3:%.*]] = add nsw i64 [[TMP0]], -1443; RV64-NEXT: [[TMP4:%.*]] = add i32 [[N]], -1444; RV64-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP3]] to i32445; RV64-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[TMP5]]446; RV64-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], [[TMP4]]447; RV64-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP3]], 4294967295448; RV64-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP9]]449; RV64-NEXT: br i1 [[TMP8]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]450; RV64: [[VECTOR_MEMCHECK]]:451; RV64-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()452; RV64-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 4453; RV64-NEXT: [[TMP13:%.*]] = mul i64 [[TMP12]], 4454; RV64-NEXT: [[TMP14:%.*]] = sub i64 [[B1]], [[A2]]455; RV64-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP14]], [[TMP13]]456; RV64-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]457; RV64: [[VECTOR_PH]]:458; RV64-NEXT: br label %[[VECTOR_BODY:.*]]459; RV64: [[VECTOR_BODY]]:460; RV64-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]461; RV64-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP0]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]462; RV64-NEXT: [[TMP20:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)463; RV64-NEXT: [[DOTCAST3:%.*]] = trunc i64 [[INDEX]] to i32464; RV64-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[N]], [[DOTCAST3]]465; RV64-NEXT: [[TMP21:%.*]] = add nsw i32 [[OFFSET_IDX]], -1466; RV64-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64467; RV64-NEXT: [[TMP23:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP22]]468; RV64-NEXT: [[TMP24:%.*]] = zext i32 [[TMP20]] to i64469; RV64-NEXT: [[TMP28:%.*]] = mul i64 0, [[TMP24]]470; RV64-NEXT: [[TMP25:%.*]] = sub i64 [[TMP24]], 1471; RV64-NEXT: [[TMP26:%.*]] = mul i64 -1, [[TMP25]]472; RV64-NEXT: [[TMP38:%.*]] = getelementptr float, ptr [[TMP23]], i64 [[TMP28]]473; RV64-NEXT: [[TMP27:%.*]] = getelementptr float, ptr [[TMP38]], i64 [[TMP26]]474; RV64-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP27]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP20]])475; RV64-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vp.reverse.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP20]])476; RV64-NEXT: [[TMP29:%.*]] = fadd <vscale x 4 x float> [[REVERSE]], splat (float 1.000000e+00)477; RV64-NEXT: [[TMP30:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP22]]478; RV64-NEXT: [[TMP39:%.*]] = zext i32 [[TMP20]] to i64479; RV64-NEXT: [[TMP31:%.*]] = mul i64 0, [[TMP39]]480; RV64-NEXT: [[TMP32:%.*]] = sub i64 [[TMP39]], 1481; RV64-NEXT: [[TMP33:%.*]] = mul i64 -1, [[TMP32]]482; RV64-NEXT: [[TMP34:%.*]] = getelementptr float, ptr [[TMP30]], i64 [[TMP31]]483; RV64-NEXT: [[TMP35:%.*]] = getelementptr float, ptr [[TMP34]], i64 [[TMP33]]484; RV64-NEXT: [[VP_REVERSE3:%.*]] = call <vscale x 4 x float> @llvm.experimental.vp.reverse.nxv4f32(<vscale x 4 x float> [[TMP29]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP20]])485; RV64-NEXT: call void @llvm.vp.store.nxv4f32.p0(<vscale x 4 x float> [[VP_REVERSE3]], ptr align 4 [[TMP35]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP20]])486; RV64-NEXT: [[TMP36:%.*]] = zext i32 [[TMP20]] to i64487; RV64-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP36]], [[INDEX]]488; RV64-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP36]]489; RV64-NEXT: [[TMP37:%.*]] = icmp eq i64 [[AVL_NEXT]], 0490; RV64-NEXT: br i1 [[TMP37]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]491; RV64: [[MIDDLE_BLOCK]]:492; RV64-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]]493; RV64: [[SCALAR_PH]]:494; RV64-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP0]], %[[VECTOR_SCEVCHECK]] ], [ [[TMP0]], %[[VECTOR_MEMCHECK]] ]495; RV64-NEXT: [[BC_RESUME_VAL4:%.*]] = phi i32 [ [[N]], %[[VECTOR_SCEVCHECK]] ], [ [[N]], %[[VECTOR_MEMCHECK]] ]496; RV64-NEXT: br label %[[FOR_BODY:.*]]497; RV64: [[FOR_COND_CLEANUP_LOOPEXIT]]:498; RV64-NEXT: br label %[[FOR_COND_CLEANUP]]499; RV64: [[FOR_COND_CLEANUP]]:500; RV64-NEXT: ret void501; RV64: [[FOR_BODY]]:502;503; RV32-LABEL: define void @vector_reverse_f32(504; RV32-SAME: ptr noundef writeonly captures(none) [[A:%.*]], ptr noundef readonly captures(none) [[B:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] {505; RV32-NEXT: [[ENTRY:.*:]]506; RV32-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i32507; RV32-NEXT: [[B1:%.*]] = ptrtoint ptr [[B]] to i32508; RV32-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[N]], 0509; RV32-NEXT: br i1 [[CMP7]], label %[[FOR_BODY_PREHEADER:.*]], label %[[FOR_COND_CLEANUP:.*]]510; RV32: [[FOR_BODY_PREHEADER]]:511; RV32-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64512; RV32-NEXT: br label %[[VECTOR_MEMCHECK:.*]]513; RV32: [[VECTOR_MEMCHECK]]:514; RV32-NEXT: [[TMP3:%.*]] = call i32 @llvm.vscale.i32()515; RV32-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP3]], 4516; RV32-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], 4517; RV32-NEXT: [[TMP6:%.*]] = sub i32 [[B1]], [[A2]]518; RV32-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i32 [[TMP6]], [[TMP5]]519; RV32-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]520; RV32: [[VECTOR_PH]]:521; RV32-NEXT: br label %[[VECTOR_BODY:.*]]522; RV32: [[VECTOR_BODY]]:523; RV32-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]524; RV32-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP0]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]525; RV32-NEXT: [[TMP16:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)526; RV32-NEXT: [[DOTCAST3:%.*]] = trunc i64 [[INDEX]] to i32527; RV32-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[N]], [[DOTCAST3]]528; RV32-NEXT: [[TMP13:%.*]] = add nsw i32 [[OFFSET_IDX]], -1529; RV32-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64530; RV32-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP14]]531; RV32-NEXT: [[TMP17:%.*]] = mul i32 0, [[TMP16]]532; RV32-NEXT: [[TMP18:%.*]] = sub i32 [[TMP16]], 1533; RV32-NEXT: [[TMP19:%.*]] = mul i32 -1, [[TMP18]]534; RV32-NEXT: [[TMP20:%.*]] = getelementptr float, ptr [[TMP15]], i32 [[TMP17]]535; RV32-NEXT: [[TMP28:%.*]] = getelementptr float, ptr [[TMP20]], i32 [[TMP19]]536; RV32-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP28]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])537; RV32-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vp.reverse.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])538; RV32-NEXT: [[TMP22:%.*]] = fadd <vscale x 4 x float> [[REVERSE]], splat (float 1.000000e+00)539; RV32-NEXT: [[TMP23:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP14]]540; RV32-NEXT: [[TMP21:%.*]] = mul i32 0, [[TMP16]]541; RV32-NEXT: [[TMP26:%.*]] = sub i32 [[TMP16]], 1542; RV32-NEXT: [[TMP27:%.*]] = mul i32 -1, [[TMP26]]543; RV32-NEXT: [[TMP24:%.*]] = getelementptr float, ptr [[TMP23]], i32 [[TMP21]]544; RV32-NEXT: [[TMP25:%.*]] = getelementptr float, ptr [[TMP24]], i32 [[TMP27]]545; RV32-NEXT: [[VP_REVERSE3:%.*]] = call <vscale x 4 x float> @llvm.experimental.vp.reverse.nxv4f32(<vscale x 4 x float> [[TMP22]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])546; RV32-NEXT: call void @llvm.vp.store.nxv4f32.p0(<vscale x 4 x float> [[VP_REVERSE3]], ptr align 4 [[TMP25]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])547; RV32-NEXT: [[TMP29:%.*]] = zext i32 [[TMP16]] to i64548; RV32-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP29]], [[INDEX]]549; RV32-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP29]]550; RV32-NEXT: [[TMP30:%.*]] = icmp eq i64 [[AVL_NEXT]], 0551; RV32-NEXT: br i1 [[TMP30]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]552; RV32: [[MIDDLE_BLOCK]]:553; RV32-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]]554; RV32: [[SCALAR_PH]]:555; RV32-NEXT: br label %[[FOR_BODY:.*]]556; RV32: [[FOR_COND_CLEANUP_LOOPEXIT]]:557; RV32-NEXT: br label %[[FOR_COND_CLEANUP]]558; RV32: [[FOR_COND_CLEANUP]]:559; RV32-NEXT: ret void560; RV32: [[FOR_BODY]]:561;562; RV64-UF2-LABEL: define void @vector_reverse_f32(563; RV64-UF2-SAME: ptr noundef writeonly captures(none) [[A:%.*]], ptr noundef readonly captures(none) [[B:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] {564; RV64-UF2-NEXT: [[ENTRY:.*:]]565; RV64-UF2-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64566; RV64-UF2-NEXT: [[B1:%.*]] = ptrtoint ptr [[B]] to i64567; RV64-UF2-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[N]], 0568; RV64-UF2-NEXT: br i1 [[CMP7]], label %[[FOR_BODY_PREHEADER:.*]], label %[[FOR_COND_CLEANUP:.*]]569; RV64-UF2: [[FOR_BODY_PREHEADER]]:570; RV64-UF2-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64571; RV64-UF2-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()572; RV64-UF2-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 3573; RV64-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]]574; RV64-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]575; RV64-UF2: [[VECTOR_SCEVCHECK]]:576; RV64-UF2-NEXT: [[TMP3:%.*]] = add nsw i64 [[TMP0]], -1577; RV64-UF2-NEXT: [[TMP4:%.*]] = add i32 [[N]], -1578; RV64-UF2-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP3]] to i32579; RV64-UF2-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[TMP5]]580; RV64-UF2-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], [[TMP4]]581; RV64-UF2-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP3]], 4294967295582; RV64-UF2-NEXT: [[TMP10:%.*]] = or i1 [[TMP7]], [[TMP9]]583; RV64-UF2-NEXT: br i1 [[TMP10]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]]584; RV64-UF2: [[VECTOR_MEMCHECK]]:585; RV64-UF2-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()586; RV64-UF2-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 4587; RV64-UF2-NEXT: [[TMP13:%.*]] = mul i64 [[TMP12]], 8588; RV64-UF2-NEXT: [[TMP14:%.*]] = sub i64 [[B1]], [[A2]]589; RV64-UF2-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP14]], [[TMP13]]590; RV64-UF2-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]591; RV64-UF2: [[VECTOR_PH]]:592; RV64-UF2-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()593; RV64-UF2-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 4594; RV64-UF2-NEXT: [[TMP19:%.*]] = mul i64 [[TMP18]], 2595; RV64-UF2-NEXT: [[N_VEC:%.*]] = urem i64 [[TMP0]], [[TMP19]]596; RV64-UF2-NEXT: [[TMP20:%.*]] = sub i64 [[TMP0]], [[N_VEC]]597; RV64-UF2-NEXT: [[TMP48:%.*]] = sub i64 [[TMP0]], [[TMP20]]598; RV64-UF2-NEXT: [[DOTCAST:%.*]] = trunc i64 [[TMP20]] to i32599; RV64-UF2-NEXT: [[TMP21:%.*]] = sub i32 [[N]], [[DOTCAST]]600; RV64-UF2-NEXT: br label %[[VECTOR_BODY:.*]]601; RV64-UF2: [[VECTOR_BODY]]:602; RV64-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]603; RV64-UF2-NEXT: [[DOTCAST3:%.*]] = trunc i64 [[INDEX]] to i32604; RV64-UF2-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[N]], [[DOTCAST3]]605; RV64-UF2-NEXT: [[TMP22:%.*]] = add nsw i32 [[OFFSET_IDX]], -1606; RV64-UF2-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64607; RV64-UF2-NEXT: [[TMP24:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP23]]608; RV64-UF2-NEXT: [[TMP25:%.*]] = mul i64 0, [[TMP18]]609; RV64-UF2-NEXT: [[TMP26:%.*]] = sub i64 [[TMP18]], 1610; RV64-UF2-NEXT: [[TMP27:%.*]] = mul i64 -1, [[TMP26]]611; RV64-UF2-NEXT: [[TMP28:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[TMP25]]612; RV64-UF2-NEXT: [[TMP29:%.*]] = getelementptr inbounds float, ptr [[TMP28]], i64 [[TMP27]]613; RV64-UF2-NEXT: [[TMP30:%.*]] = mul i64 -1, [[TMP18]]614; RV64-UF2-NEXT: [[TMP31:%.*]] = sub i64 [[TMP18]], 1615; RV64-UF2-NEXT: [[TMP32:%.*]] = mul i64 -1, [[TMP31]]616; RV64-UF2-NEXT: [[TMP33:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[TMP30]]617; RV64-UF2-NEXT: [[TMP34:%.*]] = getelementptr inbounds float, ptr [[TMP33]], i64 [[TMP32]]618; RV64-UF2-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP29]], align 4619; RV64-UF2-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> [[WIDE_LOAD]])620; RV64-UF2-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 4 x float>, ptr [[TMP34]], align 4621; RV64-UF2-NEXT: [[REVERSE5:%.*]] = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> [[WIDE_LOAD4]])622; RV64-UF2-NEXT: [[TMP35:%.*]] = fadd <vscale x 4 x float> [[REVERSE]], splat (float 1.000000e+00)623; RV64-UF2-NEXT: [[TMP36:%.*]] = fadd <vscale x 4 x float> [[REVERSE5]], splat (float 1.000000e+00)624; RV64-UF2-NEXT: [[TMP37:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP23]]625; RV64-UF2-NEXT: [[TMP38:%.*]] = mul i64 0, [[TMP18]]626; RV64-UF2-NEXT: [[TMP39:%.*]] = sub i64 [[TMP18]], 1627; RV64-UF2-NEXT: [[TMP40:%.*]] = mul i64 -1, [[TMP39]]628; RV64-UF2-NEXT: [[TMP41:%.*]] = getelementptr inbounds float, ptr [[TMP37]], i64 [[TMP38]]629; RV64-UF2-NEXT: [[TMP42:%.*]] = getelementptr inbounds float, ptr [[TMP41]], i64 [[TMP40]]630; RV64-UF2-NEXT: [[TMP43:%.*]] = mul i64 -1, [[TMP18]]631; RV64-UF2-NEXT: [[TMP44:%.*]] = sub i64 [[TMP18]], 1632; RV64-UF2-NEXT: [[TMP45:%.*]] = mul i64 -1, [[TMP44]]633; RV64-UF2-NEXT: [[TMP46:%.*]] = getelementptr inbounds float, ptr [[TMP37]], i64 [[TMP43]]634; RV64-UF2-NEXT: [[TMP47:%.*]] = getelementptr inbounds float, ptr [[TMP46]], i64 [[TMP45]]635; RV64-UF2-NEXT: [[REVERSE6:%.*]] = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> [[TMP35]])636; RV64-UF2-NEXT: store <vscale x 4 x float> [[REVERSE6]], ptr [[TMP42]], align 4637; RV64-UF2-NEXT: [[REVERSE7:%.*]] = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> [[TMP36]])638; RV64-UF2-NEXT: store <vscale x 4 x float> [[REVERSE7]], ptr [[TMP47]], align 4639; RV64-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP19]]640; RV64-UF2-NEXT: [[TMP49:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[TMP20]]641; RV64-UF2-NEXT: br i1 [[TMP49]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]642; RV64-UF2: [[MIDDLE_BLOCK]]:643; RV64-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[TMP20]]644; RV64-UF2-NEXT: br i1 [[CMP_N]], label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]], label %[[SCALAR_PH]]645; RV64-UF2: [[SCALAR_PH]]:646; RV64-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP48]], %[[MIDDLE_BLOCK]] ], [ [[TMP0]], %[[FOR_BODY_PREHEADER]] ], [ [[TMP0]], %[[VECTOR_SCEVCHECK]] ], [ [[TMP0]], %[[VECTOR_MEMCHECK]] ]647; RV64-UF2-NEXT: [[BC_RESUME_VAL8:%.*]] = phi i32 [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ [[N]], %[[FOR_BODY_PREHEADER]] ], [ [[N]], %[[VECTOR_SCEVCHECK]] ], [ [[N]], %[[VECTOR_MEMCHECK]] ]648; RV64-UF2-NEXT: br label %[[FOR_BODY:.*]]649; RV64-UF2: [[FOR_COND_CLEANUP_LOOPEXIT]]:650; RV64-UF2-NEXT: br label %[[FOR_COND_CLEANUP]]651; RV64-UF2: [[FOR_COND_CLEANUP]]:652; RV64-UF2-NEXT: ret void653; RV64-UF2: [[FOR_BODY]]:654;655entry:656 %cmp7 = icmp sgt i32 %n, 0657 br i1 %cmp7, label %for.body.preheader, label %for.cond.cleanup658 659for.body.preheader: ; preds = %entry660 %0 = zext i32 %n to i64661 br label %for.body662 663for.cond.cleanup: ; preds = %for.body, %entry664 ret void665 666for.body: ; preds = %for.body.preheader, %for.body667 %indvars.iv = phi i64 [ %0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]668 %i.0.in8 = phi i32 [ %n, %for.body.preheader ], [ %i.0, %for.body ]669 %i.0 = add nsw i32 %i.0.in8, -1670 %idxprom = zext i32 %i.0 to i64671 %arrayidx = getelementptr inbounds float, ptr %B, i64 %idxprom672 %1 = load float, ptr %arrayidx, align 4673 %conv1 = fadd float %1, 1.000000e+00674 %arrayidx3 = getelementptr inbounds float, ptr %A, i64 %idxprom675 store float %conv1, ptr %arrayidx3, align 4676 %cmp = icmp ugt i64 %indvars.iv, 1677 %indvars.iv.next = add nsw i64 %indvars.iv, -1678 br i1 %cmp, label %for.body, label %for.cond.cleanup, !llvm.loop !0679}680 681define void @vector_reverse_f32_simplify(ptr noalias %A, ptr noalias %B) {682; RV64-LABEL: define void @vector_reverse_f32_simplify(683; RV64-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0]] {684; RV64-NEXT: [[ENTRY:.*:]]685; RV64-NEXT: br label %[[VECTOR_PH:.*]]686; RV64: [[VECTOR_PH]]:687; RV64-NEXT: br label %[[VECTOR_BODY:.*]]688; RV64: [[VECTOR_BODY]]:689; RV64-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]690; RV64-NEXT: [[AVL:%.*]] = phi i64 [ 1023, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]691; RV64-NEXT: [[TMP19:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)692; RV64-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]693; RV64-NEXT: [[TMP7:%.*]] = add nsw i64 [[OFFSET_IDX]], -1694; RV64-NEXT: [[TMP8:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP7]]695; RV64-NEXT: [[TMP24:%.*]] = zext i32 [[TMP19]] to i64696; RV64-NEXT: [[TMP9:%.*]] = mul i64 0, [[TMP24]]697; RV64-NEXT: [[TMP10:%.*]] = sub i64 [[TMP24]], 1698; RV64-NEXT: [[TMP11:%.*]] = mul i64 -1, [[TMP10]]699; RV64-NEXT: [[TMP12:%.*]] = getelementptr float, ptr [[TMP8]], i64 [[TMP9]]700; RV64-NEXT: [[TMP13:%.*]] = getelementptr float, ptr [[TMP12]], i64 [[TMP11]]701; RV64-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP13]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP19]])702; RV64-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vp.reverse.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP19]])703; RV64-NEXT: [[TMP14:%.*]] = fadd <vscale x 4 x float> [[REVERSE]], splat (float 1.000000e+00)704; RV64-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP7]]705; RV64-NEXT: [[TMP16:%.*]] = zext i32 [[TMP19]] to i64706; RV64-NEXT: [[TMP25:%.*]] = mul i64 0, [[TMP16]]707; RV64-NEXT: [[TMP17:%.*]] = sub i64 [[TMP16]], 1708; RV64-NEXT: [[TMP18:%.*]] = mul i64 -1, [[TMP17]]709; RV64-NEXT: [[TMP20:%.*]] = getelementptr float, ptr [[TMP15]], i64 [[TMP25]]710; RV64-NEXT: [[TMP21:%.*]] = getelementptr float, ptr [[TMP20]], i64 [[TMP18]]711; RV64-NEXT: [[VP_REVERSE1:%.*]] = call <vscale x 4 x float> @llvm.experimental.vp.reverse.nxv4f32(<vscale x 4 x float> [[TMP14]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP19]])712; RV64-NEXT: call void @llvm.vp.store.nxv4f32.p0(<vscale x 4 x float> [[VP_REVERSE1]], ptr align 4 [[TMP21]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP19]])713; RV64-NEXT: [[TMP22:%.*]] = zext i32 [[TMP19]] to i64714; RV64-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP22]], [[INDEX]]715; RV64-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP22]]716; RV64-NEXT: [[TMP23:%.*]] = icmp eq i64 [[AVL_NEXT]], 0717; RV64-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]718; RV64: [[MIDDLE_BLOCK]]:719; RV64-NEXT: br label %[[EXIT:.*]]720; RV64: [[EXIT]]:721; RV64-NEXT: ret void722;723; RV32-LABEL: define void @vector_reverse_f32_simplify(724; RV32-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0]] {725; RV32-NEXT: [[ENTRY:.*:]]726; RV32-NEXT: br label %[[VECTOR_PH:.*]]727; RV32: [[VECTOR_PH]]:728; RV32-NEXT: br label %[[VECTOR_BODY:.*]]729; RV32: [[VECTOR_BODY]]:730; RV32-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]731; RV32-NEXT: [[AVL:%.*]] = phi i64 [ 1023, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]732; RV32-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)733; RV32-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]734; RV32-NEXT: [[TMP7:%.*]] = add nsw i64 [[OFFSET_IDX]], -1735; RV32-NEXT: [[TMP8:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP7]]736; RV32-NEXT: [[TMP10:%.*]] = mul i32 0, [[TMP9]]737; RV32-NEXT: [[TMP11:%.*]] = sub i32 [[TMP9]], 1738; RV32-NEXT: [[TMP12:%.*]] = mul i32 -1, [[TMP11]]739; RV32-NEXT: [[TMP13:%.*]] = getelementptr float, ptr [[TMP8]], i32 [[TMP10]]740; RV32-NEXT: [[TMP14:%.*]] = getelementptr float, ptr [[TMP13]], i32 [[TMP12]]741; RV32-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP14]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])742; RV32-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vp.reverse.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])743; RV32-NEXT: [[TMP15:%.*]] = fadd <vscale x 4 x float> [[REVERSE]], splat (float 1.000000e+00)744; RV32-NEXT: [[TMP16:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP7]]745; RV32-NEXT: [[TMP17:%.*]] = mul i32 0, [[TMP9]]746; RV32-NEXT: [[TMP19:%.*]] = sub i32 [[TMP9]], 1747; RV32-NEXT: [[TMP20:%.*]] = mul i32 -1, [[TMP19]]748; RV32-NEXT: [[TMP18:%.*]] = getelementptr float, ptr [[TMP16]], i32 [[TMP17]]749; RV32-NEXT: [[TMP22:%.*]] = getelementptr float, ptr [[TMP18]], i32 [[TMP20]]750; RV32-NEXT: [[VP_REVERSE1:%.*]] = call <vscale x 4 x float> @llvm.experimental.vp.reverse.nxv4f32(<vscale x 4 x float> [[TMP15]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])751; RV32-NEXT: call void @llvm.vp.store.nxv4f32.p0(<vscale x 4 x float> [[VP_REVERSE1]], ptr align 4 [[TMP22]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])752; RV32-NEXT: [[TMP23:%.*]] = zext i32 [[TMP9]] to i64753; RV32-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP23]], [[INDEX]]754; RV32-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP23]]755; RV32-NEXT: [[TMP21:%.*]] = icmp eq i64 [[AVL_NEXT]], 0756; RV32-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]757; RV32: [[MIDDLE_BLOCK]]:758; RV32-NEXT: br label %[[EXIT:.*]]759; RV32: [[EXIT]]:760; RV32-NEXT: ret void761;762; RV64-UF2-LABEL: define void @vector_reverse_f32_simplify(763; RV64-UF2-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0]] {764; RV64-UF2-NEXT: [[ENTRY:.*]]:765; RV64-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()766; RV64-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3767; RV64-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1023, [[TMP1]]768; RV64-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]769; RV64-UF2: [[VECTOR_PH]]:770; RV64-UF2-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()771; RV64-UF2-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4772; RV64-UF2-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 2773; RV64-UF2-NEXT: [[N_VEC:%.*]] = urem i64 1023, [[TMP6]]774; RV64-UF2-NEXT: [[TMP7:%.*]] = sub i64 1023, [[N_VEC]]775; RV64-UF2-NEXT: [[TMP33:%.*]] = sub i64 1023, [[TMP7]]776; RV64-UF2-NEXT: br label %[[VECTOR_BODY:.*]]777; RV64-UF2: [[VECTOR_BODY]]:778; RV64-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]779; RV64-UF2-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]780; RV64-UF2-NEXT: [[TMP8:%.*]] = add nsw i64 [[OFFSET_IDX]], -1781; RV64-UF2-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP8]]782; RV64-UF2-NEXT: [[TMP10:%.*]] = mul i64 0, [[TMP5]]783; RV64-UF2-NEXT: [[TMP11:%.*]] = sub i64 [[TMP5]], 1784; RV64-UF2-NEXT: [[TMP12:%.*]] = mul i64 -1, [[TMP11]]785; RV64-UF2-NEXT: [[TMP13:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[TMP10]]786; RV64-UF2-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[TMP12]]787; RV64-UF2-NEXT: [[TMP15:%.*]] = mul i64 -1, [[TMP5]]788; RV64-UF2-NEXT: [[TMP16:%.*]] = sub i64 [[TMP5]], 1789; RV64-UF2-NEXT: [[TMP17:%.*]] = mul i64 -1, [[TMP16]]790; RV64-UF2-NEXT: [[TMP18:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[TMP15]]791; RV64-UF2-NEXT: [[TMP19:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[TMP17]]792; RV64-UF2-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP14]], align 4793; RV64-UF2-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> [[WIDE_LOAD]])794; RV64-UF2-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x float>, ptr [[TMP19]], align 4795; RV64-UF2-NEXT: [[REVERSE2:%.*]] = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> [[WIDE_LOAD1]])796; RV64-UF2-NEXT: [[TMP20:%.*]] = fadd <vscale x 4 x float> [[REVERSE]], splat (float 1.000000e+00)797; RV64-UF2-NEXT: [[TMP21:%.*]] = fadd <vscale x 4 x float> [[REVERSE2]], splat (float 1.000000e+00)798; RV64-UF2-NEXT: [[TMP22:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP8]]799; RV64-UF2-NEXT: [[TMP23:%.*]] = mul i64 0, [[TMP5]]800; RV64-UF2-NEXT: [[TMP24:%.*]] = sub i64 [[TMP5]], 1801; RV64-UF2-NEXT: [[TMP25:%.*]] = mul i64 -1, [[TMP24]]802; RV64-UF2-NEXT: [[TMP26:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[TMP23]]803; RV64-UF2-NEXT: [[TMP27:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[TMP25]]804; RV64-UF2-NEXT: [[TMP28:%.*]] = mul i64 -1, [[TMP5]]805; RV64-UF2-NEXT: [[TMP29:%.*]] = sub i64 [[TMP5]], 1806; RV64-UF2-NEXT: [[TMP30:%.*]] = mul i64 -1, [[TMP29]]807; RV64-UF2-NEXT: [[TMP31:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[TMP28]]808; RV64-UF2-NEXT: [[TMP32:%.*]] = getelementptr inbounds float, ptr [[TMP31]], i64 [[TMP30]]809; RV64-UF2-NEXT: [[REVERSE3:%.*]] = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> [[TMP20]])810; RV64-UF2-NEXT: store <vscale x 4 x float> [[REVERSE3]], ptr [[TMP27]], align 4811; RV64-UF2-NEXT: [[REVERSE4:%.*]] = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> [[TMP21]])812; RV64-UF2-NEXT: store <vscale x 4 x float> [[REVERSE4]], ptr [[TMP32]], align 4813; RV64-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP6]]814; RV64-UF2-NEXT: [[TMP34:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[TMP7]]815; RV64-UF2-NEXT: br i1 [[TMP34]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]816; RV64-UF2: [[MIDDLE_BLOCK]]:817; RV64-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 1023, [[TMP7]]818; RV64-UF2-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]819; RV64-UF2: [[SCALAR_PH]]:820; RV64-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP33]], %[[MIDDLE_BLOCK]] ], [ 1023, %[[ENTRY]] ]821; RV64-UF2-NEXT: br label %[[FOR_BODY:.*]]822; RV64-UF2: [[FOR_BODY]]:823;824entry:825 br label %for.body826 827for.body:828 %dec.iv = phi i64 [ 1023, %entry ], [ %iv.next, %for.body ]829 %iv.next = add nsw i64 %dec.iv, -1830 %arrayidx.b = getelementptr inbounds float, ptr %B, i64 %iv.next831 %0 = load float, ptr %arrayidx.b, align 4832 %fadd = fadd float %0, 1.000000e+00833 %arrayidx.a = getelementptr inbounds float, ptr %A, i64 %iv.next834 store float %fadd, ptr %arrayidx.a, align 4835 %cmp = icmp ugt i64 %dec.iv, 1836 br i1 %cmp, label %for.body, label %exit, !llvm.loop !0837 838exit:839 ret void840}841 842define void @vector_reverse_irregular_type(ptr noalias %A, ptr noalias %B) {843; RV64-LABEL: define void @vector_reverse_irregular_type(844; RV64-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0]] {845; RV64-NEXT: [[ENTRY:.*:]]846; RV64-NEXT: br label %[[VECTOR_PH:.*]]847; RV64: [[VECTOR_PH]]:848; RV64-NEXT: br label %[[VECTOR_BODY:.*]]849; RV64: [[VECTOR_BODY]]:850; RV64-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]851; RV64-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]852; RV64-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0853; RV64-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], -1854; RV64-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], -2855; RV64-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], -3856; RV64-NEXT: [[TMP4:%.*]] = add nsw i64 [[TMP0]], -1857; RV64-NEXT: [[TMP5:%.*]] = add nsw i64 [[TMP1]], -1858; RV64-NEXT: [[TMP6:%.*]] = add nsw i64 [[TMP2]], -1859; RV64-NEXT: [[TMP7:%.*]] = add nsw i64 [[TMP3]], -1860; RV64-NEXT: [[TMP8:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP4]]861; RV64-NEXT: [[TMP9:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP5]]862; RV64-NEXT: [[TMP10:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP6]]863; RV64-NEXT: [[TMP11:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP7]]864; RV64-NEXT: [[TMP12:%.*]] = load i7, ptr [[TMP8]], align 1865; RV64-NEXT: [[TMP13:%.*]] = load i7, ptr [[TMP9]], align 1866; RV64-NEXT: [[TMP14:%.*]] = load i7, ptr [[TMP10]], align 1867; RV64-NEXT: [[TMP15:%.*]] = load i7, ptr [[TMP11]], align 1868; RV64-NEXT: [[TMP16:%.*]] = insertelement <4 x i7> poison, i7 [[TMP12]], i32 0869; RV64-NEXT: [[TMP17:%.*]] = insertelement <4 x i7> [[TMP16]], i7 [[TMP13]], i32 1870; RV64-NEXT: [[TMP18:%.*]] = insertelement <4 x i7> [[TMP17]], i7 [[TMP14]], i32 2871; RV64-NEXT: [[TMP19:%.*]] = insertelement <4 x i7> [[TMP18]], i7 [[TMP15]], i32 3872; RV64-NEXT: [[TMP20:%.*]] = add <4 x i7> [[TMP19]], splat (i7 1)873; RV64-NEXT: [[TMP25:%.*]] = extractelement <4 x i7> [[TMP20]], i32 0874; RV64-NEXT: [[TMP26:%.*]] = extractelement <4 x i7> [[TMP20]], i32 1875; RV64-NEXT: [[TMP27:%.*]] = extractelement <4 x i7> [[TMP20]], i32 2876; RV64-NEXT: [[TMP28:%.*]] = extractelement <4 x i7> [[TMP20]], i32 3877; RV64-NEXT: [[TMP21:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP4]]878; RV64-NEXT: [[TMP22:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP5]]879; RV64-NEXT: [[TMP23:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP6]]880; RV64-NEXT: [[TMP24:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP7]]881; RV64-NEXT: store i7 [[TMP25]], ptr [[TMP21]], align 1882; RV64-NEXT: store i7 [[TMP26]], ptr [[TMP22]], align 1883; RV64-NEXT: store i7 [[TMP27]], ptr [[TMP23]], align 1884; RV64-NEXT: store i7 [[TMP28]], ptr [[TMP24]], align 1885; RV64-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4886; RV64-NEXT: [[TMP29:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1020887; RV64-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]888; RV64: [[MIDDLE_BLOCK]]:889; RV64-NEXT: br label %[[SCALAR_PH:.*]]890; RV64: [[SCALAR_PH]]:891; RV64-NEXT: br label %[[FOR_BODY:.*]]892; RV64: [[FOR_BODY]]:893;894; RV32-LABEL: define void @vector_reverse_irregular_type(895; RV32-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0]] {896; RV32-NEXT: [[ENTRY:.*:]]897; RV32-NEXT: br label %[[VECTOR_PH:.*]]898; RV32: [[VECTOR_PH]]:899; RV32-NEXT: br label %[[VECTOR_BODY:.*]]900; RV32: [[VECTOR_BODY]]:901; RV32-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]902; RV32-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]903; RV32-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0904; RV32-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], -1905; RV32-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], -2906; RV32-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], -3907; RV32-NEXT: [[TMP4:%.*]] = add nsw i64 [[TMP0]], -1908; RV32-NEXT: [[TMP5:%.*]] = add nsw i64 [[TMP1]], -1909; RV32-NEXT: [[TMP6:%.*]] = add nsw i64 [[TMP2]], -1910; RV32-NEXT: [[TMP7:%.*]] = add nsw i64 [[TMP3]], -1911; RV32-NEXT: [[TMP8:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP4]]912; RV32-NEXT: [[TMP9:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP5]]913; RV32-NEXT: [[TMP10:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP6]]914; RV32-NEXT: [[TMP11:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP7]]915; RV32-NEXT: [[TMP12:%.*]] = load i7, ptr [[TMP8]], align 1916; RV32-NEXT: [[TMP13:%.*]] = load i7, ptr [[TMP9]], align 1917; RV32-NEXT: [[TMP14:%.*]] = load i7, ptr [[TMP10]], align 1918; RV32-NEXT: [[TMP15:%.*]] = load i7, ptr [[TMP11]], align 1919; RV32-NEXT: [[TMP16:%.*]] = insertelement <4 x i7> poison, i7 [[TMP12]], i32 0920; RV32-NEXT: [[TMP17:%.*]] = insertelement <4 x i7> [[TMP16]], i7 [[TMP13]], i32 1921; RV32-NEXT: [[TMP18:%.*]] = insertelement <4 x i7> [[TMP17]], i7 [[TMP14]], i32 2922; RV32-NEXT: [[TMP19:%.*]] = insertelement <4 x i7> [[TMP18]], i7 [[TMP15]], i32 3923; RV32-NEXT: [[TMP20:%.*]] = add <4 x i7> [[TMP19]], splat (i7 1)924; RV32-NEXT: [[TMP25:%.*]] = extractelement <4 x i7> [[TMP20]], i32 0925; RV32-NEXT: [[TMP26:%.*]] = extractelement <4 x i7> [[TMP20]], i32 1926; RV32-NEXT: [[TMP27:%.*]] = extractelement <4 x i7> [[TMP20]], i32 2927; RV32-NEXT: [[TMP28:%.*]] = extractelement <4 x i7> [[TMP20]], i32 3928; RV32-NEXT: [[TMP21:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP4]]929; RV32-NEXT: [[TMP22:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP5]]930; RV32-NEXT: [[TMP23:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP6]]931; RV32-NEXT: [[TMP24:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP7]]932; RV32-NEXT: store i7 [[TMP25]], ptr [[TMP21]], align 1933; RV32-NEXT: store i7 [[TMP26]], ptr [[TMP22]], align 1934; RV32-NEXT: store i7 [[TMP27]], ptr [[TMP23]], align 1935; RV32-NEXT: store i7 [[TMP28]], ptr [[TMP24]], align 1936; RV32-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4937; RV32-NEXT: [[TMP29:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1020938; RV32-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]939; RV32: [[MIDDLE_BLOCK]]:940; RV32-NEXT: br label %[[SCALAR_PH:.*]]941; RV32: [[SCALAR_PH]]:942; RV32-NEXT: br label %[[FOR_BODY:.*]]943; RV32: [[FOR_BODY]]:944;945; RV64-UF2-LABEL: define void @vector_reverse_irregular_type(946; RV64-UF2-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0]] {947; RV64-UF2-NEXT: [[ENTRY:.*:]]948; RV64-UF2-NEXT: br label %[[VECTOR_PH:.*]]949; RV64-UF2: [[VECTOR_PH]]:950; RV64-UF2-NEXT: br label %[[VECTOR_BODY:.*]]951; RV64-UF2: [[VECTOR_BODY]]:952; RV64-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]953; RV64-UF2-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]954; RV64-UF2-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0955; RV64-UF2-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], -1956; RV64-UF2-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], -2957; RV64-UF2-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], -3958; RV64-UF2-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], -4959; RV64-UF2-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], -5960; RV64-UF2-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], -6961; RV64-UF2-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], -7962; RV64-UF2-NEXT: [[TMP8:%.*]] = add nsw i64 [[TMP0]], -1963; RV64-UF2-NEXT: [[TMP9:%.*]] = add nsw i64 [[TMP1]], -1964; RV64-UF2-NEXT: [[TMP10:%.*]] = add nsw i64 [[TMP2]], -1965; RV64-UF2-NEXT: [[TMP11:%.*]] = add nsw i64 [[TMP3]], -1966; RV64-UF2-NEXT: [[TMP12:%.*]] = add nsw i64 [[TMP4]], -1967; RV64-UF2-NEXT: [[TMP13:%.*]] = add nsw i64 [[TMP5]], -1968; RV64-UF2-NEXT: [[TMP14:%.*]] = add nsw i64 [[TMP6]], -1969; RV64-UF2-NEXT: [[TMP15:%.*]] = add nsw i64 [[TMP7]], -1970; RV64-UF2-NEXT: [[TMP16:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP8]]971; RV64-UF2-NEXT: [[TMP17:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP9]]972; RV64-UF2-NEXT: [[TMP18:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP10]]973; RV64-UF2-NEXT: [[TMP19:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP11]]974; RV64-UF2-NEXT: [[TMP20:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP12]]975; RV64-UF2-NEXT: [[TMP21:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP13]]976; RV64-UF2-NEXT: [[TMP22:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP14]]977; RV64-UF2-NEXT: [[TMP23:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP15]]978; RV64-UF2-NEXT: [[TMP24:%.*]] = load i7, ptr [[TMP16]], align 1979; RV64-UF2-NEXT: [[TMP25:%.*]] = load i7, ptr [[TMP17]], align 1980; RV64-UF2-NEXT: [[TMP26:%.*]] = load i7, ptr [[TMP18]], align 1981; RV64-UF2-NEXT: [[TMP27:%.*]] = load i7, ptr [[TMP19]], align 1982; RV64-UF2-NEXT: [[TMP28:%.*]] = insertelement <4 x i7> poison, i7 [[TMP24]], i32 0983; RV64-UF2-NEXT: [[TMP29:%.*]] = insertelement <4 x i7> [[TMP28]], i7 [[TMP25]], i32 1984; RV64-UF2-NEXT: [[TMP30:%.*]] = insertelement <4 x i7> [[TMP29]], i7 [[TMP26]], i32 2985; RV64-UF2-NEXT: [[TMP31:%.*]] = insertelement <4 x i7> [[TMP30]], i7 [[TMP27]], i32 3986; RV64-UF2-NEXT: [[TMP32:%.*]] = load i7, ptr [[TMP20]], align 1987; RV64-UF2-NEXT: [[TMP33:%.*]] = load i7, ptr [[TMP21]], align 1988; RV64-UF2-NEXT: [[TMP34:%.*]] = load i7, ptr [[TMP22]], align 1989; RV64-UF2-NEXT: [[TMP35:%.*]] = load i7, ptr [[TMP23]], align 1990; RV64-UF2-NEXT: [[TMP36:%.*]] = insertelement <4 x i7> poison, i7 [[TMP32]], i32 0991; RV64-UF2-NEXT: [[TMP37:%.*]] = insertelement <4 x i7> [[TMP36]], i7 [[TMP33]], i32 1992; RV64-UF2-NEXT: [[TMP38:%.*]] = insertelement <4 x i7> [[TMP37]], i7 [[TMP34]], i32 2993; RV64-UF2-NEXT: [[TMP39:%.*]] = insertelement <4 x i7> [[TMP38]], i7 [[TMP35]], i32 3994; RV64-UF2-NEXT: [[TMP40:%.*]] = add <4 x i7> [[TMP31]], splat (i7 1)995; RV64-UF2-NEXT: [[TMP50:%.*]] = extractelement <4 x i7> [[TMP40]], i32 0996; RV64-UF2-NEXT: [[TMP51:%.*]] = extractelement <4 x i7> [[TMP40]], i32 1997; RV64-UF2-NEXT: [[TMP52:%.*]] = extractelement <4 x i7> [[TMP40]], i32 2998; RV64-UF2-NEXT: [[TMP53:%.*]] = extractelement <4 x i7> [[TMP40]], i32 3999; RV64-UF2-NEXT: [[TMP41:%.*]] = add <4 x i7> [[TMP39]], splat (i7 1)1000; RV64-UF2-NEXT: [[TMP54:%.*]] = extractelement <4 x i7> [[TMP41]], i32 01001; RV64-UF2-NEXT: [[TMP55:%.*]] = extractelement <4 x i7> [[TMP41]], i32 11002; RV64-UF2-NEXT: [[TMP56:%.*]] = extractelement <4 x i7> [[TMP41]], i32 21003; RV64-UF2-NEXT: [[TMP57:%.*]] = extractelement <4 x i7> [[TMP41]], i32 31004; RV64-UF2-NEXT: [[TMP42:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP8]]1005; RV64-UF2-NEXT: [[TMP43:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP9]]1006; RV64-UF2-NEXT: [[TMP44:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP10]]1007; RV64-UF2-NEXT: [[TMP45:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP11]]1008; RV64-UF2-NEXT: [[TMP46:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP12]]1009; RV64-UF2-NEXT: [[TMP47:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP13]]1010; RV64-UF2-NEXT: [[TMP48:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP14]]1011; RV64-UF2-NEXT: [[TMP49:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP15]]1012; RV64-UF2-NEXT: store i7 [[TMP50]], ptr [[TMP42]], align 11013; RV64-UF2-NEXT: store i7 [[TMP51]], ptr [[TMP43]], align 11014; RV64-UF2-NEXT: store i7 [[TMP52]], ptr [[TMP44]], align 11015; RV64-UF2-NEXT: store i7 [[TMP53]], ptr [[TMP45]], align 11016; RV64-UF2-NEXT: store i7 [[TMP54]], ptr [[TMP46]], align 11017; RV64-UF2-NEXT: store i7 [[TMP55]], ptr [[TMP47]], align 11018; RV64-UF2-NEXT: store i7 [[TMP56]], ptr [[TMP48]], align 11019; RV64-UF2-NEXT: store i7 [[TMP57]], ptr [[TMP49]], align 11020; RV64-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 81021; RV64-UF2-NEXT: [[TMP58:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10161022; RV64-UF2-NEXT: br i1 [[TMP58]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]1023; RV64-UF2: [[MIDDLE_BLOCK]]:1024; RV64-UF2-NEXT: br label %[[SCALAR_PH:.*]]1025; RV64-UF2: [[SCALAR_PH]]:1026; RV64-UF2-NEXT: br label %[[FOR_BODY:.*]]1027; RV64-UF2: [[FOR_BODY]]:1028;1029entry:1030 br label %for.body1031 1032for.body:1033 %dec.iv = phi i64 [ 1023, %entry ], [ %iv.next, %for.body ]1034 %iv.next = add nsw i64 %dec.iv, -11035 %arrayidx.b = getelementptr inbounds i7, ptr %B, i64 %iv.next1036 %0 = load i7, ptr %arrayidx.b, align 11037 %add = add i7 %0, 11038 %arrayidx.a = getelementptr inbounds i7, ptr %A, i64 %iv.next1039 store i7 %add, ptr %arrayidx.a, align 11040 %cmp = icmp ugt i64 %dec.iv, 11041 br i1 %cmp, label %for.body, label %exit, !llvm.loop !41042 1043exit:1044 ret void1045}1046 1047!0 = distinct !{!0, !1, !2, !3}1048!1 = !{!"llvm.loop.vectorize.width", i32 4}1049!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}1050!3 = !{!"llvm.loop.vectorize.enable", i1 true}1051!4 = distinct !{!4, !1, !3}1052