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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=loop-vectorize -scalable-vectorization=on -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -mtriple riscv64-linux-gnu -mattr=+v,+f -S 2>%t | FileCheck %s -check-prefix=CHECK3 4; Exercise tail folding on RISCV w/scalable vectors.5 6target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"7target triple = "riscv64"8 9define void @vector_add(ptr noalias nocapture %a, i64 %v, i64 %n) {10; CHECK-LABEL: @vector_add(11; CHECK-NEXT: entry:12; CHECK-NEXT: br label [[VECTOR_PH:%.*]]13; CHECK: vector.ph:14; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[V:%.*]], i64 015; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer16; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]17; CHECK: vector.body:18; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]19; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1025, [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]20; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)21; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]22; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP11]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP10]])23; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 2 x i64> [[VP_OP_LOAD]], [[BROADCAST_SPLAT]]24; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP7]], ptr align 8 [[TMP11]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP10]])25; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP10]] to i6426; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP8]], [[EVL_BASED_IV]]27; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP8]]28; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[AVL_NEXT]], 029; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]30; CHECK: middle.block:31; CHECK-NEXT: br label [[FOR_BODY:%.*]]32; CHECK: for.end:33; CHECK-NEXT: ret void34;35entry:36 br label %for.body37 38for.body:39 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]40 %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv41 %elem = load i64, ptr %arrayidx42 %add = add i64 %elem, %v43 store i64 %add, ptr %arrayidx44 %iv.next = add nuw nsw i64 %iv, 145 %exitcond.not = icmp eq i64 %iv.next, 102546 br i1 %exitcond.not, label %for.end, label %for.body47 48for.end:49 ret void50}51 52 53; a[b[i]] = v, exercise scatter support54define void @indexed_store(ptr noalias nocapture %a, ptr noalias nocapture %b, i64 %v, i64 %n) {55; CHECK-LABEL: @indexed_store(56; CHECK-NEXT: entry:57; CHECK-NEXT: br label [[VECTOR_PH:%.*]]58; CHECK: vector.ph:59; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[V:%.*]], i64 060; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer61; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]62; CHECK: vector.body:63; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]64; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1025, [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]65; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)66; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[B:%.*]], i64 [[EVL_BASED_IV]]67; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP8]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP7]])68; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], <vscale x 2 x i64> [[WIDE_MASKED_LOAD]]69; CHECK-NEXT: call void @llvm.vp.scatter.nxv2i64.nxv2p0(<vscale x 2 x i64> [[BROADCAST_SPLAT]], <vscale x 2 x ptr> align 8 [[TMP10]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP7]])70; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP7]] to i6471; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP12]], [[EVL_BASED_IV]]72; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP12]]73; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[AVL_NEXT]], 074; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]75; CHECK: middle.block:76; CHECK-NEXT: br label [[FOR_BODY:%.*]]77; CHECK: for.end:78; CHECK-NEXT: ret void79;80entry:81 br label %for.body82 83for.body:84 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]85 %baddr = getelementptr inbounds i64, ptr %b, i64 %iv86 %aidx = load i64, ptr %baddr87 %aaddr = getelementptr inbounds i64, ptr %a, i64 %aidx88 store i64 %v, ptr %aaddr89 %iv.next = add nuw nsw i64 %iv, 190 %exitcond.not = icmp eq i64 %iv.next, 102591 br i1 %exitcond.not, label %for.end, label %for.body92 93for.end:94 ret void95}96 97define i64 @indexed_load(ptr noalias nocapture %a, ptr noalias nocapture %b, i64 %v, i64 %n) {98; CHECK-LABEL: @indexed_load(99; CHECK-NEXT: entry:100; CHECK-NEXT: br label [[VECTOR_PH:%.*]]101; CHECK: vector.ph:102; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]103; CHECK: vector.body:104; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]105; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[VECTOR_BODY]] ]106; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1025, [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]107; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)108; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[B:%.*]], i64 [[EVL_BASED_IV]]109; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP8]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP7]])110; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], <vscale x 2 x i64> [[WIDE_MASKED_LOAD]]111; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 2 x i64> @llvm.vp.gather.nxv2i64.nxv2p0(<vscale x 2 x ptr> align 8 [[TMP10]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP7]])112; CHECK-NEXT: [[TMP12:%.*]] = add <vscale x 2 x i64> [[VEC_PHI]], [[WIDE_MASKED_GATHER]]113; CHECK-NEXT: [[TMP11]] = call <vscale x 2 x i64> @llvm.vp.merge.nxv2i64(<vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> [[TMP12]], <vscale x 2 x i64> [[VEC_PHI]], i32 [[TMP7]])114; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP7]] to i64115; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP15]], [[EVL_BASED_IV]]116; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP15]]117; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[AVL_NEXT]], 0118; CHECK-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]119; CHECK: middle.block:120; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> [[TMP11]])121; CHECK-NEXT: br label [[FOR_BODY:%.*]]122; CHECK: for.end:123; CHECK-NEXT: ret i64 [[TMP14]]124;125entry:126 br label %for.body127 128for.body:129 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]130 %sum = phi i64 [0, %entry], [%sum.next, %for.body]131 %baddr = getelementptr inbounds i64, ptr %b, i64 %iv132 %aidx = load i64, ptr %baddr133 %aaddr = getelementptr inbounds i64, ptr %a, i64 %aidx134 %elem = load i64, ptr %aaddr135 %iv.next = add nuw nsw i64 %iv, 1136 %sum.next = add i64 %sum, %elem137 %exitcond.not = icmp eq i64 %iv.next, 1025138 br i1 %exitcond.not, label %for.end, label %for.body139 140for.end:141 ret i64 %sum.next142}143 144define void @splat_int(ptr noalias nocapture %a, i64 %v, i64 %n) {145; CHECK-LABEL: @splat_int(146; CHECK-NEXT: entry:147; CHECK-NEXT: br label [[VECTOR_PH:%.*]]148; CHECK: vector.ph:149; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[V:%.*]], i64 0150; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer151; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]152; CHECK: vector.body:153; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]154; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1025, [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]155; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)156; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]157; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[BROADCAST_SPLAT]], ptr align 8 [[TMP10]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP9]])158; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP9]] to i64159; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP7]], [[EVL_BASED_IV]]160; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP7]]161; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[AVL_NEXT]], 0162; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]163; CHECK: middle.block:164; CHECK-NEXT: br label [[FOR_BODY:%.*]]165; CHECK: for.end:166; CHECK-NEXT: ret void167;168entry:169 br label %for.body170 171for.body:172 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]173 %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv174 store i64 %v, ptr %arrayidx175 %iv.next = add nuw nsw i64 %iv, 1176 %exitcond.not = icmp eq i64 %iv.next, 1025177 br i1 %exitcond.not, label %for.end, label %for.body178 179for.end:180 ret void181}182 183define void @uniform_store(ptr noalias nocapture %a, ptr noalias nocapture %b, i64 %v, i64 %n) {184; CHECK-LABEL: @uniform_store(185; CHECK-NEXT: entry:186; CHECK-NEXT: br label [[VECTOR_PH:%.*]]187; CHECK: vector.ph:188; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[V:%.*]], i64 0189; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer190; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]191; CHECK: vector.body:192; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]193; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1025, [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]194; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)195; CHECK-NEXT: store i64 [[V]], ptr [[B:%.*]], align 8196; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]197; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[BROADCAST_SPLAT]], ptr align 8 [[TMP8]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP7]])198; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP7]] to i64199; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP9]], [[EVL_BASED_IV]]200; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP9]]201; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[AVL_NEXT]], 0202; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]203; CHECK: middle.block:204; CHECK-NEXT: br label [[FOR_BODY:%.*]]205; CHECK: for.end:206; CHECK-NEXT: ret void207;208entry:209 br label %for.body210 211for.body:212 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]213 store i64 %v, ptr %b, align 8214 %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv215 store i64 %v, ptr %arrayidx216 %iv.next = add nuw nsw i64 %iv, 1217 %exitcond.not = icmp eq i64 %iv.next, 1025218 br i1 %exitcond.not, label %for.end, label %for.body219 220for.end:221 ret void222}223 224define i64 @uniform_load(ptr noalias nocapture %a, ptr noalias nocapture %b, i64 %n) {225; CHECK-LABEL: @uniform_load(226; CHECK-NEXT: entry:227; CHECK-NEXT: br label [[ENTRY:%.*]]228; CHECK: vector.ph:229; CHECK-NEXT: br label [[FOR_BODY:%.*]]230; CHECK: vector.body:231; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]232; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1025, [[ENTRY]] ], [ [[AVL_NEXT:%.*]], [[FOR_BODY]] ]233; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)234; CHECK-NEXT: [[V:%.*]] = load i64, ptr [[B:%.*]], align 8235; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[V]], i64 0236; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer237; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[IV]]238; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[BROADCAST_SPLAT]], ptr align 8 [[ARRAYIDX]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP0]])239; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP0]] to i64240; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[TMP5]], [[IV]]241; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP5]]242; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[AVL_NEXT]], 0243; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]244; CHECK: middle.block:245; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[TMP5]], 1246; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()247; CHECK-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 2248; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[TMP10]], 0249; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 2 x i64> [[BROADCAST_SPLAT]], i64 [[TMP8]]250; CHECK-NEXT: br label [[FOR_BODY1:%.*]]251; CHECK: for.end:252; CHECK-NEXT: ret i64 [[TMP12]]253;254entry:255 br label %for.body256 257for.body:258 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]259 %v = load i64, ptr %b, align 8260 %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv261 store i64 %v, ptr %arrayidx262 %iv.next = add nuw nsw i64 %iv, 1263 %exitcond.not = icmp eq i64 %iv.next, 1025264 br i1 %exitcond.not, label %for.end, label %for.body265 266for.end:267 ret i64 %v268}269 270 271define void @vector_add_trip1024(ptr noalias nocapture %a, i64 %v, i64 %n) {272; CHECK-LABEL: @vector_add_trip1024(273; CHECK-NEXT: entry:274; CHECK-NEXT: br label [[VECTOR_PH:%.*]]275; CHECK: vector.ph:276; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[V:%.*]], i64 0277; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer278; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]279; CHECK: vector.body:280; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]281; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1024, [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]282; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)283; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]284; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP11]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP10]])285; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 2 x i64> [[VP_OP_LOAD]], [[BROADCAST_SPLAT]]286; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP7]], ptr align 8 [[TMP11]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP10]])287; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP10]] to i64288; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP8]], [[EVL_BASED_IV]]289; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP8]]290; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[AVL_NEXT]], 0291; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]292; CHECK: middle.block:293; CHECK-NEXT: br label [[FOR_BODY:%.*]]294; CHECK: for.end:295; CHECK-NEXT: ret void296;297entry:298 br label %for.body299 300for.body:301 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]302 %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv303 %elem = load i64, ptr %arrayidx304 %add = add i64 %elem, %v305 store i64 %add, ptr %arrayidx306 %iv.next = add nuw nsw i64 %iv, 1307 %exitcond.not = icmp eq i64 %iv.next, 1024308 br i1 %exitcond.not, label %for.end, label %for.body309 310for.end:311 ret void312}313