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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -passes=loop-vectorize \3; RUN: -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue \4; RUN: -mtriple=riscv64 -mattr=+v -S %s | FileCheck %s --check-prefix=IF-EVL5 6; RUN: opt -passes=loop-vectorize \7; RUN: -prefer-predicate-over-epilogue=scalar-epilogue \8; RUN: -mtriple=riscv64 -mattr=+v -S %s | FileCheck %s --check-prefix=NO-VP9 10define void @vp_smax(ptr %a, ptr %b, ptr %c, i64 %N) {11; IF-EVL-LABEL: define void @vp_smax(12; IF-EVL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {13; IF-EVL-NEXT: [[ENTRY:.*:]]14; IF-EVL-NEXT: [[C3:%.*]] = ptrtoint ptr [[C]] to i6415; IF-EVL-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i6416; IF-EVL-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i6417; IF-EVL-NEXT: br label %[[VECTOR_MEMCHECK:.*]]18; IF-EVL: [[VECTOR_MEMCHECK]]:19; IF-EVL-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()20; IF-EVL-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 421; IF-EVL-NEXT: [[TMP23:%.*]] = mul i64 [[TMP5]], 422; IF-EVL-NEXT: [[TMP24:%.*]] = sub i64 [[A1]], [[B2]]23; IF-EVL-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP24]], [[TMP23]]24; IF-EVL-NEXT: [[TMP25:%.*]] = mul i64 [[TMP5]], 425; IF-EVL-NEXT: [[TMP26:%.*]] = sub i64 [[A1]], [[C3]]26; IF-EVL-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP26]], [[TMP25]]27; IF-EVL-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]28; IF-EVL-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]29; IF-EVL: [[VECTOR_PH]]:30; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]31; IF-EVL: [[VECTOR_BODY]]:32; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]33; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]34; IF-EVL-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)35; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[EVL_BASED_IV]]36; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])37; IF-EVL-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[EVL_BASED_IV]]38; IF-EVL-NEXT: [[VP_OP_LOAD5:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP13]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])39; IF-EVL-NEXT: [[TMP29:%.*]] = call <vscale x 4 x i32> @llvm.smax.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VP_OP_LOAD5]])40; IF-EVL-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[EVL_BASED_IV]]41; IF-EVL-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP29]], ptr align 4 [[TMP16]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])42; IF-EVL-NEXT: [[TMP18:%.*]] = zext i32 [[TMP9]] to i6443; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP18]], [[EVL_BASED_IV]]44; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP18]]45; IF-EVL-NEXT: [[TMP17:%.*]] = icmp eq i64 [[AVL_NEXT]], 046; IF-EVL-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]47; IF-EVL: [[MIDDLE_BLOCK]]:48; IF-EVL-NEXT: br label %[[EXIT:.*]]49; IF-EVL: [[SCALAR_PH]]:50; IF-EVL-NEXT: br label %[[LOOP:.*]]51; IF-EVL: [[LOOP]]:52; IF-EVL-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[SCALAR_PH]] ]53; IF-EVL-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]54; IF-EVL-NEXT: [[TMP20:%.*]] = load i32, ptr [[GEP]], align 455; IF-EVL-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[IV]]56; IF-EVL-NEXT: [[TMP21:%.*]] = load i32, ptr [[GEP3]], align 457; IF-EVL-NEXT: [[DOT:%.*]] = tail call i32 @llvm.smax.i32(i32 [[TMP20]], i32 [[TMP21]])58; IF-EVL-NEXT: [[GEP11:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]59; IF-EVL-NEXT: store i32 [[DOT]], ptr [[GEP11]], align 460; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 161; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]62; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]63; IF-EVL: [[EXIT]]:64; IF-EVL-NEXT: ret void65;66; NO-VP-LABEL: define void @vp_smax(67; NO-VP-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {68; NO-VP-NEXT: [[ENTRY:.*]]:69; NO-VP-NEXT: [[C3:%.*]] = ptrtoint ptr [[C]] to i6470; NO-VP-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i6471; NO-VP-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i6472; NO-VP-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()73; NO-VP-NEXT: [[TMP11:%.*]] = shl nuw i64 [[TMP12]], 274; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP11]], i64 16)75; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP2]]76; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]77; NO-VP: [[VECTOR_MEMCHECK]]:78; NO-VP-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()79; NO-VP-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 480; NO-VP-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 481; NO-VP-NEXT: [[TMP6:%.*]] = sub i64 [[A1]], [[B2]]82; NO-VP-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]83; NO-VP-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 484; NO-VP-NEXT: [[TMP8:%.*]] = sub i64 [[A1]], [[C3]]85; NO-VP-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP8]], [[TMP7]]86; NO-VP-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]87; NO-VP-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]88; NO-VP: [[VECTOR_PH]]:89; NO-VP-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()90; NO-VP-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 491; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP10]]92; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]93; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]94; NO-VP: [[VECTOR_BODY]]:95; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]96; NO-VP-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]97; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP13]], align 498; NO-VP-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[INDEX]]99; NO-VP-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 4 x i32>, ptr [[TMP14]], align 4100; NO-VP-NEXT: [[TMP15:%.*]] = call <vscale x 4 x i32> @llvm.smax.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[WIDE_LOAD5]])101; NO-VP-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]102; NO-VP-NEXT: store <vscale x 4 x i32> [[TMP15]], ptr [[TMP16]], align 4103; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP10]]104; NO-VP-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]105; NO-VP-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]106; NO-VP: [[MIDDLE_BLOCK]]:107; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]108; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]109; NO-VP: [[SCALAR_PH]]:110; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]111; NO-VP-NEXT: br label %[[LOOP:.*]]112; NO-VP: [[LOOP]]:113; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]114; NO-VP-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]115; NO-VP-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP]], align 4116; NO-VP-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[IV]]117; NO-VP-NEXT: [[TMP1:%.*]] = load i32, ptr [[GEP3]], align 4118; NO-VP-NEXT: [[DOT:%.*]] = tail call i32 @llvm.smax.i32(i32 [[TMP0]], i32 [[TMP1]])119; NO-VP-NEXT: [[GEP11:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]120; NO-VP-NEXT: store i32 [[DOT]], ptr [[GEP11]], align 4121; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1122; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]123; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]124; NO-VP: [[EXIT]]:125; NO-VP-NEXT: ret void126;127 128entry:129 br label %loop130 131loop:132 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]133 %gep = getelementptr inbounds i32, ptr %b, i64 %iv134 %0 = load i32, ptr %gep, align 4135 %gep3 = getelementptr inbounds i32, ptr %c, i64 %iv136 %1 = load i32, ptr %gep3, align 4137 %. = tail call i32 @llvm.smax.i32(i32 %0, i32 %1)138 %gep11 = getelementptr inbounds i32, ptr %a, i64 %iv139 store i32 %., ptr %gep11, align 4140 %iv.next = add nuw nsw i64 %iv, 1141 %exitcond.not = icmp eq i64 %iv.next, %N142 br i1 %exitcond.not, label %exit, label %loop143 144exit:145 ret void146}147 148define void @vp_smin(ptr %a, ptr %b, ptr %c, i64 %N) {149; IF-EVL-LABEL: define void @vp_smin(150; IF-EVL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {151; IF-EVL-NEXT: [[ENTRY:.*:]]152; IF-EVL-NEXT: [[C3:%.*]] = ptrtoint ptr [[C]] to i64153; IF-EVL-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64154; IF-EVL-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64155; IF-EVL-NEXT: br label %[[VECTOR_MEMCHECK:.*]]156; IF-EVL: [[VECTOR_MEMCHECK]]:157; IF-EVL-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()158; IF-EVL-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4159; IF-EVL-NEXT: [[TMP23:%.*]] = mul i64 [[TMP5]], 4160; IF-EVL-NEXT: [[TMP24:%.*]] = sub i64 [[A1]], [[B2]]161; IF-EVL-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP24]], [[TMP23]]162; IF-EVL-NEXT: [[TMP25:%.*]] = mul i64 [[TMP5]], 4163; IF-EVL-NEXT: [[TMP26:%.*]] = sub i64 [[A1]], [[C3]]164; IF-EVL-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP26]], [[TMP25]]165; IF-EVL-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]166; IF-EVL-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]167; IF-EVL: [[VECTOR_PH]]:168; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]169; IF-EVL: [[VECTOR_BODY]]:170; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]171; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]172; IF-EVL-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)173; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[EVL_BASED_IV]]174; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])175; IF-EVL-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[EVL_BASED_IV]]176; IF-EVL-NEXT: [[VP_OP_LOAD5:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP13]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])177; IF-EVL-NEXT: [[TMP29:%.*]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VP_OP_LOAD5]])178; IF-EVL-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[EVL_BASED_IV]]179; IF-EVL-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP29]], ptr align 4 [[TMP16]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])180; IF-EVL-NEXT: [[TMP18:%.*]] = zext i32 [[TMP9]] to i64181; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP18]], [[EVL_BASED_IV]]182; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP18]]183; IF-EVL-NEXT: [[TMP17:%.*]] = icmp eq i64 [[AVL_NEXT]], 0184; IF-EVL-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]185; IF-EVL: [[MIDDLE_BLOCK]]:186; IF-EVL-NEXT: br label %[[EXIT:.*]]187; IF-EVL: [[SCALAR_PH]]:188; IF-EVL-NEXT: br label %[[LOOP:.*]]189; IF-EVL: [[LOOP]]:190; IF-EVL-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[SCALAR_PH]] ]191; IF-EVL-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]192; IF-EVL-NEXT: [[TMP20:%.*]] = load i32, ptr [[GEP]], align 4193; IF-EVL-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[IV]]194; IF-EVL-NEXT: [[TMP21:%.*]] = load i32, ptr [[GEP3]], align 4195; IF-EVL-NEXT: [[DOT:%.*]] = tail call i32 @llvm.smin.i32(i32 [[TMP20]], i32 [[TMP21]])196; IF-EVL-NEXT: [[GEP11:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]197; IF-EVL-NEXT: store i32 [[DOT]], ptr [[GEP11]], align 4198; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1199; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]200; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]201; IF-EVL: [[EXIT]]:202; IF-EVL-NEXT: ret void203;204; NO-VP-LABEL: define void @vp_smin(205; NO-VP-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {206; NO-VP-NEXT: [[ENTRY:.*]]:207; NO-VP-NEXT: [[C3:%.*]] = ptrtoint ptr [[C]] to i64208; NO-VP-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64209; NO-VP-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64210; NO-VP-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()211; NO-VP-NEXT: [[TMP11:%.*]] = shl nuw i64 [[TMP12]], 2212; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP11]], i64 16)213; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP2]]214; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]215; NO-VP: [[VECTOR_MEMCHECK]]:216; NO-VP-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()217; NO-VP-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 4218; NO-VP-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4219; NO-VP-NEXT: [[TMP6:%.*]] = sub i64 [[A1]], [[B2]]220; NO-VP-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]221; NO-VP-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 4222; NO-VP-NEXT: [[TMP8:%.*]] = sub i64 [[A1]], [[C3]]223; NO-VP-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP8]], [[TMP7]]224; NO-VP-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]225; NO-VP-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]226; NO-VP: [[VECTOR_PH]]:227; NO-VP-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()228; NO-VP-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 4229; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP10]]230; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]231; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]232; NO-VP: [[VECTOR_BODY]]:233; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]234; NO-VP-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]235; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP13]], align 4236; NO-VP-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[INDEX]]237; NO-VP-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 4 x i32>, ptr [[TMP14]], align 4238; NO-VP-NEXT: [[TMP15:%.*]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[WIDE_LOAD5]])239; NO-VP-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]240; NO-VP-NEXT: store <vscale x 4 x i32> [[TMP15]], ptr [[TMP16]], align 4241; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP10]]242; NO-VP-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]243; NO-VP-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]244; NO-VP: [[MIDDLE_BLOCK]]:245; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]246; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]247; NO-VP: [[SCALAR_PH]]:248; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]249; NO-VP-NEXT: br label %[[LOOP:.*]]250; NO-VP: [[LOOP]]:251; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]252; NO-VP-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]253; NO-VP-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP]], align 4254; NO-VP-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[IV]]255; NO-VP-NEXT: [[TMP1:%.*]] = load i32, ptr [[GEP3]], align 4256; NO-VP-NEXT: [[DOT:%.*]] = tail call i32 @llvm.smin.i32(i32 [[TMP0]], i32 [[TMP1]])257; NO-VP-NEXT: [[GEP11:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]258; NO-VP-NEXT: store i32 [[DOT]], ptr [[GEP11]], align 4259; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1260; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]261; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]262; NO-VP: [[EXIT]]:263; NO-VP-NEXT: ret void264;265 266entry:267 br label %loop268 269loop:270 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]271 %gep = getelementptr inbounds i32, ptr %b, i64 %iv272 %0 = load i32, ptr %gep, align 4273 %gep3 = getelementptr inbounds i32, ptr %c, i64 %iv274 %1 = load i32, ptr %gep3, align 4275 %. = tail call i32 @llvm.smin.i32(i32 %0, i32 %1)276 %gep11 = getelementptr inbounds i32, ptr %a, i64 %iv277 store i32 %., ptr %gep11, align 4278 %iv.next = add nuw nsw i64 %iv, 1279 %exitcond.not = icmp eq i64 %iv.next, %N280 br i1 %exitcond.not, label %exit, label %loop281 282exit:283 ret void284}285 286define void @vp_umax(ptr %a, ptr %b, ptr %c, i64 %N) {287; IF-EVL-LABEL: define void @vp_umax(288; IF-EVL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {289; IF-EVL-NEXT: [[ENTRY:.*:]]290; IF-EVL-NEXT: [[C3:%.*]] = ptrtoint ptr [[C]] to i64291; IF-EVL-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64292; IF-EVL-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64293; IF-EVL-NEXT: br label %[[VECTOR_MEMCHECK:.*]]294; IF-EVL: [[VECTOR_MEMCHECK]]:295; IF-EVL-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()296; IF-EVL-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4297; IF-EVL-NEXT: [[TMP23:%.*]] = mul i64 [[TMP5]], 4298; IF-EVL-NEXT: [[TMP24:%.*]] = sub i64 [[A1]], [[B2]]299; IF-EVL-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP24]], [[TMP23]]300; IF-EVL-NEXT: [[TMP25:%.*]] = mul i64 [[TMP5]], 4301; IF-EVL-NEXT: [[TMP26:%.*]] = sub i64 [[A1]], [[C3]]302; IF-EVL-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP26]], [[TMP25]]303; IF-EVL-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]304; IF-EVL-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]305; IF-EVL: [[VECTOR_PH]]:306; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]307; IF-EVL: [[VECTOR_BODY]]:308; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]309; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]310; IF-EVL-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)311; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[EVL_BASED_IV]]312; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])313; IF-EVL-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[EVL_BASED_IV]]314; IF-EVL-NEXT: [[VP_OP_LOAD5:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP13]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])315; IF-EVL-NEXT: [[TMP29:%.*]] = call <vscale x 4 x i32> @llvm.umax.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VP_OP_LOAD5]])316; IF-EVL-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[EVL_BASED_IV]]317; IF-EVL-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP29]], ptr align 4 [[TMP16]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])318; IF-EVL-NEXT: [[TMP18:%.*]] = zext i32 [[TMP9]] to i64319; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP18]], [[EVL_BASED_IV]]320; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP18]]321; IF-EVL-NEXT: [[TMP17:%.*]] = icmp eq i64 [[AVL_NEXT]], 0322; IF-EVL-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]323; IF-EVL: [[MIDDLE_BLOCK]]:324; IF-EVL-NEXT: br label %[[EXIT:.*]]325; IF-EVL: [[SCALAR_PH]]:326; IF-EVL-NEXT: br label %[[LOOP:.*]]327; IF-EVL: [[LOOP]]:328; IF-EVL-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[SCALAR_PH]] ]329; IF-EVL-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]330; IF-EVL-NEXT: [[TMP20:%.*]] = load i32, ptr [[GEP]], align 4331; IF-EVL-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[IV]]332; IF-EVL-NEXT: [[TMP21:%.*]] = load i32, ptr [[GEP3]], align 4333; IF-EVL-NEXT: [[DOT:%.*]] = tail call i32 @llvm.umax.i32(i32 [[TMP20]], i32 [[TMP21]])334; IF-EVL-NEXT: [[GEP11:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]335; IF-EVL-NEXT: store i32 [[DOT]], ptr [[GEP11]], align 4336; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1337; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]338; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]339; IF-EVL: [[EXIT]]:340; IF-EVL-NEXT: ret void341;342; NO-VP-LABEL: define void @vp_umax(343; NO-VP-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {344; NO-VP-NEXT: [[ENTRY:.*]]:345; NO-VP-NEXT: [[C3:%.*]] = ptrtoint ptr [[C]] to i64346; NO-VP-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64347; NO-VP-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64348; NO-VP-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()349; NO-VP-NEXT: [[TMP11:%.*]] = shl nuw i64 [[TMP12]], 2350; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP11]], i64 16)351; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP2]]352; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]353; NO-VP: [[VECTOR_MEMCHECK]]:354; NO-VP-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()355; NO-VP-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 4356; NO-VP-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4357; NO-VP-NEXT: [[TMP6:%.*]] = sub i64 [[A1]], [[B2]]358; NO-VP-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]359; NO-VP-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 4360; NO-VP-NEXT: [[TMP8:%.*]] = sub i64 [[A1]], [[C3]]361; NO-VP-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP8]], [[TMP7]]362; NO-VP-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]363; NO-VP-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]364; NO-VP: [[VECTOR_PH]]:365; NO-VP-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()366; NO-VP-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 4367; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP10]]368; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]369; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]370; NO-VP: [[VECTOR_BODY]]:371; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]372; NO-VP-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]373; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP13]], align 4374; NO-VP-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[INDEX]]375; NO-VP-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 4 x i32>, ptr [[TMP14]], align 4376; NO-VP-NEXT: [[TMP15:%.*]] = call <vscale x 4 x i32> @llvm.umax.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[WIDE_LOAD5]])377; NO-VP-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]378; NO-VP-NEXT: store <vscale x 4 x i32> [[TMP15]], ptr [[TMP16]], align 4379; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP10]]380; NO-VP-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]381; NO-VP-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]382; NO-VP: [[MIDDLE_BLOCK]]:383; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]384; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]385; NO-VP: [[SCALAR_PH]]:386; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]387; NO-VP-NEXT: br label %[[LOOP:.*]]388; NO-VP: [[LOOP]]:389; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]390; NO-VP-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]391; NO-VP-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP]], align 4392; NO-VP-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[IV]]393; NO-VP-NEXT: [[TMP1:%.*]] = load i32, ptr [[GEP3]], align 4394; NO-VP-NEXT: [[DOT:%.*]] = tail call i32 @llvm.umax.i32(i32 [[TMP0]], i32 [[TMP1]])395; NO-VP-NEXT: [[GEP11:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]396; NO-VP-NEXT: store i32 [[DOT]], ptr [[GEP11]], align 4397; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1398; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]399; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]400; NO-VP: [[EXIT]]:401; NO-VP-NEXT: ret void402;403 404entry:405 br label %loop406 407loop:408 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]409 %gep = getelementptr inbounds i32, ptr %b, i64 %iv410 %0 = load i32, ptr %gep, align 4411 %gep3 = getelementptr inbounds i32, ptr %c, i64 %iv412 %1 = load i32, ptr %gep3, align 4413 %. = tail call i32 @llvm.umax.i32(i32 %0, i32 %1)414 %gep11 = getelementptr inbounds i32, ptr %a, i64 %iv415 store i32 %., ptr %gep11, align 4416 %iv.next = add nuw nsw i64 %iv, 1417 %exitcond.not = icmp eq i64 %iv.next, %N418 br i1 %exitcond.not, label %exit, label %loop419 420exit:421 ret void422}423 424define void @vp_umin(ptr %a, ptr %b, ptr %c, i64 %N) {425; IF-EVL-LABEL: define void @vp_umin(426; IF-EVL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {427; IF-EVL-NEXT: [[ENTRY:.*:]]428; IF-EVL-NEXT: [[C3:%.*]] = ptrtoint ptr [[C]] to i64429; IF-EVL-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64430; IF-EVL-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64431; IF-EVL-NEXT: br label %[[VECTOR_MEMCHECK:.*]]432; IF-EVL: [[VECTOR_MEMCHECK]]:433; IF-EVL-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()434; IF-EVL-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4435; IF-EVL-NEXT: [[TMP23:%.*]] = mul i64 [[TMP5]], 4436; IF-EVL-NEXT: [[TMP24:%.*]] = sub i64 [[A1]], [[B2]]437; IF-EVL-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP24]], [[TMP23]]438; IF-EVL-NEXT: [[TMP25:%.*]] = mul i64 [[TMP5]], 4439; IF-EVL-NEXT: [[TMP26:%.*]] = sub i64 [[A1]], [[C3]]440; IF-EVL-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP26]], [[TMP25]]441; IF-EVL-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]442; IF-EVL-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]443; IF-EVL: [[VECTOR_PH]]:444; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]445; IF-EVL: [[VECTOR_BODY]]:446; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]447; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]448; IF-EVL-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)449; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[EVL_BASED_IV]]450; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])451; IF-EVL-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[EVL_BASED_IV]]452; IF-EVL-NEXT: [[VP_OP_LOAD5:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP13]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])453; IF-EVL-NEXT: [[TMP29:%.*]] = call <vscale x 4 x i32> @llvm.umin.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VP_OP_LOAD5]])454; IF-EVL-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[EVL_BASED_IV]]455; IF-EVL-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP29]], ptr align 4 [[TMP16]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])456; IF-EVL-NEXT: [[TMP18:%.*]] = zext i32 [[TMP9]] to i64457; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP18]], [[EVL_BASED_IV]]458; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP18]]459; IF-EVL-NEXT: [[TMP17:%.*]] = icmp eq i64 [[AVL_NEXT]], 0460; IF-EVL-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]461; IF-EVL: [[MIDDLE_BLOCK]]:462; IF-EVL-NEXT: br label %[[EXIT:.*]]463; IF-EVL: [[SCALAR_PH]]:464; IF-EVL-NEXT: br label %[[LOOP:.*]]465; IF-EVL: [[LOOP]]:466; IF-EVL-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[SCALAR_PH]] ]467; IF-EVL-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]468; IF-EVL-NEXT: [[TMP20:%.*]] = load i32, ptr [[GEP]], align 4469; IF-EVL-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[IV]]470; IF-EVL-NEXT: [[TMP21:%.*]] = load i32, ptr [[GEP3]], align 4471; IF-EVL-NEXT: [[DOT:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP20]], i32 [[TMP21]])472; IF-EVL-NEXT: [[GEP11:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]473; IF-EVL-NEXT: store i32 [[DOT]], ptr [[GEP11]], align 4474; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1475; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]476; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]477; IF-EVL: [[EXIT]]:478; IF-EVL-NEXT: ret void479;480; NO-VP-LABEL: define void @vp_umin(481; NO-VP-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {482; NO-VP-NEXT: [[ENTRY:.*]]:483; NO-VP-NEXT: [[C3:%.*]] = ptrtoint ptr [[C]] to i64484; NO-VP-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64485; NO-VP-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64486; NO-VP-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()487; NO-VP-NEXT: [[TMP11:%.*]] = shl nuw i64 [[TMP12]], 2488; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP11]], i64 16)489; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP2]]490; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]491; NO-VP: [[VECTOR_MEMCHECK]]:492; NO-VP-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()493; NO-VP-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 4494; NO-VP-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4495; NO-VP-NEXT: [[TMP6:%.*]] = sub i64 [[A1]], [[B2]]496; NO-VP-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]497; NO-VP-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 4498; NO-VP-NEXT: [[TMP8:%.*]] = sub i64 [[A1]], [[C3]]499; NO-VP-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP8]], [[TMP7]]500; NO-VP-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]501; NO-VP-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]502; NO-VP: [[VECTOR_PH]]:503; NO-VP-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()504; NO-VP-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 4505; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP10]]506; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]507; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]508; NO-VP: [[VECTOR_BODY]]:509; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]510; NO-VP-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]511; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP13]], align 4512; NO-VP-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[INDEX]]513; NO-VP-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 4 x i32>, ptr [[TMP14]], align 4514; NO-VP-NEXT: [[TMP15:%.*]] = call <vscale x 4 x i32> @llvm.umin.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[WIDE_LOAD5]])515; NO-VP-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]516; NO-VP-NEXT: store <vscale x 4 x i32> [[TMP15]], ptr [[TMP16]], align 4517; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP10]]518; NO-VP-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]519; NO-VP-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]520; NO-VP: [[MIDDLE_BLOCK]]:521; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]522; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]523; NO-VP: [[SCALAR_PH]]:524; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]525; NO-VP-NEXT: br label %[[LOOP:.*]]526; NO-VP: [[LOOP]]:527; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]528; NO-VP-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]529; NO-VP-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP]], align 4530; NO-VP-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[IV]]531; NO-VP-NEXT: [[TMP1:%.*]] = load i32, ptr [[GEP3]], align 4532; NO-VP-NEXT: [[DOT:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP0]], i32 [[TMP1]])533; NO-VP-NEXT: [[GEP11:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]534; NO-VP-NEXT: store i32 [[DOT]], ptr [[GEP11]], align 4535; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1536; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]537; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]538; NO-VP: [[EXIT]]:539; NO-VP-NEXT: ret void540;541 542entry:543 br label %loop544 545loop:546 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]547 %gep = getelementptr inbounds i32, ptr %b, i64 %iv548 %0 = load i32, ptr %gep, align 4549 %gep3 = getelementptr inbounds i32, ptr %c, i64 %iv550 %1 = load i32, ptr %gep3, align 4551 %. = tail call i32 @llvm.umin.i32(i32 %0, i32 %1)552 %gep11 = getelementptr inbounds i32, ptr %a, i64 %iv553 store i32 %., ptr %gep11, align 4554 %iv.next = add nuw nsw i64 %iv, 1555 %exitcond.not = icmp eq i64 %iv.next, %N556 br i1 %exitcond.not, label %exit, label %loop557 558exit:559 ret void560}561 562 563define void @vp_ctlz(ptr %a, ptr %b, i64 %N) {564; IF-EVL-LABEL: define void @vp_ctlz(565; IF-EVL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {566; IF-EVL-NEXT: [[ENTRY:.*:]]567; IF-EVL-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64568; IF-EVL-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64569; IF-EVL-NEXT: br label %[[VECTOR_MEMCHECK:.*]]570; IF-EVL: [[VECTOR_MEMCHECK]]:571; IF-EVL-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()572; IF-EVL-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4573; IF-EVL-NEXT: [[TMP20:%.*]] = mul i64 [[TMP5]], 4574; IF-EVL-NEXT: [[TMP21:%.*]] = sub i64 [[A1]], [[B2]]575; IF-EVL-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP21]], [[TMP20]]576; IF-EVL-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]577; IF-EVL: [[VECTOR_PH]]:578; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]579; IF-EVL: [[VECTOR_BODY]]:580; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]581; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]582; IF-EVL-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)583; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[EVL_BASED_IV]]584; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])585; IF-EVL-NEXT: [[TMP24:%.*]] = call <vscale x 4 x i32> @llvm.ctlz.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], i1 true)586; IF-EVL-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[EVL_BASED_IV]]587; IF-EVL-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP24]], ptr align 4 [[TMP14]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])588; IF-EVL-NEXT: [[TMP16:%.*]] = zext i32 [[TMP9]] to i64589; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]590; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP16]]591; IF-EVL-NEXT: [[TMP15:%.*]] = icmp eq i64 [[AVL_NEXT]], 0592; IF-EVL-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]593; IF-EVL: [[MIDDLE_BLOCK]]:594; IF-EVL-NEXT: br label %[[EXIT:.*]]595; IF-EVL: [[SCALAR_PH]]:596; IF-EVL-NEXT: br label %[[LOOP:.*]]597; IF-EVL: [[LOOP]]:598; IF-EVL-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[SCALAR_PH]] ]599; IF-EVL-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]600; IF-EVL-NEXT: [[TMP18:%.*]] = load i32, ptr [[GEP]], align 4601; IF-EVL-NEXT: [[TMP19:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP18]], i1 true)602; IF-EVL-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]603; IF-EVL-NEXT: store i32 [[TMP19]], ptr [[GEP3]], align 4604; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1605; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]606; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]607; IF-EVL: [[EXIT]]:608; IF-EVL-NEXT: ret void609;610; NO-VP-LABEL: define void @vp_ctlz(611; NO-VP-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {612; NO-VP-NEXT: [[ENTRY:.*]]:613; NO-VP-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64614; NO-VP-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64615; NO-VP-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()616; NO-VP-NEXT: [[TMP9:%.*]] = shl nuw i64 [[TMP10]], 2617; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP9]], i64 8)618; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP2]]619; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]620; NO-VP: [[VECTOR_MEMCHECK]]:621; NO-VP-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()622; NO-VP-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 4623; NO-VP-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4624; NO-VP-NEXT: [[TMP6:%.*]] = sub i64 [[A1]], [[B2]]625; NO-VP-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]626; NO-VP-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]627; NO-VP: [[VECTOR_PH]]:628; NO-VP-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()629; NO-VP-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 4630; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP8]]631; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]632; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]633; NO-VP: [[VECTOR_BODY]]:634; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]635; NO-VP-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]636; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[GEP]], align 4637; NO-VP-NEXT: [[TMP12:%.*]] = call <vscale x 4 x i32> @llvm.ctlz.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], i1 true)638; NO-VP-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]639; NO-VP-NEXT: store <vscale x 4 x i32> [[TMP12]], ptr [[TMP13]], align 4640; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP8]]641; NO-VP-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]642; NO-VP-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]643; NO-VP: [[MIDDLE_BLOCK]]:644; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]645; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]646; NO-VP: [[SCALAR_PH]]:647; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]648; NO-VP-NEXT: br label %[[LOOP:.*]]649; NO-VP: [[LOOP]]:650; NO-VP-NEXT: [[IV1:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]651; NO-VP-NEXT: [[GEP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV1]]652; NO-VP-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP1]], align 4653; NO-VP-NEXT: [[TMP1:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 true)654; NO-VP-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]]655; NO-VP-NEXT: store i32 [[TMP1]], ptr [[GEP3]], align 4656; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1657; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]658; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]659; NO-VP: [[EXIT]]:660; NO-VP-NEXT: ret void661;662 663entry:664 br label %loop665 666loop:667 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]668 %gep = getelementptr inbounds i32, ptr %b, i64 %iv669 %0 = load i32, ptr %gep, align 4670 %1 = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 %0, i1 true)671 %gep3 = getelementptr inbounds i32, ptr %a, i64 %iv672 store i32 %1, ptr %gep3, align 4673 %iv.next = add nuw nsw i64 %iv, 1674 %exitcond.not = icmp eq i64 %iv.next, %N675 br i1 %exitcond.not, label %exit, label %loop676 677exit:678 ret void679}680 681define void @vp_cttz(ptr %a, ptr %b, i64 %N) {682; IF-EVL-LABEL: define void @vp_cttz(683; IF-EVL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {684; IF-EVL-NEXT: [[ENTRY:.*:]]685; IF-EVL-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64686; IF-EVL-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64687; IF-EVL-NEXT: br label %[[VECTOR_MEMCHECK:.*]]688; IF-EVL: [[VECTOR_MEMCHECK]]:689; IF-EVL-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()690; IF-EVL-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4691; IF-EVL-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 4692; IF-EVL-NEXT: [[TMP7:%.*]] = sub i64 [[A1]], [[B2]]693; IF-EVL-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP7]], [[TMP6]]694; IF-EVL-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]695; IF-EVL: [[VECTOR_PH]]:696; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]697; IF-EVL: [[VECTOR_BODY]]:698; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]699; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]700; IF-EVL-NEXT: [[TMP13:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)701; IF-EVL-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[EVL_BASED_IV]]702; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP15]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP13]])703; IF-EVL-NEXT: [[TMP17:%.*]] = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], i1 true)704; IF-EVL-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[EVL_BASED_IV]]705; IF-EVL-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP17]], ptr align 4 [[TMP18]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP13]])706; IF-EVL-NEXT: [[TMP20:%.*]] = zext i32 [[TMP13]] to i64707; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP20]], [[EVL_BASED_IV]]708; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP20]]709; IF-EVL-NEXT: [[TMP14:%.*]] = icmp eq i64 [[AVL_NEXT]], 0710; IF-EVL-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]711; IF-EVL: [[MIDDLE_BLOCK]]:712; IF-EVL-NEXT: br label %[[EXIT:.*]]713; IF-EVL: [[SCALAR_PH]]:714; IF-EVL-NEXT: br label %[[LOOP:.*]]715; IF-EVL: [[LOOP]]:716; IF-EVL-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[SCALAR_PH]] ]717; IF-EVL-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]718; IF-EVL-NEXT: [[TMP22:%.*]] = load i32, ptr [[GEP]], align 4719; IF-EVL-NEXT: [[TMP23:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[TMP22]], i1 true)720; IF-EVL-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]721; IF-EVL-NEXT: store i32 [[TMP23]], ptr [[GEP3]], align 4722; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1723; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]724; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]]725; IF-EVL: [[EXIT]]:726; IF-EVL-NEXT: ret void727;728; NO-VP-LABEL: define void @vp_cttz(729; NO-VP-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {730; NO-VP-NEXT: [[ENTRY:.*]]:731; NO-VP-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64732; NO-VP-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64733; NO-VP-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()734; NO-VP-NEXT: [[TMP9:%.*]] = shl nuw i64 [[TMP10]], 2735; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP9]], i64 8)736; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP2]]737; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]738; NO-VP: [[VECTOR_MEMCHECK]]:739; NO-VP-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()740; NO-VP-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 4741; NO-VP-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4742; NO-VP-NEXT: [[TMP6:%.*]] = sub i64 [[A1]], [[B2]]743; NO-VP-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]744; NO-VP-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]745; NO-VP: [[VECTOR_PH]]:746; NO-VP-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()747; NO-VP-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 4748; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP8]]749; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]750; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]751; NO-VP: [[VECTOR_BODY]]:752; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]753; NO-VP-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]754; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[GEP]], align 4755; NO-VP-NEXT: [[TMP12:%.*]] = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], i1 true)756; NO-VP-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]757; NO-VP-NEXT: store <vscale x 4 x i32> [[TMP12]], ptr [[TMP13]], align 4758; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP8]]759; NO-VP-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]760; NO-VP-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]761; NO-VP: [[MIDDLE_BLOCK]]:762; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]763; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]764; NO-VP: [[SCALAR_PH]]:765; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]766; NO-VP-NEXT: br label %[[LOOP:.*]]767; NO-VP: [[LOOP]]:768; NO-VP-NEXT: [[IV1:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]769; NO-VP-NEXT: [[GEP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV1]]770; NO-VP-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP1]], align 4771; NO-VP-NEXT: [[TMP1:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[TMP0]], i1 true)772; NO-VP-NEXT: [[GEP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]]773; NO-VP-NEXT: store i32 [[TMP1]], ptr [[GEP3]], align 4774; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1775; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]776; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]]777; NO-VP: [[EXIT]]:778; NO-VP-NEXT: ret void779;780 781entry:782 br label %loop783 784loop:785 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]786 %gep = getelementptr inbounds i32, ptr %b, i64 %iv787 %0 = load i32, ptr %gep, align 4788 %1 = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 %0, i1 true)789 %gep3 = getelementptr inbounds i32, ptr %a, i64 %iv790 store i32 %1, ptr %gep3, align 4791 %iv.next = add nuw nsw i64 %iv, 1792 %exitcond.not = icmp eq i64 %iv.next, %N793 br i1 %exitcond.not, label %exit, label %loop794 795exit:796 ret void797}798 799define void @vp_lrint(ptr %a, ptr %b, i64 %N) {800; IF-EVL-LABEL: define void @vp_lrint(801; IF-EVL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {802; IF-EVL-NEXT: [[ENTRY:.*:]]803; IF-EVL-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64804; IF-EVL-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64805; IF-EVL-NEXT: br label %[[VECTOR_MEMCHECK:.*]]806; IF-EVL: [[VECTOR_MEMCHECK]]:807; IF-EVL-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()808; IF-EVL-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4809; IF-EVL-NEXT: [[TMP23:%.*]] = mul i64 [[TMP5]], 4810; IF-EVL-NEXT: [[TMP24:%.*]] = sub i64 [[A1]], [[B2]]811; IF-EVL-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP24]], [[TMP23]]812; IF-EVL-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]813; IF-EVL: [[VECTOR_PH]]:814; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]815; IF-EVL: [[VECTOR_BODY]]:816; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]817; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]818; IF-EVL-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)819; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[EVL_BASED_IV]]820; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])821; IF-EVL-NEXT: [[TMP27:%.*]] = fpext <vscale x 4 x float> [[VP_OP_LOAD]] to <vscale x 4 x double>822; IF-EVL-NEXT: [[TMP28:%.*]] = call <vscale x 4 x i64> @llvm.lrint.nxv4i64.nxv4f64(<vscale x 4 x double> [[TMP27]])823; IF-EVL-NEXT: [[TMP15:%.*]] = trunc <vscale x 4 x i64> [[TMP28]] to <vscale x 4 x i32>824; IF-EVL-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[EVL_BASED_IV]]825; IF-EVL-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP15]], ptr align 4 [[TMP16]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])826; IF-EVL-NEXT: [[TMP18:%.*]] = zext i32 [[TMP9]] to i64827; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP18]], [[EVL_BASED_IV]]828; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP18]]829; IF-EVL-NEXT: [[TMP17:%.*]] = icmp eq i64 [[AVL_NEXT]], 0830; IF-EVL-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]831; IF-EVL: [[MIDDLE_BLOCK]]:832; IF-EVL-NEXT: br label %[[EXIT:.*]]833; IF-EVL: [[SCALAR_PH]]:834; IF-EVL-NEXT: br label %[[LOOP:.*]]835; IF-EVL: [[LOOP]]:836; IF-EVL-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[SCALAR_PH]] ]837; IF-EVL-NEXT: [[GEP:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]838; IF-EVL-NEXT: [[TMP20:%.*]] = load float, ptr [[GEP]], align 4839; IF-EVL-NEXT: [[CONV2:%.*]] = fpext float [[TMP20]] to double840; IF-EVL-NEXT: [[TMP21:%.*]] = tail call i64 @llvm.lrint.i64.f64(double [[CONV2]])841; IF-EVL-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP21]] to i32842; IF-EVL-NEXT: [[GEP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]843; IF-EVL-NEXT: store i32 [[CONV3]], ptr [[GEP5]], align 4844; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1845; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]846; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP15:![0-9]+]]847; IF-EVL: [[EXIT]]:848; IF-EVL-NEXT: ret void849;850; NO-VP-LABEL: define void @vp_lrint(851; NO-VP-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {852; NO-VP-NEXT: [[ENTRY:.*]]:853; NO-VP-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64854; NO-VP-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64855; NO-VP-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()856; NO-VP-NEXT: [[TMP9:%.*]] = shl nuw i64 [[TMP10]], 2857; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP9]], i64 16)858; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP2]]859; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]860; NO-VP: [[VECTOR_MEMCHECK]]:861; NO-VP-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()862; NO-VP-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 4863; NO-VP-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4864; NO-VP-NEXT: [[TMP6:%.*]] = sub i64 [[A1]], [[B2]]865; NO-VP-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]866; NO-VP-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]867; NO-VP: [[VECTOR_PH]]:868; NO-VP-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()869; NO-VP-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 4870; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP8]]871; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]872; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]873; NO-VP: [[VECTOR_BODY]]:874; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]875; NO-VP-NEXT: [[GEP:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]876; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[GEP]], align 4877; NO-VP-NEXT: [[TMP12:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD]] to <vscale x 4 x double>878; NO-VP-NEXT: [[TMP13:%.*]] = call <vscale x 4 x i64> @llvm.lrint.nxv4i64.nxv4f64(<vscale x 4 x double> [[TMP12]])879; NO-VP-NEXT: [[TMP14:%.*]] = trunc <vscale x 4 x i64> [[TMP13]] to <vscale x 4 x i32>880; NO-VP-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]881; NO-VP-NEXT: store <vscale x 4 x i32> [[TMP14]], ptr [[TMP15]], align 4882; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP8]]883; NO-VP-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]884; NO-VP-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]885; NO-VP: [[MIDDLE_BLOCK]]:886; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]887; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]888; NO-VP: [[SCALAR_PH]]:889; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]890; NO-VP-NEXT: br label %[[LOOP:.*]]891; NO-VP: [[LOOP]]:892; NO-VP-NEXT: [[IV1:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]893; NO-VP-NEXT: [[GEP1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV1]]894; NO-VP-NEXT: [[TMP0:%.*]] = load float, ptr [[GEP1]], align 4895; NO-VP-NEXT: [[CONV2:%.*]] = fpext float [[TMP0]] to double896; NO-VP-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.lrint.i64.f64(double [[CONV2]])897; NO-VP-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP1]] to i32898; NO-VP-NEXT: [[GEP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]]899; NO-VP-NEXT: store i32 [[CONV3]], ptr [[GEP5]], align 4900; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1901; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]902; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP15:![0-9]+]]903; NO-VP: [[EXIT]]:904; NO-VP-NEXT: ret void905;906 907entry:908 br label %loop909 910loop:911 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]912 %gep = getelementptr inbounds float, ptr %b, i64 %iv913 %0 = load float, ptr %gep, align 4914 %conv2 = fpext float %0 to double915 %1 = tail call i64 @llvm.lrint.i64.f64(double %conv2)916 %conv3 = trunc i64 %1 to i32917 %gep5 = getelementptr inbounds i32, ptr %a, i64 %iv918 store i32 %conv3, ptr %gep5, align 4919 %iv.next = add nuw nsw i64 %iv, 1920 %exitcond.not = icmp eq i64 %iv.next, %N921 br i1 %exitcond.not, label %exit, label %loop922 923exit:924 ret void925}926 927define void @vp_llrint(ptr %a, ptr %b, i64 %N) {928; IF-EVL-LABEL: define void @vp_llrint(929; IF-EVL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {930; IF-EVL-NEXT: [[ENTRY:.*:]]931; IF-EVL-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64932; IF-EVL-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64933; IF-EVL-NEXT: br label %[[VECTOR_MEMCHECK:.*]]934; IF-EVL: [[VECTOR_MEMCHECK]]:935; IF-EVL-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()936; IF-EVL-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4937; IF-EVL-NEXT: [[TMP23:%.*]] = mul i64 [[TMP5]], 4938; IF-EVL-NEXT: [[TMP24:%.*]] = sub i64 [[A1]], [[B2]]939; IF-EVL-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP24]], [[TMP23]]940; IF-EVL-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]941; IF-EVL: [[VECTOR_PH]]:942; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]943; IF-EVL: [[VECTOR_BODY]]:944; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]945; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]946; IF-EVL-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)947; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[EVL_BASED_IV]]948; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])949; IF-EVL-NEXT: [[TMP27:%.*]] = fpext <vscale x 4 x float> [[VP_OP_LOAD]] to <vscale x 4 x double>950; IF-EVL-NEXT: [[TMP28:%.*]] = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f64(<vscale x 4 x double> [[TMP27]])951; IF-EVL-NEXT: [[TMP15:%.*]] = trunc <vscale x 4 x i64> [[TMP28]] to <vscale x 4 x i32>952; IF-EVL-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[EVL_BASED_IV]]953; IF-EVL-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP15]], ptr align 4 [[TMP16]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])954; IF-EVL-NEXT: [[TMP18:%.*]] = zext i32 [[TMP9]] to i64955; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP18]], [[EVL_BASED_IV]]956; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP18]]957; IF-EVL-NEXT: [[TMP17:%.*]] = icmp eq i64 [[AVL_NEXT]], 0958; IF-EVL-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]959; IF-EVL: [[MIDDLE_BLOCK]]:960; IF-EVL-NEXT: br label %[[EXIT:.*]]961; IF-EVL: [[SCALAR_PH]]:962; IF-EVL-NEXT: br label %[[LOOP:.*]]963; IF-EVL: [[LOOP]]:964; IF-EVL-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[SCALAR_PH]] ]965; IF-EVL-NEXT: [[GEP:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]966; IF-EVL-NEXT: [[TMP20:%.*]] = load float, ptr [[GEP]], align 4967; IF-EVL-NEXT: [[CONV2:%.*]] = fpext float [[TMP20]] to double968; IF-EVL-NEXT: [[TMP21:%.*]] = tail call i64 @llvm.llrint.i64.f64(double [[CONV2]])969; IF-EVL-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP21]] to i32970; IF-EVL-NEXT: [[GEP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]971; IF-EVL-NEXT: store i32 [[CONV3]], ptr [[GEP5]], align 4972; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1973; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]974; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP17:![0-9]+]]975; IF-EVL: [[EXIT]]:976; IF-EVL-NEXT: ret void977;978; NO-VP-LABEL: define void @vp_llrint(979; NO-VP-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {980; NO-VP-NEXT: [[ENTRY:.*]]:981; NO-VP-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i64982; NO-VP-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64983; NO-VP-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()984; NO-VP-NEXT: [[TMP9:%.*]] = shl nuw i64 [[TMP10]], 2985; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP9]], i64 16)986; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP2]]987; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]988; NO-VP: [[VECTOR_MEMCHECK]]:989; NO-VP-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()990; NO-VP-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 4991; NO-VP-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4992; NO-VP-NEXT: [[TMP6:%.*]] = sub i64 [[A1]], [[B2]]993; NO-VP-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]994; NO-VP-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]995; NO-VP: [[VECTOR_PH]]:996; NO-VP-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()997; NO-VP-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 4998; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP8]]999; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]1000; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]1001; NO-VP: [[VECTOR_BODY]]:1002; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1003; NO-VP-NEXT: [[GEP:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]1004; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[GEP]], align 41005; NO-VP-NEXT: [[TMP12:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD]] to <vscale x 4 x double>1006; NO-VP-NEXT: [[TMP13:%.*]] = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f64(<vscale x 4 x double> [[TMP12]])1007; NO-VP-NEXT: [[TMP14:%.*]] = trunc <vscale x 4 x i64> [[TMP13]] to <vscale x 4 x i32>1008; NO-VP-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]1009; NO-VP-NEXT: store <vscale x 4 x i32> [[TMP14]], ptr [[TMP15]], align 41010; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP8]]1011; NO-VP-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]1012; NO-VP-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]1013; NO-VP: [[MIDDLE_BLOCK]]:1014; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]1015; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]1016; NO-VP: [[SCALAR_PH]]:1017; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]1018; NO-VP-NEXT: br label %[[LOOP:.*]]1019; NO-VP: [[LOOP]]:1020; NO-VP-NEXT: [[IV1:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]1021; NO-VP-NEXT: [[GEP1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV1]]1022; NO-VP-NEXT: [[TMP0:%.*]] = load float, ptr [[GEP1]], align 41023; NO-VP-NEXT: [[CONV2:%.*]] = fpext float [[TMP0]] to double1024; NO-VP-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.llrint.i64.f64(double [[CONV2]])1025; NO-VP-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP1]] to i321026; NO-VP-NEXT: [[GEP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]]1027; NO-VP-NEXT: store i32 [[CONV3]], ptr [[GEP5]], align 41028; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 11029; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]1030; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP17:![0-9]+]]1031; NO-VP: [[EXIT]]:1032; NO-VP-NEXT: ret void1033;1034 1035entry:1036 br label %loop1037 1038loop:1039 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]1040 %gep = getelementptr inbounds float, ptr %b, i64 %iv1041 %0 = load float, ptr %gep, align 41042 %conv2 = fpext float %0 to double1043 %1 = tail call i64 @llvm.llrint.i64.f64(double %conv2)1044 %conv3 = trunc i64 %1 to i321045 %gep5 = getelementptr inbounds i32, ptr %a, i64 %iv1046 store i32 %conv3, ptr %gep5, align 41047 %iv.next = add nuw nsw i64 %iv, 11048 %exitcond.not = icmp eq i64 %iv.next, %N1049 br i1 %exitcond.not, label %exit, label %loop1050 1051exit:1052 ret void1053}1054 1055define void @vp_abs(ptr %a, ptr %b, i64 %N) {1056; IF-EVL-LABEL: define void @vp_abs(1057; IF-EVL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {1058; IF-EVL-NEXT: [[ENTRY:.*:]]1059; IF-EVL-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i641060; IF-EVL-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i641061; IF-EVL-NEXT: br label %[[VECTOR_MEMCHECK:.*]]1062; IF-EVL: [[VECTOR_MEMCHECK]]:1063; IF-EVL-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()1064; IF-EVL-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 41065; IF-EVL-NEXT: [[TMP20:%.*]] = mul i64 [[TMP5]], 41066; IF-EVL-NEXT: [[TMP21:%.*]] = sub i64 [[A1]], [[B2]]1067; IF-EVL-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP21]], [[TMP20]]1068; IF-EVL-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]1069; IF-EVL: [[VECTOR_PH]]:1070; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]1071; IF-EVL: [[VECTOR_BODY]]:1072; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]1073; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]1074; IF-EVL-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)1075; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[EVL_BASED_IV]]1076; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])1077; IF-EVL-NEXT: [[TMP24:%.*]] = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], i1 true)1078; IF-EVL-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[EVL_BASED_IV]]1079; IF-EVL-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP24]], ptr align 4 [[TMP14]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])1080; IF-EVL-NEXT: [[TMP16:%.*]] = zext i32 [[TMP9]] to i641081; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]1082; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP16]]1083; IF-EVL-NEXT: [[TMP15:%.*]] = icmp eq i64 [[AVL_NEXT]], 01084; IF-EVL-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]1085; IF-EVL: [[MIDDLE_BLOCK]]:1086; IF-EVL-NEXT: br label %[[EXIT:.*]]1087; IF-EVL: [[SCALAR_PH]]:1088; IF-EVL-NEXT: br label %[[LOOP:.*]]1089; IF-EVL: [[LOOP]]:1090; IF-EVL-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[SCALAR_PH]] ]1091; IF-EVL-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]1092; IF-EVL-NEXT: [[TMP18:%.*]] = load i32, ptr [[GEP]], align 41093; IF-EVL-NEXT: [[COND:%.*]] = tail call i32 @llvm.abs.i32(i32 [[TMP18]], i1 true)1094; IF-EVL-NEXT: [[GEP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]1095; IF-EVL-NEXT: store i32 [[COND]], ptr [[GEP9]], align 41096; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11097; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]1098; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP19:![0-9]+]]1099; IF-EVL: [[EXIT]]:1100; IF-EVL-NEXT: ret void1101;1102; NO-VP-LABEL: define void @vp_abs(1103; NO-VP-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {1104; NO-VP-NEXT: [[ENTRY:.*]]:1105; NO-VP-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i641106; NO-VP-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i641107; NO-VP-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()1108; NO-VP-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP9]], 21109; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP1]], i64 8)1110; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP2]]1111; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]1112; NO-VP: [[VECTOR_MEMCHECK]]:1113; NO-VP-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1114; NO-VP-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 41115; NO-VP-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 41116; NO-VP-NEXT: [[TMP6:%.*]] = sub i64 [[A1]], [[B2]]1117; NO-VP-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]1118; NO-VP-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]1119; NO-VP: [[VECTOR_PH]]:1120; NO-VP-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()1121; NO-VP-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 41122; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP8]]1123; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]1124; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]1125; NO-VP: [[VECTOR_BODY]]:1126; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1127; NO-VP-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]1128; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[GEP]], align 41129; NO-VP-NEXT: [[TMP12:%.*]] = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], i1 true)1130; NO-VP-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]1131; NO-VP-NEXT: store <vscale x 4 x i32> [[TMP12]], ptr [[TMP13]], align 41132; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP8]]1133; NO-VP-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]1134; NO-VP-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]1135; NO-VP: [[MIDDLE_BLOCK]]:1136; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]1137; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]1138; NO-VP: [[SCALAR_PH]]:1139; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]1140; NO-VP-NEXT: br label %[[LOOP:.*]]1141; NO-VP: [[LOOP]]:1142; NO-VP-NEXT: [[IV1:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]1143; NO-VP-NEXT: [[GEP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV1]]1144; NO-VP-NEXT: [[TMP0:%.*]] = load i32, ptr [[GEP1]], align 41145; NO-VP-NEXT: [[COND:%.*]] = tail call i32 @llvm.abs.i32(i32 [[TMP0]], i1 true)1146; NO-VP-NEXT: [[GEP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]]1147; NO-VP-NEXT: store i32 [[COND]], ptr [[GEP9]], align 41148; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 11149; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]1150; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP19:![0-9]+]]1151; NO-VP: [[EXIT]]:1152; NO-VP-NEXT: ret void1153;1154 1155entry:1156 br label %loop1157 1158loop:1159 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]1160 %gep = getelementptr inbounds i32, ptr %b, i64 %iv1161 %0 = load i32, ptr %gep, align 41162 %cond = tail call i32 @llvm.abs.i32(i32 %0, i1 true)1163 %gep9 = getelementptr inbounds i32, ptr %a, i64 %iv1164 store i32 %cond, ptr %gep9, align 41165 %iv.next = add nuw nsw i64 %iv, 11166 %exitcond.not = icmp eq i64 %iv.next, %N1167 br i1 %exitcond.not, label %exit, label %loop1168 1169exit:1170 ret void1171}1172 1173; There's no @llvm.vp.log10, so don't transform it.1174define void @log10(ptr %a, ptr %b, i64 %N) {1175; IF-EVL-LABEL: define void @log10(1176; IF-EVL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {1177; IF-EVL-NEXT: [[ENTRY:.*]]:1178; IF-EVL-NEXT: br label %[[LOOP:.*]]1179; IF-EVL: [[LOOP]]:1180; IF-EVL-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]1181; IF-EVL-NEXT: [[GEP:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]1182; IF-EVL-NEXT: [[TMP0:%.*]] = load float, ptr [[GEP]], align 41183; IF-EVL-NEXT: [[COND:%.*]] = tail call float @llvm.log10.f32(float [[TMP0]])1184; IF-EVL-NEXT: [[GEP9:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]]1185; IF-EVL-NEXT: store float [[COND]], ptr [[GEP9]], align 41186; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11187; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]1188; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]1189; IF-EVL: [[EXIT]]:1190; IF-EVL-NEXT: ret void1191;1192; NO-VP-LABEL: define void @log10(1193; NO-VP-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {1194; NO-VP-NEXT: [[ENTRY:.*]]:1195; NO-VP-NEXT: [[B2:%.*]] = ptrtoint ptr [[B]] to i641196; NO-VP-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i641197; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 81198; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]1199; NO-VP: [[VECTOR_MEMCHECK]]:1200; NO-VP-NEXT: [[TMP1:%.*]] = sub i64 [[A1]], [[B2]]1201; NO-VP-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP1]], 161202; NO-VP-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]1203; NO-VP: [[VECTOR_PH]]:1204; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 41205; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]1206; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]1207; NO-VP: [[VECTOR_BODY]]:1208; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1209; NO-VP-NEXT: [[GEP:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]1210; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[GEP]], align 41211; NO-VP-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.log10.v4f32(<4 x float> [[WIDE_LOAD]])1212; NO-VP-NEXT: [[TMP3:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]]1213; NO-VP-NEXT: store <4 x float> [[TMP2]], ptr [[TMP3]], align 41214; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 41215; NO-VP-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]1216; NO-VP-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]1217; NO-VP: [[MIDDLE_BLOCK]]:1218; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]1219; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]1220; NO-VP: [[SCALAR_PH]]:1221; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]1222; NO-VP-NEXT: br label %[[LOOP:.*]]1223; NO-VP: [[LOOP]]:1224; NO-VP-NEXT: [[IV1:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]1225; NO-VP-NEXT: [[GEP1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV1]]1226; NO-VP-NEXT: [[TMP0:%.*]] = load float, ptr [[GEP1]], align 41227; NO-VP-NEXT: [[COND:%.*]] = tail call float @llvm.log10.f32(float [[TMP0]])1228; NO-VP-NEXT: [[GEP9:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV1]]1229; NO-VP-NEXT: store float [[COND]], ptr [[GEP9]], align 41230; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 11231; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]1232; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP21:![0-9]+]]1233; NO-VP: [[EXIT]]:1234; NO-VP-NEXT: ret void1235;1236 1237entry:1238 br label %loop1239 1240loop:1241 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]1242 %gep = getelementptr inbounds float, ptr %b, i64 %iv1243 %0 = load float, ptr %gep, align 41244 %cond = tail call float @llvm.log10.f32(float %0)1245 %gep9 = getelementptr inbounds float, ptr %a, i64 %iv1246 store float %cond, ptr %gep9, align 41247 %iv.next = add nuw nsw i64 %iv, 11248 %exitcond.not = icmp eq i64 %iv.next, %N1249 br i1 %exitcond.not, label %exit, label %loop1250 1251exit:1252 ret void1253}1254 1255 1256declare i32 @llvm.smax.i32(i32, i32)1257declare i32 @llvm.smin.i32(i32, i32)1258declare i32 @llvm.umax.i32(i32, i32)1259declare i32 @llvm.umin.i32(i32, i32)1260declare i32 @llvm.ctlz.i32(i32, i1 immarg)1261declare i32 @llvm.cttz.i32(i32, i1 immarg)1262declare i64 @llvm.lrint.i64.f64(double)1263declare i64 @llvm.llrint.i64.f64(double)1264declare i32 @llvm.abs.i32(i32, i1 immarg)1265;.1266; IF-EVL: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}1267; IF-EVL: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}1268; IF-EVL: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}1269; IF-EVL: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}1270; IF-EVL: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}1271; IF-EVL: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}1272; IF-EVL: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}1273; IF-EVL: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]}1274; IF-EVL: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}1275; IF-EVL: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]}1276; IF-EVL: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}1277; IF-EVL: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]]}1278; IF-EVL: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]}1279; IF-EVL: [[LOOP13]] = distinct !{[[LOOP13]], [[META1]]}1280; IF-EVL: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]], [[META2]]}1281; IF-EVL: [[LOOP15]] = distinct !{[[LOOP15]], [[META1]]}1282; IF-EVL: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]], [[META2]]}1283; IF-EVL: [[LOOP17]] = distinct !{[[LOOP17]], [[META1]]}1284; IF-EVL: [[LOOP18]] = distinct !{[[LOOP18]], [[META1]], [[META2]]}1285; IF-EVL: [[LOOP19]] = distinct !{[[LOOP19]], [[META1]]}1286;.1287; NO-VP: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}1288; NO-VP: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}1289; NO-VP: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}1290; NO-VP: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}1291; NO-VP: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}1292; NO-VP: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}1293; NO-VP: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}1294; NO-VP: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]}1295; NO-VP: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}1296; NO-VP: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]}1297; NO-VP: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}1298; NO-VP: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]]}1299; NO-VP: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]}1300; NO-VP: [[LOOP13]] = distinct !{[[LOOP13]], [[META1]]}1301; NO-VP: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]], [[META2]]}1302; NO-VP: [[LOOP15]] = distinct !{[[LOOP15]], [[META1]]}1303; NO-VP: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]], [[META2]]}1304; NO-VP: [[LOOP17]] = distinct !{[[LOOP17]], [[META1]]}1305; NO-VP: [[LOOP18]] = distinct !{[[LOOP18]], [[META1]], [[META2]]}1306; NO-VP: [[LOOP19]] = distinct !{[[LOOP19]], [[META1]]}1307; NO-VP: [[LOOP20]] = distinct !{[[LOOP20]], [[META1]], [[META2]]}1308; NO-VP: [[LOOP21]] = distinct !{[[LOOP21]], [[META1]]}1309;.1310