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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -passes=loop-vectorize \3; RUN: -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue \4; RUN: -mtriple=riscv64 -mattr=+v -S < %s | FileCheck %s5 6; TODO: We know the IV will never overflow here so we can skip the overflow7; check8 9define void @trip_count_max_1024(ptr %p, i64 %tc) vscale_range(2, 1024) {10; CHECK-LABEL: define void @trip_count_max_1024(11; CHECK-SAME: ptr [[P:%.*]], i64 [[TC:%.*]]) #[[ATTR0:[0-9]+]] {12; CHECK-NEXT: [[ENTRY:.*:]]13; CHECK-NEXT: [[GUARD:%.*]] = icmp ugt i64 [[TC]], 102414; CHECK-NEXT: br i1 [[GUARD]], label %[[EXIT:.*]], label %[[LOOP_PREHEADER:.*]]15; CHECK: [[LOOP_PREHEADER]]:16; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TC]], i64 1)17; CHECK-NEXT: br label %[[VECTOR_PH:.*]]18; CHECK: [[VECTOR_PH]]:19; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]20; CHECK: [[VECTOR_BODY]]:21; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]22; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[UMAX]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]23; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)24; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[P]], i64 [[EVL_BASED_IV]]25; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP11]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP9]])26; CHECK-NEXT: [[VP_OP:%.*]] = add <vscale x 2 x i64> [[VP_OP_LOAD]], splat (i64 1)27; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[VP_OP]], ptr align 8 [[TMP11]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP9]])28; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP9]] to i6429; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP13]], [[EVL_BASED_IV]]30; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP13]]31; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[AVL_NEXT]], 032; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]33; CHECK: [[MIDDLE_BLOCK]]:34; CHECK-NEXT: br label %[[EXIT_LOOPEXIT:.*]]35; CHECK: [[EXIT_LOOPEXIT]]:36; CHECK-NEXT: br label %[[EXIT]]37; CHECK: [[EXIT]]:38; CHECK-NEXT: ret void39;40entry:41 %guard = icmp ugt i64 %tc, 102442 br i1 %guard, label %exit, label %loop43loop:44 %i = phi i64 [%i.next, %loop], [0, %entry]45 %gep = getelementptr i64, ptr %p, i64 %i46 %x = load i64, ptr %gep47 %y = add i64 %x, 148 store i64 %y, ptr %gep49 %i.next = add i64 %i, 150 %done = icmp uge i64 %i.next, %tc51 br i1 %done, label %exit, label %loop52exit:53 ret void54}55 56; If %tc = 0 the IV will overflow, so we need to emit an overflow check57; FIXME: The check still allows %tc =058 59define void @overflow_at_0(ptr %p, i64 %tc) vscale_range(2, 1024) {60; CHECK-LABEL: define void @overflow_at_0(61; CHECK-SAME: ptr [[P:%.*]], i64 [[TC:%.*]]) #[[ATTR0]] {62; CHECK-NEXT: [[ENTRY:.*:]]63; CHECK-NEXT: [[GUARD:%.*]] = icmp ugt i64 [[TC]], 102464; CHECK-NEXT: br i1 [[GUARD]], label %[[EXIT:.*]], label %[[LOOP_PREHEADER:.*]]65; CHECK: [[LOOP_PREHEADER]]:66; CHECK-NEXT: br label %[[VECTOR_PH:.*]]67; CHECK: [[VECTOR_PH]]:68; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]69; CHECK: [[VECTOR_BODY]]:70; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]71; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TC]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]72; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)73; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[P]], i64 [[EVL_BASED_IV]]74; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP11]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP9]])75; CHECK-NEXT: [[VP_OP:%.*]] = add <vscale x 2 x i64> [[VP_OP_LOAD]], splat (i64 1)76; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[VP_OP]], ptr align 8 [[TMP11]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP9]])77; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP9]] to i6478; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP13]], [[EVL_BASED_IV]]79; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP13]]80; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[AVL_NEXT]], 081; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]82; CHECK: [[MIDDLE_BLOCK]]:83; CHECK-NEXT: br label %[[EXIT_LOOPEXIT:.*]]84; CHECK: [[EXIT_LOOPEXIT]]:85; CHECK-NEXT: br label %[[EXIT]]86; CHECK: [[EXIT]]:87; CHECK-NEXT: ret void88;89entry:90 %guard = icmp ugt i64 %tc, 102491 br i1 %guard, label %exit, label %loop92loop:93 %i = phi i64 [%i.next, %loop], [0, %entry]94 %gep = getelementptr i64, ptr %p, i64 %i95 %x = load i64, ptr %gep96 %y = add i64 %x, 197 store i64 %y, ptr %gep98 %i.next = add i64 %i, 199 %done = icmp eq i64 %i.next, %tc100 br i1 %done, label %exit, label %loop101exit:102 ret void103}104 105; %tc won't = 0 so the IV won't overflow106 107define void @no_overflow_at_0(ptr %p, i64 %tc) vscale_range(2, 1024) {108; CHECK-LABEL: define void @no_overflow_at_0(109; CHECK-SAME: ptr [[P:%.*]], i64 [[TC:%.*]]) #[[ATTR0]] {110; CHECK-NEXT: [[ENTRY:.*:]]111; CHECK-NEXT: [[TC_ADD:%.*]] = add i64 [[TC]], 1112; CHECK-NEXT: [[GUARD:%.*]] = icmp ugt i64 [[TC]], 1024113; CHECK-NEXT: br i1 [[GUARD]], label %[[EXIT:.*]], label %[[LOOP_PREHEADER:.*]]114; CHECK: [[LOOP_PREHEADER]]:115; CHECK-NEXT: br label %[[VECTOR_PH:.*]]116; CHECK: [[VECTOR_PH]]:117; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]118; CHECK: [[VECTOR_BODY]]:119; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]120; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TC_ADD]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]121; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)122; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[P]], i64 [[EVL_BASED_IV]]123; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP7]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP5]])124; CHECK-NEXT: [[VP_OP:%.*]] = add <vscale x 2 x i64> [[VP_OP_LOAD]], splat (i64 1)125; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[VP_OP]], ptr align 8 [[TMP7]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP5]])126; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP5]] to i64127; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP9]], [[EVL_BASED_IV]]128; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP9]]129; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[AVL_NEXT]], 0130; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]131; CHECK: [[MIDDLE_BLOCK]]:132; CHECK-NEXT: br label %[[EXIT_LOOPEXIT:.*]]133; CHECK: [[EXIT_LOOPEXIT]]:134; CHECK-NEXT: br label %[[EXIT]]135; CHECK: [[EXIT]]:136; CHECK-NEXT: ret void137;138entry:139 %tc.add = add nuw i64 %tc, 1140 %guard = icmp ugt i64 %tc, 1024141 br i1 %guard, label %exit, label %loop142loop:143 %i = phi i64 [%i.next, %loop], [0, %entry]144 %gep = getelementptr i64, ptr %p, i64 %i145 %x = load i64, ptr %gep146 %y = add i64 %x, 1147 store i64 %y, ptr %gep148 %i.next = add i64 %i, 1149 %done = icmp eq i64 %i.next, %tc.add150 br i1 %done, label %exit, label %loop151exit:152 ret void153}154;.155; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}156; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}157; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}158; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}159; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}160;.161