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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=loop-vectorize \3; RUN: -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue \4; RUN: -mtriple=riscv64 -mattr=+v -S < %s | FileCheck %s --check-prefix=IF-EVL5 6; RUN: opt -passes=loop-vectorize \7; RUN: -prefer-predicate-over-epilogue=scalar-epilogue \8; RUN: -mtriple=riscv64 -mattr=+v -S < %s | FileCheck %s --check-prefix=NO-VP9 10; Dependence distance between read and write is greater than the trip11; count of the loop. Thus, values written are never read for any12; valid vectorization of the loop.13define void @test(ptr %p) {14; IF-EVL-LABEL: @test(15; IF-EVL-NEXT: entry:16; IF-EVL-NEXT: br label [[VECTOR_PH:%.*]]17; IF-EVL: vector.ph:18; IF-EVL-NEXT: br label [[VECTOR_BODY:%.*]]19; IF-EVL: vector.body:20; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]21; IF-EVL-NEXT: [[TMP5:%.*]] = phi i64 [ 200, [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]22; IF-EVL-NEXT: [[TMP6:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[TMP5]], i32 2, i1 true)23; IF-EVL-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[P:%.*]], i64 [[EVL_BASED_IV]]24; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP8]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP6]])25; IF-EVL-NEXT: [[TMP10:%.*]] = add i64 [[EVL_BASED_IV]], 20026; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[P]], i64 [[TMP10]]27; IF-EVL-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[VP_OP_LOAD]], ptr align 8 [[TMP11]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP6]])28; IF-EVL-NEXT: [[TMP13:%.*]] = zext i32 [[TMP6]] to i6429; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP13]], [[EVL_BASED_IV]]30; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[TMP5]], [[TMP13]]31; IF-EVL-NEXT: [[TMP12:%.*]] = icmp eq i64 [[AVL_NEXT]], 032; IF-EVL-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]33; IF-EVL: middle.block:34; IF-EVL-NEXT: br label [[LOOP:%.*]]35; IF-EVL: exit:36; IF-EVL-NEXT: ret void37;38; NO-VP-LABEL: @test(39; NO-VP-NEXT: entry:40; NO-VP-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()41; NO-VP-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 142; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 200, [[TMP1]]43; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[ENTRY:%.*]]44; NO-VP: vector.ph:45; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()46; NO-VP-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 247; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 200, [[TMP3]]48; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 200, [[N_MOD_VF]]49; NO-VP-NEXT: br label [[LOOP:%.*]]50; NO-VP: vector.body:51; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]52; NO-VP-NEXT: [[A1:%.*]] = getelementptr i64, ptr [[P:%.*]], i64 [[IV]]53; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[A1]], align 854; NO-VP-NEXT: [[TMP7:%.*]] = add i64 [[IV]], 20055; NO-VP-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[P]], i64 [[TMP7]]56; NO-VP-NEXT: store <vscale x 2 x i64> [[WIDE_LOAD]], ptr [[TMP8]], align 857; NO-VP-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], [[TMP3]]58; NO-VP-NEXT: [[TMP9:%.*]] = icmp eq i64 [[IV_NEXT]], [[N_VEC]]59; NO-VP-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[LOOP]], !llvm.loop [[LOOP0:![0-9]+]]60; NO-VP: middle.block:61; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 200, [[N_VEC]]62; NO-VP-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]63; NO-VP: scalar.ph:64; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY1:%.*]] ]65; NO-VP-NEXT: br label [[LOOP1:%.*]]66; NO-VP: loop:67; NO-VP-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT1:%.*]], [[LOOP1]] ]68; NO-VP-NEXT: [[A3:%.*]] = getelementptr i64, ptr [[P]], i64 [[IV1]]69; NO-VP-NEXT: [[V:%.*]] = load i64, ptr [[A3]], align 870; NO-VP-NEXT: [[OFFSET:%.*]] = add i64 [[IV1]], 20071; NO-VP-NEXT: [[A2:%.*]] = getelementptr i64, ptr [[P]], i64 [[OFFSET]]72; NO-VP-NEXT: store i64 [[V]], ptr [[A2]], align 873; NO-VP-NEXT: [[IV_NEXT1]] = add i64 [[IV1]], 174; NO-VP-NEXT: [[CMP:%.*]] = icmp ne i64 [[IV1]], 19975; NO-VP-NEXT: br i1 [[CMP]], label [[LOOP1]], label [[EXIT]], !llvm.loop [[LOOP3:![0-9]+]]76; NO-VP: exit:77; NO-VP-NEXT: ret void78;79entry:80 br label %loop81 82loop:83 %iv = phi i64 [0, %entry], [%iv.next, %loop]84 %a1 = getelementptr i64, ptr %p, i64 %iv85 %v = load i64, ptr %a1, align 886 %offset = add i64 %iv, 20087 %a2 = getelementptr i64, ptr %p, i64 %offset88 store i64 %v, ptr %a2, align 889 %iv.next = add i64 %iv, 190 %cmp = icmp ne i64 %iv, 19991 br i1 %cmp, label %loop, label %exit92 93exit:94 ret void95}96 97; Dependence distance is less than trip count, thus we must prove that98; chosen VF guaranteed to be less than dependence distance.99define void @test_may_clobber1(ptr %p) {100; IF-EVL-LABEL: @test_may_clobber1(101; IF-EVL-NEXT: entry:102; IF-EVL-NEXT: br label [[VECTOR_PH:%.*]]103; IF-EVL: vector.ph:104; IF-EVL-NEXT: br label [[VECTOR_BODY:%.*]]105; IF-EVL: vector.body:106; IF-EVL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]107; IF-EVL-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr [[P:%.*]], i64 [[INDEX]]108; IF-EVL-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 32109; IF-EVL-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 100110; IF-EVL-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[P]], i64 [[TMP3]]111; IF-EVL-NEXT: store <4 x i64> [[WIDE_LOAD]], ptr [[TMP4]], align 32112; IF-EVL-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4113; IF-EVL-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200114; IF-EVL-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]115; IF-EVL: middle.block:116; IF-EVL-NEXT: br label [[LOOP:%.*]]117; IF-EVL: exit:118; IF-EVL-NEXT: ret void119;120; NO-VP-LABEL: @test_may_clobber1(121; NO-VP-NEXT: entry:122; NO-VP-NEXT: br label [[VECTOR_PH:%.*]]123; NO-VP: vector.ph:124; NO-VP-NEXT: br label [[VECTOR_BODY:%.*]]125; NO-VP: vector.body:126; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]127; NO-VP-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr [[P:%.*]], i64 [[INDEX]]128; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 32129; NO-VP-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 100130; NO-VP-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[P]], i64 [[TMP3]]131; NO-VP-NEXT: store <4 x i64> [[WIDE_LOAD]], ptr [[TMP4]], align 32132; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4133; NO-VP-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200134; NO-VP-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]135; NO-VP: middle.block:136; NO-VP-NEXT: br label [[LOOP:%.*]]137; NO-VP: exit:138; NO-VP-NEXT: ret void139;140entry:141 br label %loop142 143loop:144 %iv = phi i64 [0, %entry], [%iv.next, %loop]145 %a1 = getelementptr i64, ptr %p, i64 %iv146 %v = load i64, ptr %a1, align 32147 %offset = add i64 %iv, 100148 %a2 = getelementptr i64, ptr %p, i64 %offset149 store i64 %v, ptr %a2, align 32150 %iv.next = add i64 %iv, 1151 %cmp = icmp ne i64 %iv, 199152 br i1 %cmp, label %loop, label %exit153 154exit:155 ret void156}157 158define void @test_may_clobber2(ptr %p) {159; IF-EVL-LABEL: @test_may_clobber2(160; IF-EVL-NEXT: entry:161; IF-EVL-NEXT: br label [[LOOP:%.*]]162; IF-EVL: loop:163; IF-EVL-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]164; IF-EVL-NEXT: [[A1:%.*]] = getelementptr i64, ptr [[P:%.*]], i64 [[IV]]165; IF-EVL-NEXT: [[V:%.*]] = load i64, ptr [[A1]], align 32166; IF-EVL-NEXT: [[OFFSET:%.*]] = add i64 [[IV]], 9167; IF-EVL-NEXT: [[A2:%.*]] = getelementptr i64, ptr [[P]], i64 [[OFFSET]]168; IF-EVL-NEXT: store i64 [[V]], ptr [[A2]], align 32169; IF-EVL-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1170; IF-EVL-NEXT: [[CMP:%.*]] = icmp ne i64 [[IV]], 199171; IF-EVL-NEXT: br i1 [[CMP]], label [[LOOP]], label [[EXIT:%.*]]172; IF-EVL: exit:173; IF-EVL-NEXT: ret void174;175; NO-VP-LABEL: @test_may_clobber2(176; NO-VP-NEXT: entry:177; NO-VP-NEXT: br label [[LOOP:%.*]]178; NO-VP: loop:179; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]180; NO-VP-NEXT: [[A1:%.*]] = getelementptr i64, ptr [[P:%.*]], i64 [[IV]]181; NO-VP-NEXT: [[V:%.*]] = load i64, ptr [[A1]], align 32182; NO-VP-NEXT: [[OFFSET:%.*]] = add i64 [[IV]], 9183; NO-VP-NEXT: [[A2:%.*]] = getelementptr i64, ptr [[P]], i64 [[OFFSET]]184; NO-VP-NEXT: store i64 [[V]], ptr [[A2]], align 32185; NO-VP-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1186; NO-VP-NEXT: [[CMP:%.*]] = icmp ne i64 [[IV]], 199187; NO-VP-NEXT: br i1 [[CMP]], label [[LOOP]], label [[EXIT:%.*]]188; NO-VP: exit:189; NO-VP-NEXT: ret void190;191entry:192 br label %loop193 194loop:195 %iv = phi i64 [0, %entry], [%iv.next, %loop]196 %a1 = getelementptr i64, ptr %p, i64 %iv197 %v = load i64, ptr %a1, align 32198 %offset = add i64 %iv, 9199 %a2 = getelementptr i64, ptr %p, i64 %offset200 store i64 %v, ptr %a2, align 32201 %iv.next = add i64 %iv, 1202 %cmp = icmp ne i64 %iv, 199203 br i1 %cmp, label %loop, label %exit204 205exit:206 ret void207}208 209define void @test_may_clobber3(ptr %p) {210; IF-EVL-LABEL: @test_may_clobber3(211; IF-EVL-NEXT: entry:212; IF-EVL-NEXT: br label [[VECTOR_PH:%.*]]213; IF-EVL: vector.ph:214; IF-EVL-NEXT: br label [[VECTOR_BODY:%.*]]215; IF-EVL: vector.body:216; IF-EVL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]217; IF-EVL-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr [[P:%.*]], i64 [[INDEX]]218; IF-EVL-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP1]], align 32219; IF-EVL-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 10220; IF-EVL-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[P]], i64 [[TMP3]]221; IF-EVL-NEXT: store <2 x i64> [[WIDE_LOAD]], ptr [[TMP4]], align 32222; IF-EVL-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2223; IF-EVL-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200224; IF-EVL-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]225; IF-EVL: middle.block:226; IF-EVL-NEXT: br label [[LOOP:%.*]]227; IF-EVL: exit:228; IF-EVL-NEXT: ret void229;230; NO-VP-LABEL: @test_may_clobber3(231; NO-VP-NEXT: entry:232; NO-VP-NEXT: br label [[VECTOR_PH:%.*]]233; NO-VP: vector.ph:234; NO-VP-NEXT: br label [[VECTOR_BODY:%.*]]235; NO-VP: vector.body:236; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]237; NO-VP-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr [[P:%.*]], i64 [[INDEX]]238; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP1]], align 32239; NO-VP-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 10240; NO-VP-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[P]], i64 [[TMP3]]241; NO-VP-NEXT: store <2 x i64> [[WIDE_LOAD]], ptr [[TMP4]], align 32242; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2243; NO-VP-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200244; NO-VP-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]245; NO-VP: middle.block:246; NO-VP-NEXT: br label [[LOOP:%.*]]247; NO-VP: exit:248; NO-VP-NEXT: ret void249;250entry:251 br label %loop252 253loop:254 %iv = phi i64 [0, %entry], [%iv.next, %loop]255 %a1 = getelementptr i64, ptr %p, i64 %iv256 %v = load i64, ptr %a1, align 32257 %offset = add i64 %iv, 10258 %a2 = getelementptr i64, ptr %p, i64 %offset259 store i64 %v, ptr %a2, align 32260 %iv.next = add i64 %iv, 1261 %cmp = icmp ne i64 %iv, 199262 br i1 %cmp, label %loop, label %exit263 264exit:265 ret void266}267 268; Trviailly no overlap due to maximum possible value of VLEN and LMUL269define void @trivial_due_max_vscale(ptr %p) {270; IF-EVL-LABEL: @trivial_due_max_vscale(271; IF-EVL-NEXT: entry:272; IF-EVL-NEXT: br label [[VECTOR_PH:%.*]]273; IF-EVL: vector.ph:274; IF-EVL-NEXT: br label [[VECTOR_BODY:%.*]]275; IF-EVL: vector.body:276; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]277; IF-EVL-NEXT: [[TMP5:%.*]] = phi i64 [ 200, [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]278; IF-EVL-NEXT: [[TMP6:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[TMP5]], i32 2, i1 true)279; IF-EVL-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[P:%.*]], i64 [[EVL_BASED_IV]]280; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 32 [[TMP8]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP6]])281; IF-EVL-NEXT: [[TMP10:%.*]] = add i64 [[EVL_BASED_IV]], 8192282; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[P]], i64 [[TMP10]]283; IF-EVL-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[VP_OP_LOAD]], ptr align 32 [[TMP11]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP6]])284; IF-EVL-NEXT: [[TMP13:%.*]] = zext i32 [[TMP6]] to i64285; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP13]], [[EVL_BASED_IV]]286; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[TMP5]], [[TMP13]]287; IF-EVL-NEXT: [[TMP12:%.*]] = icmp eq i64 [[AVL_NEXT]], 0288; IF-EVL-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]289; IF-EVL: middle.block:290; IF-EVL-NEXT: br label [[LOOP:%.*]]291; IF-EVL: exit:292; IF-EVL-NEXT: ret void293;294; NO-VP-LABEL: @trivial_due_max_vscale(295; NO-VP-NEXT: entry:296; NO-VP-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()297; NO-VP-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 1298; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 200, [[TMP1]]299; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[ENTRY:%.*]]300; NO-VP: vector.ph:301; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()302; NO-VP-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 2303; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 200, [[TMP3]]304; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 200, [[N_MOD_VF]]305; NO-VP-NEXT: br label [[LOOP:%.*]]306; NO-VP: vector.body:307; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]308; NO-VP-NEXT: [[A1:%.*]] = getelementptr i64, ptr [[P:%.*]], i64 [[IV]]309; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[A1]], align 32310; NO-VP-NEXT: [[TMP7:%.*]] = add i64 [[IV]], 8192311; NO-VP-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[P]], i64 [[TMP7]]312; NO-VP-NEXT: store <vscale x 2 x i64> [[WIDE_LOAD]], ptr [[TMP8]], align 32313; NO-VP-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], [[TMP3]]314; NO-VP-NEXT: [[TMP9:%.*]] = icmp eq i64 [[IV_NEXT]], [[N_VEC]]315; NO-VP-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]316; NO-VP: middle.block:317; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 200, [[N_VEC]]318; NO-VP-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]319; NO-VP: scalar.ph:320; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY1:%.*]] ]321; NO-VP-NEXT: br label [[LOOP1:%.*]]322; NO-VP: loop:323; NO-VP-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT1:%.*]], [[LOOP1]] ]324; NO-VP-NEXT: [[A3:%.*]] = getelementptr i64, ptr [[P]], i64 [[IV1]]325; NO-VP-NEXT: [[V:%.*]] = load i64, ptr [[A3]], align 32326; NO-VP-NEXT: [[OFFSET:%.*]] = add i64 [[IV1]], 8192327; NO-VP-NEXT: [[A2:%.*]] = getelementptr i64, ptr [[P]], i64 [[OFFSET]]328; NO-VP-NEXT: store i64 [[V]], ptr [[A2]], align 32329; NO-VP-NEXT: [[IV_NEXT1]] = add i64 [[IV1]], 1330; NO-VP-NEXT: [[CMP:%.*]] = icmp ne i64 [[IV1]], 199331; NO-VP-NEXT: br i1 [[CMP]], label [[LOOP1]], label [[EXIT]], !llvm.loop [[LOOP7:![0-9]+]]332; NO-VP: exit:333; NO-VP-NEXT: ret void334;335entry:336 br label %loop337 338loop:339 %iv = phi i64 [0, %entry], [%iv.next, %loop]340 %a1 = getelementptr i64, ptr %p, i64 %iv341 %v = load i64, ptr %a1, align 32342 %offset = add i64 %iv, 8192343 %a2 = getelementptr i64, ptr %p, i64 %offset344 store i64 %v, ptr %a2, align 32345 %iv.next = add i64 %iv, 1346 %cmp = icmp ne i64 %iv, 199347 br i1 %cmp, label %loop, label %exit348 349exit:350 ret void351}352 353; Dependence distance could be violated via LMUL>=2 or interleaving354define void @no_high_lmul_or_interleave(ptr %p) {355; IF-EVL-LABEL: @no_high_lmul_or_interleave(356; IF-EVL-NEXT: entry:357; IF-EVL-NEXT: br label [[VECTOR_PH:%.*]]358; IF-EVL: vector.ph:359; IF-EVL-NEXT: br label [[VECTOR_BODY:%.*]]360; IF-EVL: vector.body:361; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]362; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ 3002, [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]363; IF-EVL-NEXT: [[TMP9:%.*]] = icmp ult i64 [[AVL]], 1024364; IF-EVL-NEXT: [[SAFE_AVL:%.*]] = select i1 [[TMP9]], i64 [[AVL]], i64 1024365; IF-EVL-NEXT: [[TMP10:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[SAFE_AVL]], i32 1, i1 true)366; IF-EVL-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[P:%.*]], i64 [[EVL_BASED_IV]]367; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 1 x i64> @llvm.vp.load.nxv1i64.p0(ptr align 32 [[TMP2]], <vscale x 1 x i1> splat (i1 true), i32 [[TMP10]])368; IF-EVL-NEXT: [[TMP4:%.*]] = add i64 [[EVL_BASED_IV]], 1024369; IF-EVL-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[P]], i64 [[TMP4]]370; IF-EVL-NEXT: call void @llvm.vp.store.nxv1i64.p0(<vscale x 1 x i64> [[VP_OP_LOAD]], ptr align 32 [[TMP5]], <vscale x 1 x i1> splat (i1 true), i32 [[TMP10]])371; IF-EVL-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64372; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP11]], [[EVL_BASED_IV]]373; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP11]]374; IF-EVL-NEXT: [[TMP12:%.*]] = icmp eq i64 [[AVL_NEXT]], 0375; IF-EVL-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]376; IF-EVL: middle.block:377; IF-EVL-NEXT: br label [[LOOP:%.*]]378; IF-EVL: exit:379; IF-EVL-NEXT: ret void380;381; NO-VP-LABEL: @no_high_lmul_or_interleave(382; NO-VP-NEXT: entry:383; NO-VP-NEXT: br label [[ENTRY:%.*]]384; NO-VP: vector.ph:385; NO-VP-NEXT: br label [[LOOP:%.*]]386; NO-VP: vector.body:387; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]388; NO-VP-NEXT: [[A1:%.*]] = getelementptr i64, ptr [[P:%.*]], i64 [[IV]]389; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[A1]], align 32390; NO-VP-NEXT: [[TMP1:%.*]] = add i64 [[IV]], 1024391; NO-VP-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[P]], i64 [[TMP1]]392; NO-VP-NEXT: store <4 x i64> [[WIDE_LOAD]], ptr [[TMP2]], align 32393; NO-VP-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 4394; NO-VP-NEXT: [[TMP3:%.*]] = icmp eq i64 [[IV_NEXT]], 3000395; NO-VP-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]396; NO-VP: middle.block:397; NO-VP-NEXT: br label [[SCALAR_PH:%.*]]398; NO-VP: scalar.ph:399; NO-VP-NEXT: br label [[LOOP1:%.*]]400; NO-VP: loop:401; NO-VP-NEXT: [[IV1:%.*]] = phi i64 [ 3000, [[SCALAR_PH]] ], [ [[IV_NEXT1:%.*]], [[LOOP1]] ]402; NO-VP-NEXT: [[A3:%.*]] = getelementptr i64, ptr [[P]], i64 [[IV1]]403; NO-VP-NEXT: [[V:%.*]] = load i64, ptr [[A3]], align 32404; NO-VP-NEXT: [[OFFSET:%.*]] = add i64 [[IV1]], 1024405; NO-VP-NEXT: [[A2:%.*]] = getelementptr i64, ptr [[P]], i64 [[OFFSET]]406; NO-VP-NEXT: store i64 [[V]], ptr [[A2]], align 32407; NO-VP-NEXT: [[IV_NEXT1]] = add i64 [[IV1]], 1408; NO-VP-NEXT: [[CMP:%.*]] = icmp ne i64 [[IV1]], 3001409; NO-VP-NEXT: br i1 [[CMP]], label [[LOOP1]], label [[EXIT:%.*]], !llvm.loop [[LOOP9:![0-9]+]]410; NO-VP: exit:411; NO-VP-NEXT: ret void412;413entry:414 br label %loop415 416loop:417 %iv = phi i64 [0, %entry], [%iv.next, %loop]418 %a1 = getelementptr i64, ptr %p, i64 %iv419 %v = load i64, ptr %a1, align 32420 %offset = add i64 %iv, 1024421 %a2 = getelementptr i64, ptr %p, i64 %offset422 store i64 %v, ptr %a2, align 32423 %iv.next = add i64 %iv, 1424 %cmp = icmp ne i64 %iv, 3001425 br i1 %cmp, label %loop, label %exit426 427exit:428 ret void429}430 431define void @non-power-2-storeloadforward(ptr %A) {432; IF-EVL-LABEL: @non-power-2-storeloadforward(433; IF-EVL-NEXT: entry:434; IF-EVL-NEXT: br label [[FOR_BODY:%.*]]435; IF-EVL: for.body:436; IF-EVL-NEXT: [[IV:%.*]] = phi i64 [ 16, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]437; IF-EVL-NEXT: [[TMP0:%.*]] = add nsw i64 [[IV]], -3438; IF-EVL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[TMP0]]439; IF-EVL-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4440; IF-EVL-NEXT: [[TMP2:%.*]] = add nsw i64 [[IV]], 4441; IF-EVL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP2]]442; IF-EVL-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4443; IF-EVL-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], [[TMP1]]444; IF-EVL-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]445; IF-EVL-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX5]], align 4446; IF-EVL-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1447; IF-EVL-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[IV_NEXT]] to i32448; IF-EVL-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[LFTR_WIDEIV]], 128449; IF-EVL-NEXT: br i1 [[EXITCOND]], label [[FOR_BODY]], label [[FOR_END:%.*]]450; IF-EVL: for.end:451; IF-EVL-NEXT: ret void452;453; NO-VP-LABEL: @non-power-2-storeloadforward(454; NO-VP-NEXT: entry:455; NO-VP-NEXT: br label [[FOR_BODY:%.*]]456; NO-VP: for.body:457; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ 16, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]458; NO-VP-NEXT: [[TMP0:%.*]] = add nsw i64 [[IV]], -3459; NO-VP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[TMP0]]460; NO-VP-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4461; NO-VP-NEXT: [[TMP2:%.*]] = add nsw i64 [[IV]], 4462; NO-VP-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP2]]463; NO-VP-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4464; NO-VP-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], [[TMP1]]465; NO-VP-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]466; NO-VP-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX5]], align 4467; NO-VP-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1468; NO-VP-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[IV_NEXT]] to i32469; NO-VP-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[LFTR_WIDEIV]], 128470; NO-VP-NEXT: br i1 [[EXITCOND]], label [[FOR_BODY]], label [[FOR_END:%.*]]471; NO-VP: for.end:472; NO-VP-NEXT: ret void473;474entry:475 br label %for.body476 477for.body:478 %iv = phi i64 [ 16, %entry ], [ %iv.next, %for.body ]479 %0 = add nsw i64 %iv, -3480 %arrayidx = getelementptr inbounds i32, ptr %A, i64 %0481 %1 = load i32, ptr %arrayidx, align 4482 %2 = add nsw i64 %iv, 4483 %arrayidx2 = getelementptr inbounds i32, ptr %A, i64 %2484 %3 = load i32, ptr %arrayidx2, align 4485 %add3 = add nsw i32 %3, %1486 %arrayidx5 = getelementptr inbounds i32, ptr %A, i64 %iv487 store i32 %add3, ptr %arrayidx5, align 4488 %iv.next = add i64 %iv, 1489 %lftr.wideiv = trunc i64 %iv.next to i32490 %exitcond = icmp ne i32 %lftr.wideiv, 128491 br i1 %exitcond, label %for.body, label %for.end492 493for.end:494 ret void495}496 497