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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt < %s --prefer-predicate-over-epilogue=predicate-else-scalar-epilogue --passes=loop-vectorize -mcpu=sifive-p470 -mattr=+v,+f -S | FileCheck %s3; Generated from issue #109468.4; In this test case, the vector store with tail mask will transfer to the vp intrinsic with EVL.5 6target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"7target triple = "riscv64-unknown-linux-gnu"8 9define void @lshift_significand(i32 %n, ptr nocapture writeonly %dst) {10; CHECK-LABEL: define void @lshift_significand(11; CHECK-SAME: i32 [[N:%.*]], ptr writeonly captures(none) [[DST:%.*]]) #[[ATTR0:[0-9]+]] {12; CHECK-NEXT: [[ENTRY:.*:]]13; CHECK-NEXT: [[CMP1_PEEL:%.*]] = icmp eq i32 [[N]], 014; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[CMP1_PEEL]], i64 2, i64 015; CHECK-NEXT: [[TMP0:%.*]] = sub i64 3, [[SPEC_SELECT]]16; CHECK-NEXT: br label %[[VECTOR_PH:.*]]17; CHECK: [[VECTOR_PH]]:18; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]19; CHECK: [[VECTOR_BODY]]:20; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]21; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP0]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]22; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)23; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[SPEC_SELECT]], [[EVL_BASED_IV]]24; CHECK-NEXT: [[TMP12:%.*]] = sub nuw nsw i64 1, [[OFFSET_IDX]]25; CHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP12]]26; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP11]] to i6427; CHECK-NEXT: [[TMP16:%.*]] = mul i64 0, [[TMP15]]28; CHECK-NEXT: [[TMP23:%.*]] = sub i64 [[TMP15]], 129; CHECK-NEXT: [[TMP17:%.*]] = mul i64 -1, [[TMP23]]30; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i64, ptr [[ARRAYIDX13]], i64 [[TMP16]]31; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i64, ptr [[TMP18]], i64 [[TMP17]]32; CHECK-NEXT: [[VP_REVERSE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vp.reverse.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), i32 [[TMP11]])33; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[VP_REVERSE]], ptr align 8 [[TMP19]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP11]])34; CHECK-NEXT: [[TMP20:%.*]] = zext i32 [[TMP11]] to i6435; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP20]], [[EVL_BASED_IV]]36; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP20]]37; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i64 [[AVL_NEXT]], 038; CHECK-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]39; CHECK: [[MIDDLE_BLOCK]]:40; CHECK-NEXT: br label %[[EXIT:.*]]41; CHECK: [[EXIT]]:42; CHECK-NEXT: ret void43;44entry:45 %cmp1.peel = icmp eq i32 %n, 046 %spec.select = select i1 %cmp1.peel, i64 2, i64 047 br label %loop48 49loop:50 %iv = phi i64 [ %spec.select, %entry ], [ %iv.next, %loop ]51 %1 = sub nuw nsw i64 1, %iv52 %arrayidx13 = getelementptr i64, ptr %dst, i64 %153 store i64 0, ptr %arrayidx13, align 854 %iv.next = add nuw nsw i64 %iv, 155 %exitcond.not = icmp eq i64 %iv.next, 356 br i1 %exitcond.not, label %exit, label %loop, !llvm.loop !057 58exit:59 ret void60}61 62!0 = distinct !{!0, !1, !2, !3}63!1 = !{!"llvm.loop.vectorize.width", i32 2}64!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}65!3 = !{!"llvm.loop.vectorize.enable", i1 true}66